[mirror_ubuntu-bionic-kernel.git] / arch / ia64 / kernel / irq_ia64.c

/*
 * linux/arch/ia64/kernel/irq_ia64.c
 *
 * Copyright (C) 1998-2001 Hewlett-Packard Co
 *	Stephane Eranian <eranian@hpl.hp.com>
 *	David Mosberger-Tang <davidm@hpl.hp.com>
 *
 *  6/10/99: Updated to bring in sync with x86 version to facilitate
 *	     support for SMP and different interrupt controllers.
 *
 * 09/15/00 Goutham Rao <goutham.rao@intel.com> Implemented pci_irq_to_vector
 *                      PCI to vector allocation routine.
 * 04/14/2004 Ashok Raj <ashok.raj@intel.com>
 *						Added CPU Hotplug handling for IPF.
 */

#include <linux/module.h>

#include <linux/jiffies.h>
#include <linux/errno.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/kernel_stat.h>
#include <linux/ptrace.h>
#include <linux/random.h>	/* for rand_initialize_irq() */
#include <linux/signal.h>
#include <linux/smp.h>
#include <linux/threads.h>
#include <linux/bitops.h>
#include <linux/irq.h>
#include <linux/ratelimit.h>
#include <linux/acpi.h>
#include <linux/sched.h>

#include <asm/delay.h>
#include <asm/intrinsics.h>
#include <asm/io.h>
#include <asm/hw_irq.h>
#include <asm/machvec.h>
#include <asm/pgtable.h>
#include <asm/system.h>
#include <asm/tlbflush.h>

#ifdef CONFIG_PERFMON
# include <asm/perfmon.h>
#endif

#define IRQ_DEBUG	0

#define IRQ_VECTOR_UNASSIGNED	(0)

#define IRQ_UNUSED		(0)
#define IRQ_USED		(1)
#define IRQ_RSVD		(2)

/* These can be overridden in platform_irq_init */
int ia64_first_device_vector = IA64_DEF_FIRST_DEVICE_VECTOR;
int ia64_last_device_vector = IA64_DEF_LAST_DEVICE_VECTOR;

/* default base addr of IPI table */
void __iomem *ipi_base_addr = ((void __iomem *)
			       (__IA64_UNCACHED_OFFSET | IA64_IPI_DEFAULT_BASE_ADDR));

static cpumask_t vector_allocation_domain(int cpu);

/*
 * Legacy IRQ to IA-64 vector translation table.
 */
__u8 isa_irq_to_vector_map[16] = {
	/* 8259 IRQ translation, first 16 entries */
	0x2f, 0x20, 0x2e, 0x2d, 0x2c, 0x2b, 0x2a, 0x29,
	0x28, 0x27, 0x26, 0x25, 0x24, 0x23, 0x22, 0x21
};
EXPORT_SYMBOL(isa_irq_to_vector_map);

DEFINE_SPINLOCK(vector_lock);

struct irq_cfg irq_cfg[NR_IRQS] __read_mostly = {
	[0 ... NR_IRQS - 1] = {
		.vector = IRQ_VECTOR_UNASSIGNED,
		.domain = CPU_MASK_NONE
	}
};

DEFINE_PER_CPU(int[IA64_NUM_VECTORS], vector_irq) = {
	[0 ... IA64_NUM_VECTORS - 1] = -1
};

static cpumask_t vector_table[IA64_NUM_VECTORS] = {
	[0 ... IA64_NUM_VECTORS - 1] = CPU_MASK_NONE
};

static int irq_status[NR_IRQS] = {
	[0 ... NR_IRQS -1] = IRQ_UNUSED
};

int check_irq_used(int irq)
{
	if (irq_status[irq] == IRQ_USED)
		return 1;

	return -1;
}

static inline int find_unassigned_irq(void)
{
	int irq;

	for (irq = IA64_FIRST_DEVICE_VECTOR; irq < NR_IRQS; irq++)
		if (irq_status[irq] == IRQ_UNUSED)
			return irq;
	return -ENOSPC;
}

static inline int find_unassigned_vector(cpumask_t domain)
{
	cpumask_t mask;
	int pos, vector;

	cpus_and(mask, domain, cpu_online_map);
	if (cpus_empty(mask))
		return -EINVAL;

	for (pos = 0; pos < IA64_NUM_DEVICE_VECTORS; pos++) {
		vector = IA64_FIRST_DEVICE_VECTOR + pos;
		cpus_and(mask, domain, vector_table[vector]);
		if (!cpus_empty(mask))
			continue;
		return vector;
	}
	return -ENOSPC;
}

static int __bind_irq_vector(int irq, int vector, cpumask_t domain)
{
	cpumask_t mask;
	int cpu;
	struct irq_cfg *cfg = &irq_cfg[irq];

	BUG_ON((unsigned)irq >= NR_IRQS);
	BUG_ON((unsigned)vector >= IA64_NUM_VECTORS);

	cpus_and(mask, domain, cpu_online_map);
	if (cpus_empty(mask))
		return -EINVAL;
	if ((cfg->vector == vector) && cpus_equal(cfg->domain, domain))
		return 0;
	if (cfg->vector != IRQ_VECTOR_UNASSIGNED)
		return -EBUSY;
	for_each_cpu_mask(cpu, mask)
		per_cpu(vector_irq, cpu)[vector] = irq;
	cfg->vector = vector;
	cfg->domain = domain;
	irq_status[irq] = IRQ_USED;
	cpus_or(vector_table[vector], vector_table[vector], domain);
	return 0;
}

int bind_irq_vector(int irq, int vector, cpumask_t domain)
{
	unsigned long flags;
	int ret;

	spin_lock_irqsave(&vector_lock, flags);
	ret = __bind_irq_vector(irq, vector, domain);
	spin_unlock_irqrestore(&vector_lock, flags);
	return ret;
}

static void __clear_irq_vector(int irq)
{
	int vector, cpu;
	cpumask_t mask;
	cpumask_t domain;
	struct irq_cfg *cfg = &irq_cfg[irq];

	BUG_ON((unsigned)irq >= NR_IRQS);
	BUG_ON(cfg->vector == IRQ_VECTOR_UNASSIGNED);
	vector = cfg->vector;
	domain = cfg->domain;
	cpus_and(mask, cfg->domain, cpu_online_map);
	for_each_cpu_mask(cpu, mask)
		per_cpu(vector_irq, cpu)[vector] = -1;
	cfg->vector = IRQ_VECTOR_UNASSIGNED;
	cfg->domain = CPU_MASK_NONE;
	irq_status[irq] = IRQ_UNUSED;
	cpus_andnot(vector_table[vector], vector_table[vector], domain);
}

static void clear_irq_vector(int irq)
{
	unsigned long flags;

	spin_lock_irqsave(&vector_lock, flags);
	__clear_irq_vector(irq);
	spin_unlock_irqrestore(&vector_lock, flags);
}

int
ia64_native_assign_irq_vector (int irq)
{
	unsigned long flags;
	int vector, cpu;
	cpumask_t domain = CPU_MASK_NONE;

	vector = -ENOSPC;

	spin_lock_irqsave(&vector_lock, flags);
	for_each_online_cpu(cpu) {
		domain = vector_allocation_domain(cpu);
		vector = find_unassigned_vector(domain);
		if (vector >= 0)
			break;
	}
	if (vector < 0)
		goto out;
	if (irq == AUTO_ASSIGN)
		irq = vector;
	BUG_ON(__bind_irq_vector(irq, vector, domain));
 out:
	spin_unlock_irqrestore(&vector_lock, flags);
	return vector;
}

void
ia64_native_free_irq_vector (int vector)
{
	if (vector < IA64_FIRST_DEVICE_VECTOR ||
	    vector > IA64_LAST_DEVICE_VECTOR)
		return;
	clear_irq_vector(vector);
}

int
reserve_irq_vector (int vector)
{
	if (vector < IA64_FIRST_DEVICE_VECTOR ||
	    vector > IA64_LAST_DEVICE_VECTOR)
		return -EINVAL;
	return !!bind_irq_vector(vector, vector, CPU_MASK_ALL);
}

/*
 * Initialize vector_irq on a new cpu. This function must be called
 * with vector_lock held.
 */
void __setup_vector_irq(int cpu)
{
	int irq, vector;

	/* Clear vector_irq */
	for (vector = 0; vector < IA64_NUM_VECTORS; ++vector)
		per_cpu(vector_irq, cpu)[vector] = -1;
	/* Mark the inuse vectors */
	for (irq = 0; irq < NR_IRQS; ++irq) {
		if (!cpu_isset(cpu, irq_cfg[irq].domain))
			continue;
		vector = irq_to_vector(irq);
		per_cpu(vector_irq, cpu)[vector] = irq;
	}
}

#if defined(CONFIG_SMP) && (defined(CONFIG_IA64_GENERIC) || defined(CONFIG_IA64_DIG))

static enum vector_domain_type {
	VECTOR_DOMAIN_NONE,
	VECTOR_DOMAIN_PERCPU
} vector_domain_type = VECTOR_DOMAIN_NONE;

static cpumask_t vector_allocation_domain(int cpu)
{
	if (vector_domain_type == VECTOR_DOMAIN_PERCPU)
		return cpumask_of_cpu(cpu);
	return CPU_MASK_ALL;
}

static int __irq_prepare_move(int irq, int cpu)
{
	struct irq_cfg *cfg = &irq_cfg[irq];
	int vector;
	cpumask_t domain;

	if (cfg->move_in_progress || cfg->move_cleanup_count)
		return -EBUSY;
	if (cfg->vector == IRQ_VECTOR_UNASSIGNED || !cpu_online(cpu))
		return -EINVAL;
	if (cpu_isset(cpu, cfg->domain))
		return 0;
	domain = vector_allocation_domain(cpu);
	vector = find_unassigned_vector(domain);
	if (vector < 0)
		return -ENOSPC;
	cfg->move_in_progress = 1;
	cfg->old_domain = cfg->domain;
	cfg->vector = IRQ_VECTOR_UNASSIGNED;
	cfg->domain = CPU_MASK_NONE;
	BUG_ON(__bind_irq_vector(irq, vector, domain));
	return 0;
}

int irq_prepare_move(int irq, int cpu)
{
	unsigned long flags;
	int ret;

	spin_lock_irqsave(&vector_lock, flags);
	ret = __irq_prepare_move(irq, cpu);
	spin_unlock_irqrestore(&vector_lock, flags);
	return ret;
}

void irq_complete_move(unsigned irq)
{
	struct irq_cfg *cfg = &irq_cfg[irq];
	cpumask_t cleanup_mask;
	int i;

	if (likely(!cfg->move_in_progress))
		return;

	if (unlikely(cpu_isset(smp_processor_id(), cfg->old_domain)))
		return;

	cpus_and(cleanup_mask, cfg->old_domain, cpu_online_map);
	cfg->move_cleanup_count = cpus_weight(cleanup_mask);
	for_each_cpu_mask(i, cleanup_mask)
		platform_send_ipi(i, IA64_IRQ_MOVE_VECTOR, IA64_IPI_DM_INT, 0);
	cfg->move_in_progress = 0;
}

static irqreturn_t smp_irq_move_cleanup_interrupt(int irq, void *dev_id)
{
	int me = smp_processor_id();
	ia64_vector vector;
	unsigned long flags;

	for (vector = IA64_FIRST_DEVICE_VECTOR;
	     vector < IA64_LAST_DEVICE_VECTOR; vector++) {
		int irq;
		struct irq_desc *desc;
		struct irq_cfg *cfg;
		irq = __get_cpu_var(vector_irq)[vector];
		if (irq < 0)
			continue;

		desc = irq_to_desc(irq);
		cfg = irq_cfg + irq;
		raw_spin_lock(&desc->lock);
		if (!cfg->move_cleanup_count)
			goto unlock;

		if (!cpu_isset(me, cfg->old_domain))
			goto unlock;

		spin_lock_irqsave(&vector_lock, flags);
		__get_cpu_var(vector_irq)[vector] = -1;
		cpu_clear(me, vector_table[vector]);
		spin_unlock_irqrestore(&vector_lock, flags);
		cfg->move_cleanup_count--;
	unlock:
		raw_spin_unlock(&desc->lock);
	}
	return IRQ_HANDLED;
}

static struct irqaction irq_move_irqaction = {
	.handler =	smp_irq_move_cleanup_interrupt,
	.flags =	IRQF_DISABLED,
	.name =		"irq_move"
};

static int __init parse_vector_domain(char *arg)
{
	if (!arg)
		return -EINVAL;
	if (!strcmp(arg, "percpu")) {
		vector_domain_type = VECTOR_DOMAIN_PERCPU;
		no_int_routing = 1;
	}
	return 0;
}
early_param("vector", parse_vector_domain);
#else
static cpumask_t vector_allocation_domain(int cpu)
{
	return CPU_MASK_ALL;
}
#endif


void destroy_and_reserve_irq(unsigned int irq)
{
	unsigned long flags;

	dynamic_irq_cleanup(irq);

	spin_lock_irqsave(&vector_lock, flags);
	__clear_irq_vector(irq);
	irq_status[irq] = IRQ_RSVD;
	spin_unlock_irqrestore(&vector_lock, flags);
}

/*
 * Dynamic irq allocate and deallocation for MSI
 */
int create_irq(void)
{
	unsigned long flags;
	int irq, vector, cpu;
	cpumask_t domain = CPU_MASK_NONE;

	irq = vector = -ENOSPC;
	spin_lock_irqsave(&vector_lock, flags);
	for_each_online_cpu(cpu) {
		domain = vector_allocation_domain(cpu);
		vector = find_unassigned_vector(domain);
		if (vector >= 0)
			break;
	}
	if (vector < 0)
		goto out;
	irq = find_unassigned_irq();
	if (irq < 0)
		goto out;
	BUG_ON(__bind_irq_vector(irq, vector, domain));
 out:
	spin_unlock_irqrestore(&vector_lock, flags);
	if (irq >= 0)
		dynamic_irq_init(irq);
	return irq;
}

void destroy_irq(unsigned int irq)
{
	dynamic_irq_cleanup(irq);
	clear_irq_vector(irq);
}

#ifdef CONFIG_SMP
#	define IS_RESCHEDULE(vec)	(vec == IA64_IPI_RESCHEDULE)
#	define IS_LOCAL_TLB_FLUSH(vec)	(vec == IA64_IPI_LOCAL_TLB_FLUSH)
#else
#	define IS_RESCHEDULE(vec)	(0)
#	define IS_LOCAL_TLB_FLUSH(vec)	(0)
#endif
/*
 * That's where the IVT branches when we get an external
 * interrupt. This branches to the correct hardware IRQ handler via
 * function ptr.
 */
void
ia64_handle_irq (ia64_vector vector, struct pt_regs *regs)
{
	struct pt_regs *old_regs = set_irq_regs(regs);
	unsigned long saved_tpr;

#if IRQ_DEBUG
	{
		unsigned long bsp, sp;

		/*
		 * Note: if the interrupt happened while executing in
		 * the context switch routine (ia64_switch_to), we may
		 * get a spurious stack overflow here.  This is
		 * because the register and the memory stack are not
		 * switched atomically.
		 */
		bsp = ia64_getreg(_IA64_REG_AR_BSP);
		sp = ia64_getreg(_IA64_REG_SP);

		if ((sp - bsp) < 1024) {
			static DEFINE_RATELIMIT_STATE(ratelimit, 5 * HZ, 5);

			if (__ratelimit(&ratelimit)) {
				printk("ia64_handle_irq: DANGER: less than "
				       "1KB of free stack space!!\n"
				       "(bsp=0x%lx, sp=%lx)\n", bsp, sp);
			}
		}
	}
#endif /* IRQ_DEBUG */

	/*
	 * Always set TPR to limit maximum interrupt nesting depth to
	 * 16 (without this, it would be ~240, which could easily lead
	 * to kernel stack overflows).
	 */
	irq_enter();
	saved_tpr = ia64_getreg(_IA64_REG_CR_TPR);
	ia64_srlz_d();
	while (vector != IA64_SPURIOUS_INT_VECTOR) {
		int irq = local_vector_to_irq(vector);
		struct irq_desc *desc = irq_to_desc(irq);

		if (unlikely(IS_LOCAL_TLB_FLUSH(vector))) {
			smp_local_flush_tlb();
			kstat_incr_irqs_this_cpu(irq, desc);
		} else if (unlikely(IS_RESCHEDULE(vector))) {
			scheduler_ipi();
			kstat_incr_irqs_this_cpu(irq, desc);
		} else {
			ia64_setreg(_IA64_REG_CR_TPR, vector);
			ia64_srlz_d();

			if (unlikely(irq < 0)) {
				printk(KERN_ERR "%s: Unexpected interrupt "
				       "vector %d on CPU %d is not mapped "
				       "to any IRQ!\n", __func__, vector,
				       smp_processor_id());
			} else
				generic_handle_irq(irq);

			/*
			 * Disable interrupts and send EOI:
			 */
			local_irq_disable();
			ia64_setreg(_IA64_REG_CR_TPR, saved_tpr);
		}
		ia64_eoi();
		vector = ia64_get_ivr();
	}
	/*
	 * This must be done *after* the ia64_eoi().  For example, the keyboard softirq
	 * handler needs to be able to wait for further keyboard interrupts, which can't
	 * come through until ia64_eoi() has been done.
	 */
	irq_exit();
	set_irq_regs(old_regs);
}

#ifdef CONFIG_HOTPLUG_CPU
/*
 * This function emulates a interrupt processing when a cpu is about to be
 * brought down.
 */
void ia64_process_pending_intr(void)
{
	ia64_vector vector;
	unsigned long saved_tpr;
	extern unsigned int vectors_in_migration[NR_IRQS];

	vector = ia64_get_ivr();

	irq_enter();
	saved_tpr = ia64_getreg(_IA64_REG_CR_TPR);
	ia64_srlz_d();

	 /*
	  * Perform normal interrupt style processing
	  */
	while (vector != IA64_SPURIOUS_INT_VECTOR) {
		int irq = local_vector_to_irq(vector);
		struct irq_desc *desc = irq_to_desc(irq);

		if (unlikely(IS_LOCAL_TLB_FLUSH(vector))) {
			smp_local_flush_tlb();
			kstat_incr_irqs_this_cpu(irq, desc);
		} else if (unlikely(IS_RESCHEDULE(vector))) {
			kstat_incr_irqs_this_cpu(irq, desc);
		} else {
			struct pt_regs *old_regs = set_irq_regs(NULL);

			ia64_setreg(_IA64_REG_CR_TPR, vector);
			ia64_srlz_d();

			/*
			 * Now try calling normal ia64_handle_irq as it would have got called
			 * from a real intr handler. Try passing null for pt_regs, hopefully
			 * it will work. I hope it works!.
			 * Probably could shared code.
			 */
			if (unlikely(irq < 0)) {
				printk(KERN_ERR "%s: Unexpected interrupt "
				       "vector %d on CPU %d not being mapped "
				       "to any IRQ!!\n", __func__, vector,
				       smp_processor_id());
			} else {
				vectors_in_migration[irq]=0;
				generic_handle_irq(irq);
			}
			set_irq_regs(old_regs);

			/*
			 * Disable interrupts and send EOI
			 */
			local_irq_disable();
			ia64_setreg(_IA64_REG_CR_TPR, saved_tpr);
		}
		ia64_eoi();
		vector = ia64_get_ivr();
	}
	irq_exit();
}
#endif


#ifdef CONFIG_SMP

static irqreturn_t dummy_handler (int irq, void *dev_id)
{
	BUG();
}

static struct irqaction ipi_irqaction = {
	.handler =	handle_IPI,
	.flags =	IRQF_DISABLED,
	.name =		"IPI"
};

/*
 * KVM uses this interrupt to force a cpu out of guest mode
 */
static struct irqaction resched_irqaction = {
	.handler =	dummy_handler,
	.flags =	IRQF_DISABLED,
	.name =		"resched"
};

static struct irqaction tlb_irqaction = {
	.handler =	dummy_handler,
	.flags =	IRQF_DISABLED,
	.name =		"tlb_flush"
};

#endif

void
ia64_native_register_percpu_irq (ia64_vector vec, struct irqaction *action)
{
	unsigned int irq;

	irq = vec;
	BUG_ON(bind_irq_vector(irq, vec, CPU_MASK_ALL));
	irq_set_status_flags(irq, IRQ_PER_CPU);
	irq_set_chip(irq, &irq_type_ia64_lsapic);
	if (action)
		setup_irq(irq, action);
	irq_set_handler(irq, handle_percpu_irq);
}

void __init
ia64_native_register_ipi(void)
{
#ifdef CONFIG_SMP
	register_percpu_irq(IA64_IPI_VECTOR, &ipi_irqaction);
	register_percpu_irq(IA64_IPI_RESCHEDULE, &resched_irqaction);
	register_percpu_irq(IA64_IPI_LOCAL_TLB_FLUSH, &tlb_irqaction);
#endif
}

void __init
init_IRQ (void)
{
#ifdef CONFIG_ACPI
	acpi_boot_init();
#endif
	ia64_register_ipi();
	register_percpu_irq(IA64_SPURIOUS_INT_VECTOR, NULL);
#ifdef CONFIG_SMP
#if defined(CONFIG_IA64_GENERIC) || defined(CONFIG_IA64_DIG)
	if (vector_domain_type != VECTOR_DOMAIN_NONE)
		register_percpu_irq(IA64_IRQ_MOVE_VECTOR, &irq_move_irqaction);
#endif
#endif
#ifdef CONFIG_PERFMON
	pfm_init_percpu();
#endif
	platform_irq_init();
}

void
ia64_send_ipi (int cpu, int vector, int delivery_mode, int redirect)
{
	void __iomem *ipi_addr;
	unsigned long ipi_data;
	unsigned long phys_cpu_id;

	phys_cpu_id = cpu_physical_id(cpu);

	/*
	 * cpu number is in 8bit ID and 8bit EID
	 */

	ipi_data = (delivery_mode << 8) | (vector & 0xff);
	ipi_addr = ipi_base_addr + ((phys_cpu_id << 4) | ((redirect & 1) << 3));

	writeq(ipi_data, ipi_addr);
}
Commit	Line	Data
1da177e4	1	/*
f30c2269	2	* linux/arch/ia64/kernel/irq_ia64.c
1da177e4 LT	3	*
	4	* Copyright (C) 1998-2001 Hewlett-Packard Co
	5	* Stephane Eranian <eranian@hpl.hp.com>
	6	* David Mosberger-Tang <davidm@hpl.hp.com>
	7	*
	8	* 6/10/99: Updated to bring in sync with x86 version to facilitate
	9	* support for SMP and different interrupt controllers.
	10	*
	11	* 09/15/00 Goutham Rao <goutham.rao@intel.com> Implemented pci_irq_to_vector
	12	* PCI to vector allocation routine.
	13	* 04/14/2004 Ashok Raj <ashok.raj@intel.com>
	14	* Added CPU Hotplug handling for IPF.
	15	*/
	16
1da177e4 LT	17	#include <linux/module.h>
	18
	19	#include <linux/jiffies.h>
	20	#include <linux/errno.h>
	21	#include <linux/init.h>
	22	#include <linux/interrupt.h>
	23	#include <linux/ioport.h>
	24	#include <linux/kernel_stat.h>
1da177e4 LT	25	#include <linux/ptrace.h>
	26	#include <linux/random.h> /* for rand_initialize_irq() */
	27	#include <linux/signal.h>
	28	#include <linux/smp.h>
1da177e4 LT	29	#include <linux/threads.h>
1da177e4 LT	30	#include <linux/bitops.h>
b6cf2583	31	#include <linux/irq.h>
7683a3f9	32	#include <linux/ratelimit.h>
4de0a759	33	#include <linux/acpi.h>
184748cc	34	#include <linux/sched.h>
1da177e4 LT	35
	36	#include <asm/delay.h>
	37	#include <asm/intrinsics.h>
	38	#include <asm/io.h>
	39	#include <asm/hw_irq.h>
	40	#include <asm/machvec.h>
	41	#include <asm/pgtable.h>
	42	#include <asm/system.h>
3be44b9c	43	#include <asm/tlbflush.h>
1da177e4 LT	44
	45	#ifdef CONFIG_PERFMON
	46	# include <asm/perfmon.h>
	47	#endif
	48
	49	#define IRQ_DEBUG 0
	50
e1b30a39 YI	51	#define IRQ_VECTOR_UNASSIGNED (0)
	52
	53	#define IRQ_UNUSED (0)
	54	#define IRQ_USED (1)
	55	#define IRQ_RSVD (2)
	56
10083072 MM	57	/* These can be overridden in platform_irq_init */
	58	int ia64_first_device_vector = IA64_DEF_FIRST_DEVICE_VECTOR;
	59	int ia64_last_device_vector = IA64_DEF_LAST_DEVICE_VECTOR;
	60
1da177e4 LT	61	/* default base addr of IPI table */
	62	void __iomem ipi_base_addr = ((void __iomem )
	63	(__IA64_UNCACHED_OFFSET \| IA64_IPI_DEFAULT_BASE_ADDR));
	64
4994be1b YI	65	static cpumask_t vector_allocation_domain(int cpu);
4994be1b YI	66
1da177e4 LT	67	/*
	68	* Legacy IRQ to IA-64 vector translation table.
	69	*/
	70	__u8 isa_irq_to_vector_map[16] = {
	71	/* 8259 IRQ translation, first 16 entries */
	72	0x2f, 0x20, 0x2e, 0x2d, 0x2c, 0x2b, 0x2a, 0x29,
	73	0x28, 0x27, 0x26, 0x25, 0x24, 0x23, 0x22, 0x21
	74	};
	75	EXPORT_SYMBOL(isa_irq_to_vector_map);
	76
e1b30a39 YI	77	DEFINE_SPINLOCK(vector_lock);
	78
	79	struct irq_cfg irq_cfg[NR_IRQS] __read_mostly = {
4994be1b YI	80	[0 ... NR_IRQS - 1] = {
	81	.vector = IRQ_VECTOR_UNASSIGNED,
	82	.domain = CPU_MASK_NONE
	83	}
e1b30a39 YI	84	};
	85
	86	DEFINE_PER_CPU(int[IA64_NUM_VECTORS], vector_irq) = {
17764d24	87	[0 ... IA64_NUM_VECTORS - 1] = -1
e1b30a39 YI	88	};
e1b30a39 YI	89
6ffbc823 KK	90	static cpumask_t vector_table[IA64_NUM_VECTORS] = {
6ffbc823 KK	91	[0 ... IA64_NUM_VECTORS - 1] = CPU_MASK_NONE
4994be1b YI	92	};
4994be1b YI	93
e1b30a39 YI	94	static int irq_status[NR_IRQS] = {
	95	[0 ... NR_IRQS -1] = IRQ_UNUSED
	96	};
	97
	98	int check_irq_used(int irq)
	99	{
	100	if (irq_status[irq] == IRQ_USED)
	101	return 1;
	102
	103	return -1;
	104	}
	105
e1b30a39 YI	106	static inline int find_unassigned_irq(void)
	107	{
	108	int irq;
	109
	110	for (irq = IA64_FIRST_DEVICE_VECTOR; irq < NR_IRQS; irq++)
	111	if (irq_status[irq] == IRQ_UNUSED)
	112	return irq;
	113	return -ENOSPC;
	114	}
	115
4994be1b	116	static inline int find_unassigned_vector(cpumask_t domain)
e1b30a39	117	{
4994be1b	118	cpumask_t mask;
6ffbc823	119	int pos, vector;
4994be1b YI	120
	121	cpus_and(mask, domain, cpu_online_map);
	122	if (cpus_empty(mask))
	123	return -EINVAL;
e1b30a39	124
4994be1b	125	for (pos = 0; pos < IA64_NUM_DEVICE_VECTORS; pos++) {
6ffbc823 KK	126	vector = IA64_FIRST_DEVICE_VECTOR + pos;
6ffbc823 KK	127	cpus_and(mask, domain, vector_table[vector]);
4994be1b YI	128	if (!cpus_empty(mask))
4994be1b YI	129	continue;
6ffbc823	130	return vector;
4994be1b	131	}
e1b30a39 YI	132	return -ENOSPC;
	133	}
	134
4994be1b	135	static int __bind_irq_vector(int irq, int vector, cpumask_t domain)
e1b30a39	136	{
4994be1b	137	cpumask_t mask;
6ffbc823	138	int cpu;
4994be1b	139	struct irq_cfg *cfg = &irq_cfg[irq];
e1b30a39	140
6bde71ec KK	141	BUG_ON((unsigned)irq >= NR_IRQS);
	142	BUG_ON((unsigned)vector >= IA64_NUM_VECTORS);
	143
4994be1b YI	144	cpus_and(mask, domain, cpu_online_map);
	145	if (cpus_empty(mask))
	146	return -EINVAL;
	147	if ((cfg->vector == vector) && cpus_equal(cfg->domain, domain))
e1b30a39	148	return 0;
4994be1b	149	if (cfg->vector != IRQ_VECTOR_UNASSIGNED)
e1b30a39	150	return -EBUSY;
4994be1b	151	for_each_cpu_mask(cpu, mask)
e1b30a39	152	per_cpu(vector_irq, cpu)[vector] = irq;
4994be1b YI	153	cfg->vector = vector;
4994be1b YI	154	cfg->domain = domain;
e1b30a39	155	irq_status[irq] = IRQ_USED;
6ffbc823	156	cpus_or(vector_table[vector], vector_table[vector], domain);
e1b30a39 YI	157	return 0;
	158	}
	159
4994be1b	160	int bind_irq_vector(int irq, int vector, cpumask_t domain)
e1b30a39 YI	161	{
	162	unsigned long flags;
	163	int ret;
	164
	165	spin_lock_irqsave(&vector_lock, flags);
4994be1b	166	ret = __bind_irq_vector(irq, vector, domain);
e1b30a39 YI	167	spin_unlock_irqrestore(&vector_lock, flags);
	168	return ret;
	169	}
	170
cd378f18	171	static void __clear_irq_vector(int irq)
e1b30a39	172	{
6ffbc823	173	int vector, cpu;
4994be1b YI	174	cpumask_t mask;
	175	cpumask_t domain;
	176	struct irq_cfg *cfg = &irq_cfg[irq];
e1b30a39	177
e1b30a39	178	BUG_ON((unsigned)irq >= NR_IRQS);
4994be1b YI	179	BUG_ON(cfg->vector == IRQ_VECTOR_UNASSIGNED);
	180	vector = cfg->vector;
	181	domain = cfg->domain;
	182	cpus_and(mask, cfg->domain, cpu_online_map);
	183	for_each_cpu_mask(cpu, mask)
17764d24	184	per_cpu(vector_irq, cpu)[vector] = -1;
4994be1b YI	185	cfg->vector = IRQ_VECTOR_UNASSIGNED;
4994be1b YI	186	cfg->domain = CPU_MASK_NONE;
e1b30a39	187	irq_status[irq] = IRQ_UNUSED;
6ffbc823	188	cpus_andnot(vector_table[vector], vector_table[vector], domain);
cd378f18 YI	189	}
	190
	191	static void clear_irq_vector(int irq)
	192	{
	193	unsigned long flags;
	194
	195	spin_lock_irqsave(&vector_lock, flags);
	196	__clear_irq_vector(irq);
e1b30a39 YI	197	spin_unlock_irqrestore(&vector_lock, flags);
e1b30a39 YI	198	}
1da177e4 LT	199
1da177e4 LT	200	int
85cbc503	201	ia64_native_assign_irq_vector (int irq)
1da177e4	202	{
e1b30a39	203	unsigned long flags;
4994be1b	204	int vector, cpu;
373167e8	205	cpumask_t domain = CPU_MASK_NONE;
4994be1b YI	206
4994be1b YI	207	vector = -ENOSPC;
e1b30a39	208
4994be1b	209	spin_lock_irqsave(&vector_lock, flags);
4994be1b YI	210	for_each_online_cpu(cpu) {
	211	domain = vector_allocation_domain(cpu);
	212	vector = find_unassigned_vector(domain);
	213	if (vector >= 0)
	214	break;
	215	}
e1b30a39 YI	216	if (vector < 0)
e1b30a39 YI	217	goto out;
8f5ad1a8 YI	218	if (irq == AUTO_ASSIGN)
8f5ad1a8 YI	219	irq = vector;
4994be1b	220	BUG_ON(__bind_irq_vector(irq, vector, domain));
e1b30a39	221	out:
4994be1b	222	spin_unlock_irqrestore(&vector_lock, flags);
1da177e4 LT	223	return vector;
	224	}
	225
	226	void
85cbc503	227	ia64_native_free_irq_vector (int vector)
1da177e4	228	{
e1b30a39 YI	229	if (vector < IA64_FIRST_DEVICE_VECTOR \|\|
e1b30a39 YI	230	vector > IA64_LAST_DEVICE_VECTOR)
1da177e4	231	return;
e1b30a39	232	clear_irq_vector(vector);
1da177e4 LT	233	}
1da177e4 LT	234
10083072 MM	235	int
	236	reserve_irq_vector (int vector)
	237	{
10083072 MM	238	if (vector < IA64_FIRST_DEVICE_VECTOR \|\|
	239	vector > IA64_LAST_DEVICE_VECTOR)
	240	return -EINVAL;
4994be1b	241	return !!bind_irq_vector(vector, vector, CPU_MASK_ALL);
e1b30a39	242	}
10083072	243
e1b30a39 YI	244	/*
	245	* Initialize vector_irq on a new cpu. This function must be called
	246	* with vector_lock held.
	247	*/
	248	void __setup_vector_irq(int cpu)
	249	{
	250	int irq, vector;
	251
	252	/* Clear vector_irq */
	253	for (vector = 0; vector < IA64_NUM_VECTORS; ++vector)
17764d24	254	per_cpu(vector_irq, cpu)[vector] = -1;
e1b30a39 YI	255	/* Mark the inuse vectors */
e1b30a39 YI	256	for (irq = 0; irq < NR_IRQS; ++irq) {
4994be1b YI	257	if (!cpu_isset(cpu, irq_cfg[irq].domain))
	258	continue;
	259	vector = irq_to_vector(irq);
	260	per_cpu(vector_irq, cpu)[vector] = irq;
e1b30a39 YI	261	}
	262	}
	263
e5bd762b	264	#if defined(CONFIG_SMP) && (defined(CONFIG_IA64_GENERIC) \|\| defined(CONFIG_IA64_DIG))
a6cd6322	265
d080d397 YI	266	static enum vector_domain_type {
	267	VECTOR_DOMAIN_NONE,
	268	VECTOR_DOMAIN_PERCPU
	269	} vector_domain_type = VECTOR_DOMAIN_NONE;
	270
4994be1b YI	271	static cpumask_t vector_allocation_domain(int cpu)
4994be1b YI	272	{
d080d397 YI	273	if (vector_domain_type == VECTOR_DOMAIN_PERCPU)
d080d397 YI	274	return cpumask_of_cpu(cpu);
4994be1b YI	275	return CPU_MASK_ALL;
	276	}
	277
a6cd6322 KK	278	static int __irq_prepare_move(int irq, int cpu)
	279	{
	280	struct irq_cfg *cfg = &irq_cfg[irq];
	281	int vector;
	282	cpumask_t domain;
	283
	284	if (cfg->move_in_progress \|\| cfg->move_cleanup_count)
	285	return -EBUSY;
	286	if (cfg->vector == IRQ_VECTOR_UNASSIGNED \|\| !cpu_online(cpu))
	287	return -EINVAL;
	288	if (cpu_isset(cpu, cfg->domain))
	289	return 0;
	290	domain = vector_allocation_domain(cpu);
	291	vector = find_unassigned_vector(domain);
	292	if (vector < 0)
	293	return -ENOSPC;
	294	cfg->move_in_progress = 1;
	295	cfg->old_domain = cfg->domain;
	296	cfg->vector = IRQ_VECTOR_UNASSIGNED;
	297	cfg->domain = CPU_MASK_NONE;
	298	BUG_ON(__bind_irq_vector(irq, vector, domain));
	299	return 0;
	300	}
	301
	302	int irq_prepare_move(int irq, int cpu)
	303	{
	304	unsigned long flags;
	305	int ret;
	306
	307	spin_lock_irqsave(&vector_lock, flags);
	308	ret = __irq_prepare_move(irq, cpu);
	309	spin_unlock_irqrestore(&vector_lock, flags);
	310	return ret;
	311	}
	312
	313	void irq_complete_move(unsigned irq)
	314	{
	315	struct irq_cfg *cfg = &irq_cfg[irq];
	316	cpumask_t cleanup_mask;
	317	int i;
	318
	319	if (likely(!cfg->move_in_progress))
	320	return;
	321
	322	if (unlikely(cpu_isset(smp_processor_id(), cfg->old_domain)))
	323	return;
	324
	325	cpus_and(cleanup_mask, cfg->old_domain, cpu_online_map);
	326	cfg->move_cleanup_count = cpus_weight(cleanup_mask);
	327	for_each_cpu_mask(i, cleanup_mask)
	328	platform_send_ipi(i, IA64_IRQ_MOVE_VECTOR, IA64_IPI_DM_INT, 0);
	329	cfg->move_in_progress = 0;
	330	}
	331
	332	static irqreturn_t smp_irq_move_cleanup_interrupt(int irq, void *dev_id)
	333	{
	334	int me = smp_processor_id();
	335	ia64_vector vector;
	336	unsigned long flags;
	337
	338	for (vector = IA64_FIRST_DEVICE_VECTOR;
	339	vector < IA64_LAST_DEVICE_VECTOR; vector++) {
	340	int irq;
	341	struct irq_desc *desc;
342	struct irq_cfg *cfg;
343	irq = __get_cpu_var(vector_irq)[vector];
344	if (irq < 0)
345	continue;
346
a2178334	347	desc = irq_to_desc(irq);
a6cd6322	348	cfg = irq_cfg + irq;
239007b8	349	raw_spin_lock(&desc->lock);
a6cd6322 KK	350	if (!cfg->move_cleanup_count)
	351	goto unlock;
	352
	353	if (!cpu_isset(me, cfg->old_domain))
	354	goto unlock;
	355
	356	spin_lock_irqsave(&vector_lock, flags);
	357	__get_cpu_var(vector_irq)[vector] = -1;
	358	cpu_clear(me, vector_table[vector]);
	359	spin_unlock_irqrestore(&vector_lock, flags);
	360	cfg->move_cleanup_count--;
	361	unlock:
239007b8	362	raw_spin_unlock(&desc->lock);
a6cd6322 KK	363	}
	364	return IRQ_HANDLED;
	365	}
	366
	367	static struct irqaction irq_move_irqaction = {
	368	.handler = smp_irq_move_cleanup_interrupt,
	369	.flags = IRQF_DISABLED,
	370	.name = "irq_move"
	371	};
	372
d080d397 YI	373	static int __init parse_vector_domain(char *arg)
	374	{
	375	if (!arg)
	376	return -EINVAL;
	377	if (!strcmp(arg, "percpu")) {
	378	vector_domain_type = VECTOR_DOMAIN_PERCPU;
	379	no_int_routing = 1;
	380	}
074ff856	381	return 0;
d080d397 YI	382	}
	383	early_param("vector", parse_vector_domain);
	384	#else
	385	static cpumask_t vector_allocation_domain(int cpu)
	386	{
	387	return CPU_MASK_ALL;
	388	}
	389	#endif
	390
4994be1b	391
e1b30a39 YI	392	void destroy_and_reserve_irq(unsigned int irq)
e1b30a39 YI	393	{
216fcd29 KK	394	unsigned long flags;
216fcd29 KK	395
e1b30a39 YI	396	dynamic_irq_cleanup(irq);
e1b30a39 YI	397
216fcd29 KK	398	spin_lock_irqsave(&vector_lock, flags);
	399	__clear_irq_vector(irq);
	400	irq_status[irq] = IRQ_RSVD;
	401	spin_unlock_irqrestore(&vector_lock, flags);
10083072 MM	402	}
10083072 MM	403
b6cf2583 EB	404	/*
	405	* Dynamic irq allocate and deallocation for MSI
	406	*/
	407	int create_irq(void)
	408	{
e1b30a39	409	unsigned long flags;
4994be1b	410	int irq, vector, cpu;
373167e8	411	cpumask_t domain = CPU_MASK_NONE;
e1b30a39	412
4994be1b	413	irq = vector = -ENOSPC;
e1b30a39	414	spin_lock_irqsave(&vector_lock, flags);
4994be1b YI	415	for_each_online_cpu(cpu) {
	416	domain = vector_allocation_domain(cpu);
	417	vector = find_unassigned_vector(domain);
	418	if (vector >= 0)
	419	break;
	420	}
e1b30a39 YI	421	if (vector < 0)
	422	goto out;
	423	irq = find_unassigned_irq();
	424	if (irq < 0)
	425	goto out;
4994be1b	426	BUG_ON(__bind_irq_vector(irq, vector, domain));
e1b30a39 YI	427	out:
	428	spin_unlock_irqrestore(&vector_lock, flags);
	429	if (irq >= 0)
	430	dynamic_irq_init(irq);
	431	return irq;
b6cf2583 EB	432	}
	433
	434	void destroy_irq(unsigned int irq)
	435	{
	436	dynamic_irq_cleanup(irq);
e1b30a39	437	clear_irq_vector(irq);
b6cf2583 EB	438	}
b6cf2583 EB	439
1da177e4 LT	440	#ifdef CONFIG_SMP
1da177e4 LT	441	# define IS_RESCHEDULE(vec) (vec == IA64_IPI_RESCHEDULE)
3be44b9c	442	# define IS_LOCAL_TLB_FLUSH(vec) (vec == IA64_IPI_LOCAL_TLB_FLUSH)
1da177e4 LT	443	#else
1da177e4 LT	444	# define IS_RESCHEDULE(vec) (0)
3be44b9c	445	# define IS_LOCAL_TLB_FLUSH(vec) (0)
1da177e4 LT	446	#endif
	447	/*
	448	* That's where the IVT branches when we get an external
	449	* interrupt. This branches to the correct hardware IRQ handler via
	450	* function ptr.
	451	*/
	452	void
	453	ia64_handle_irq (ia64_vector vector, struct pt_regs *regs)
	454	{
7d12e780	455	struct pt_regs *old_regs = set_irq_regs(regs);
1da177e4 LT	456	unsigned long saved_tpr;
	457
	458	#if IRQ_DEBUG
	459	{
	460	unsigned long bsp, sp;
	461
	462	/*
	463	* Note: if the interrupt happened while executing in
	464	* the context switch routine (ia64_switch_to), we may
	465	* get a spurious stack overflow here. This is
	466	* because the register and the memory stack are not
	467	* switched atomically.
	468	*/
	469	bsp = ia64_getreg(_IA64_REG_AR_BSP);
	470	sp = ia64_getreg(_IA64_REG_SP);
	471
	472	if ((sp - bsp) < 1024) {
7683a3f9	473	static DEFINE_RATELIMIT_STATE(ratelimit, 5 * HZ, 5);
1da177e4	474
7683a3f9	475	if (__ratelimit(&ratelimit)) {
1da177e4 LT	476	printk("ia64_handle_irq: DANGER: less than "
	477	"1KB of free stack space!!\n"
	478	"(bsp=0x%lx, sp=%lx)\n", bsp, sp);
	479	}
	480	}
	481	}
	482	#endif /* IRQ_DEBUG */
	483
	484	/*
	485	* Always set TPR to limit maximum interrupt nesting depth to
	486	* 16 (without this, it would be ~240, which could easily lead
	487	* to kernel stack overflows).
	488	*/
	489	irq_enter();
	490	saved_tpr = ia64_getreg(_IA64_REG_CR_TPR);
	491	ia64_srlz_d();
	492	while (vector != IA64_SPURIOUS_INT_VECTOR) {
66f3e6af	493	int irq = local_vector_to_irq(vector);
7c730ccd	494	struct irq_desc *desc = irq_to_desc(irq);
66f3e6af	495
3be44b9c JS	496	if (unlikely(IS_LOCAL_TLB_FLUSH(vector))) {
3be44b9c JS	497	smp_local_flush_tlb();
66f3e6af	498	kstat_incr_irqs_this_cpu(irq, desc);
7c730ccd	499	} else if (unlikely(IS_RESCHEDULE(vector))) {
184748cc	500	scheduler_ipi();
66f3e6af	501	kstat_incr_irqs_this_cpu(irq, desc);
7c730ccd	502	} else {
1da177e4 LT	503	ia64_setreg(_IA64_REG_CR_TPR, vector);
	504	ia64_srlz_d();
	505
17764d24 KK	506	if (unlikely(irq < 0)) {
	507	printk(KERN_ERR "%s: Unexpected interrupt "
	508	"vector %d on CPU %d is not mapped "
d4ed8084	509	"to any IRQ!\n", __func__, vector,
17764d24 KK	510	smp_processor_id());
	511	} else
	512	generic_handle_irq(irq);
1da177e4 LT	513
	514	/*
	515	* Disable interrupts and send EOI:
	516	*/
	517	local_irq_disable();
	518	ia64_setreg(_IA64_REG_CR_TPR, saved_tpr);
	519	}
	520	ia64_eoi();
	521	vector = ia64_get_ivr();
	522	}
	523	/*
	524	* This must be done after the ia64_eoi(). For example, the keyboard softirq
	525	* handler needs to be able to wait for further keyboard interrupts, which can't
	526	* come through until ia64_eoi() has been done.
	527	*/
	528	irq_exit();
7d12e780	529	set_irq_regs(old_regs);
1da177e4 LT	530	}
	531
	532	#ifdef CONFIG_HOTPLUG_CPU
	533	/*
	534	* This function emulates a interrupt processing when a cpu is about to be
	535	* brought down.
	536	*/
	537	void ia64_process_pending_intr(void)
	538	{
	539	ia64_vector vector;
	540	unsigned long saved_tpr;
	541	extern unsigned int vectors_in_migration[NR_IRQS];
	542
	543	vector = ia64_get_ivr();
	544
66f3e6af JS	545	irq_enter();
	546	saved_tpr = ia64_getreg(_IA64_REG_CR_TPR);
	547	ia64_srlz_d();
1da177e4 LT	548
	549	/*
	550	* Perform normal interrupt style processing
	551	*/
	552	while (vector != IA64_SPURIOUS_INT_VECTOR) {
66f3e6af	553	int irq = local_vector_to_irq(vector);
7c730ccd	554	struct irq_desc *desc = irq_to_desc(irq);
66f3e6af	555
3be44b9c JS	556	if (unlikely(IS_LOCAL_TLB_FLUSH(vector))) {
3be44b9c JS	557	smp_local_flush_tlb();
66f3e6af	558	kstat_incr_irqs_this_cpu(irq, desc);
7c730ccd	559	} else if (unlikely(IS_RESCHEDULE(vector))) {
66f3e6af	560	kstat_incr_irqs_this_cpu(irq, desc);
7c730ccd	561	} else {
8c1addbc TL	562	struct pt_regs *old_regs = set_irq_regs(NULL);
8c1addbc TL	563
1da177e4 LT	564	ia64_setreg(_IA64_REG_CR_TPR, vector);
	565	ia64_srlz_d();
	566
	567	/*
	568	* Now try calling normal ia64_handle_irq as it would have got called
	569	* from a real intr handler. Try passing null for pt_regs, hopefully
	570	* it will work. I hope it works!.
	571	* Probably could shared code.
	572	*/
17764d24 KK	573	if (unlikely(irq < 0)) {
	574	printk(KERN_ERR "%s: Unexpected interrupt "
	575	"vector %d on CPU %d not being mapped "
d4ed8084	576	"to any IRQ!!\n", __func__, vector,
17764d24 KK	577	smp_processor_id());
	578	} else {
	579	vectors_in_migration[irq]=0;
	580	generic_handle_irq(irq);
	581	}
8c1addbc	582	set_irq_regs(old_regs);
1da177e4 LT	583
	584	/*
	585	* Disable interrupts and send EOI
	586	*/
	587	local_irq_disable();
	588	ia64_setreg(_IA64_REG_CR_TPR, saved_tpr);
	589	}
	590	ia64_eoi();
	591	vector = ia64_get_ivr();
	592	}
	593	irq_exit();
	594	}
	595	#endif
	596
	597
	598	#ifdef CONFIG_SMP
1da177e4	599
9b3377f9 JS	600	static irqreturn_t dummy_handler (int irq, void *dev_id)
	601	{
	602	BUG();
	603	}
	604
1da177e4 LT	605	static struct irqaction ipi_irqaction = {
1da177e4 LT	606	.handler = handle_IPI,
121a4226	607	.flags = IRQF_DISABLED,
1da177e4 LT	608	.name = "IPI"
1da177e4 LT	609	};
9b3377f9	610
32f88400 MT	611	/*
	612	* KVM uses this interrupt to force a cpu out of guest mode
	613	*/
9b3377f9 JS	614	static struct irqaction resched_irqaction = {
9b3377f9 JS	615	.handler = dummy_handler,
38515e90	616	.flags = IRQF_DISABLED,
9b3377f9 JS	617	.name = "resched"
9b3377f9 JS	618	};
3be44b9c JS	619
	620	static struct irqaction tlb_irqaction = {
	621	.handler = dummy_handler,
5329571b	622	.flags = IRQF_DISABLED,
3be44b9c JS	623	.name = "tlb_flush"
	624	};
	625
1da177e4 LT	626	#endif
	627
	628	void
85cbc503	629	ia64_native_register_percpu_irq (ia64_vector vec, struct irqaction *action)
1da177e4	630	{
1da177e4 LT	631	unsigned int irq;
1da177e4 LT	632
e1b30a39	633	irq = vec;
4994be1b	634	BUG_ON(bind_irq_vector(irq, vec, CPU_MASK_ALL));
a2178334	635	irq_set_status_flags(irq, IRQ_PER_CPU);
53c909c9	636	irq_set_chip(irq, &irq_type_ia64_lsapic);
e1b30a39 YI	637	if (action)
e1b30a39 YI	638	setup_irq(irq, action);
53c909c9	639	irq_set_handler(irq, handle_percpu_irq);
1da177e4 LT	640	}
	641
	642	void __init
85cbc503	643	ia64_native_register_ipi(void)
1da177e4	644	{
1da177e4 LT	645	#ifdef CONFIG_SMP
1da177e4 LT	646	register_percpu_irq(IA64_IPI_VECTOR, &ipi_irqaction);
9b3377f9	647	register_percpu_irq(IA64_IPI_RESCHEDULE, &resched_irqaction);
3be44b9c	648	register_percpu_irq(IA64_IPI_LOCAL_TLB_FLUSH, &tlb_irqaction);
85cbc503 IY	649	#endif
	650	}
	651
	652	void __init
	653	init_IRQ (void)
	654	{
4de0a759 TL	655	#ifdef CONFIG_ACPI
	656	acpi_boot_init();
	657	#endif
85cbc503 IY	658	ia64_register_ipi();
	659	register_percpu_irq(IA64_SPURIOUS_INT_VECTOR, NULL);
	660	#ifdef CONFIG_SMP
a6cd6322	661	#if defined(CONFIG_IA64_GENERIC) \|\| defined(CONFIG_IA64_DIG)
09b366b7	662	if (vector_domain_type != VECTOR_DOMAIN_NONE)
a6cd6322	663	register_percpu_irq(IA64_IRQ_MOVE_VECTOR, &irq_move_irqaction);
a6cd6322	664	#endif
1da177e4 LT	665	#endif
	666	#ifdef CONFIG_PERFMON
	667	pfm_init_percpu();
	668	#endif
	669	platform_irq_init();
	670	}
	671
	672	void
	673	ia64_send_ipi (int cpu, int vector, int delivery_mode, int redirect)
	674	{
	675	void __iomem *ipi_addr;
	676	unsigned long ipi_data;
	677	unsigned long phys_cpu_id;
	678
1da177e4	679	phys_cpu_id = cpu_physical_id(cpu);
1da177e4 LT	680
	681	/*
	682	* cpu number is in 8bit ID and 8bit EID
	683	*/
	684
	685	ipi_data = (delivery_mode << 8) \| (vector & 0xff);
	686	ipi_addr = ipi_base_addr + ((phys_cpu_id << 4) \| ((redirect & 1) << 3));
	687
	688	writeq(ipi_data, ipi_addr);
	689	}