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b2441318 | 1 | // SPDX-License-Identifier: GPL-2.0 |
1da177e4 | 2 | /* |
f30c2269 | 3 | * linux/arch/ia64/kernel/irq_ia64.c |
1da177e4 LT |
4 | * |
5 | * Copyright (C) 1998-2001 Hewlett-Packard Co | |
6 | * Stephane Eranian <eranian@hpl.hp.com> | |
7 | * David Mosberger-Tang <davidm@hpl.hp.com> | |
8 | * | |
9 | * 6/10/99: Updated to bring in sync with x86 version to facilitate | |
10 | * support for SMP and different interrupt controllers. | |
11 | * | |
12 | * 09/15/00 Goutham Rao <goutham.rao@intel.com> Implemented pci_irq_to_vector | |
13 | * PCI to vector allocation routine. | |
14 | * 04/14/2004 Ashok Raj <ashok.raj@intel.com> | |
15 | * Added CPU Hotplug handling for IPF. | |
16 | */ | |
17 | ||
1da177e4 LT |
18 | #include <linux/module.h> |
19 | ||
20 | #include <linux/jiffies.h> | |
21 | #include <linux/errno.h> | |
22 | #include <linux/init.h> | |
23 | #include <linux/interrupt.h> | |
24 | #include <linux/ioport.h> | |
25 | #include <linux/kernel_stat.h> | |
1da177e4 | 26 | #include <linux/ptrace.h> |
1da177e4 LT |
27 | #include <linux/signal.h> |
28 | #include <linux/smp.h> | |
1da177e4 LT |
29 | #include <linux/threads.h> |
30 | #include <linux/bitops.h> | |
b6cf2583 | 31 | #include <linux/irq.h> |
7683a3f9 | 32 | #include <linux/ratelimit.h> |
4de0a759 | 33 | #include <linux/acpi.h> |
184748cc | 34 | #include <linux/sched.h> |
1da177e4 LT |
35 | |
36 | #include <asm/delay.h> | |
37 | #include <asm/intrinsics.h> | |
38 | #include <asm/io.h> | |
39 | #include <asm/hw_irq.h> | |
40 | #include <asm/machvec.h> | |
41 | #include <asm/pgtable.h> | |
3be44b9c | 42 | #include <asm/tlbflush.h> |
1da177e4 LT |
43 | |
44 | #ifdef CONFIG_PERFMON | |
45 | # include <asm/perfmon.h> | |
46 | #endif | |
47 | ||
48 | #define IRQ_DEBUG 0 | |
49 | ||
e1b30a39 YI |
50 | #define IRQ_VECTOR_UNASSIGNED (0) |
51 | ||
52 | #define IRQ_UNUSED (0) | |
53 | #define IRQ_USED (1) | |
54 | #define IRQ_RSVD (2) | |
55 | ||
10083072 MM |
56 | /* These can be overridden in platform_irq_init */ |
57 | int ia64_first_device_vector = IA64_DEF_FIRST_DEVICE_VECTOR; | |
58 | int ia64_last_device_vector = IA64_DEF_LAST_DEVICE_VECTOR; | |
59 | ||
1da177e4 LT |
60 | /* default base addr of IPI table */ |
61 | void __iomem *ipi_base_addr = ((void __iomem *) | |
62 | (__IA64_UNCACHED_OFFSET | IA64_IPI_DEFAULT_BASE_ADDR)); | |
63 | ||
4994be1b YI |
64 | static cpumask_t vector_allocation_domain(int cpu); |
65 | ||
1da177e4 LT |
66 | /* |
67 | * Legacy IRQ to IA-64 vector translation table. | |
68 | */ | |
69 | __u8 isa_irq_to_vector_map[16] = { | |
70 | /* 8259 IRQ translation, first 16 entries */ | |
71 | 0x2f, 0x20, 0x2e, 0x2d, 0x2c, 0x2b, 0x2a, 0x29, | |
72 | 0x28, 0x27, 0x26, 0x25, 0x24, 0x23, 0x22, 0x21 | |
73 | }; | |
74 | EXPORT_SYMBOL(isa_irq_to_vector_map); | |
75 | ||
e1b30a39 YI |
76 | DEFINE_SPINLOCK(vector_lock); |
77 | ||
78 | struct irq_cfg irq_cfg[NR_IRQS] __read_mostly = { | |
4994be1b YI |
79 | [0 ... NR_IRQS - 1] = { |
80 | .vector = IRQ_VECTOR_UNASSIGNED, | |
81 | .domain = CPU_MASK_NONE | |
82 | } | |
e1b30a39 YI |
83 | }; |
84 | ||
85 | DEFINE_PER_CPU(int[IA64_NUM_VECTORS], vector_irq) = { | |
17764d24 | 86 | [0 ... IA64_NUM_VECTORS - 1] = -1 |
e1b30a39 YI |
87 | }; |
88 | ||
6ffbc823 KK |
89 | static cpumask_t vector_table[IA64_NUM_VECTORS] = { |
90 | [0 ... IA64_NUM_VECTORS - 1] = CPU_MASK_NONE | |
4994be1b YI |
91 | }; |
92 | ||
e1b30a39 YI |
93 | static int irq_status[NR_IRQS] = { |
94 | [0 ... NR_IRQS -1] = IRQ_UNUSED | |
95 | }; | |
96 | ||
e1b30a39 YI |
97 | static inline int find_unassigned_irq(void) |
98 | { | |
99 | int irq; | |
100 | ||
101 | for (irq = IA64_FIRST_DEVICE_VECTOR; irq < NR_IRQS; irq++) | |
102 | if (irq_status[irq] == IRQ_UNUSED) | |
103 | return irq; | |
104 | return -ENOSPC; | |
105 | } | |
106 | ||
4994be1b | 107 | static inline int find_unassigned_vector(cpumask_t domain) |
e1b30a39 | 108 | { |
4994be1b | 109 | cpumask_t mask; |
6ffbc823 | 110 | int pos, vector; |
4994be1b | 111 | |
7d7f9848 | 112 | cpumask_and(&mask, &domain, cpu_online_mask); |
5d2068da | 113 | if (cpumask_empty(&mask)) |
4994be1b | 114 | return -EINVAL; |
e1b30a39 | 115 | |
4994be1b | 116 | for (pos = 0; pos < IA64_NUM_DEVICE_VECTORS; pos++) { |
6ffbc823 | 117 | vector = IA64_FIRST_DEVICE_VECTOR + pos; |
5d2068da RR |
118 | cpumask_and(&mask, &domain, &vector_table[vector]); |
119 | if (!cpumask_empty(&mask)) | |
4994be1b | 120 | continue; |
6ffbc823 | 121 | return vector; |
4994be1b | 122 | } |
e1b30a39 YI |
123 | return -ENOSPC; |
124 | } | |
125 | ||
4994be1b | 126 | static int __bind_irq_vector(int irq, int vector, cpumask_t domain) |
e1b30a39 | 127 | { |
4994be1b | 128 | cpumask_t mask; |
6ffbc823 | 129 | int cpu; |
4994be1b | 130 | struct irq_cfg *cfg = &irq_cfg[irq]; |
e1b30a39 | 131 | |
6bde71ec KK |
132 | BUG_ON((unsigned)irq >= NR_IRQS); |
133 | BUG_ON((unsigned)vector >= IA64_NUM_VECTORS); | |
134 | ||
7d7f9848 | 135 | cpumask_and(&mask, &domain, cpu_online_mask); |
5d2068da | 136 | if (cpumask_empty(&mask)) |
4994be1b | 137 | return -EINVAL; |
5d2068da | 138 | if ((cfg->vector == vector) && cpumask_equal(&cfg->domain, &domain)) |
e1b30a39 | 139 | return 0; |
4994be1b | 140 | if (cfg->vector != IRQ_VECTOR_UNASSIGNED) |
e1b30a39 | 141 | return -EBUSY; |
5d2068da | 142 | for_each_cpu(cpu, &mask) |
e1b30a39 | 143 | per_cpu(vector_irq, cpu)[vector] = irq; |
4994be1b YI |
144 | cfg->vector = vector; |
145 | cfg->domain = domain; | |
e1b30a39 | 146 | irq_status[irq] = IRQ_USED; |
5d2068da | 147 | cpumask_or(&vector_table[vector], &vector_table[vector], &domain); |
e1b30a39 YI |
148 | return 0; |
149 | } | |
150 | ||
4994be1b | 151 | int bind_irq_vector(int irq, int vector, cpumask_t domain) |
e1b30a39 YI |
152 | { |
153 | unsigned long flags; | |
154 | int ret; | |
155 | ||
156 | spin_lock_irqsave(&vector_lock, flags); | |
4994be1b | 157 | ret = __bind_irq_vector(irq, vector, domain); |
e1b30a39 YI |
158 | spin_unlock_irqrestore(&vector_lock, flags); |
159 | return ret; | |
160 | } | |
161 | ||
cd378f18 | 162 | static void __clear_irq_vector(int irq) |
e1b30a39 | 163 | { |
6ffbc823 | 164 | int vector, cpu; |
4994be1b YI |
165 | cpumask_t domain; |
166 | struct irq_cfg *cfg = &irq_cfg[irq]; | |
e1b30a39 | 167 | |
e1b30a39 | 168 | BUG_ON((unsigned)irq >= NR_IRQS); |
4994be1b YI |
169 | BUG_ON(cfg->vector == IRQ_VECTOR_UNASSIGNED); |
170 | vector = cfg->vector; | |
171 | domain = cfg->domain; | |
51f7bd85 | 172 | for_each_cpu_and(cpu, &cfg->domain, cpu_online_mask) |
17764d24 | 173 | per_cpu(vector_irq, cpu)[vector] = -1; |
4994be1b YI |
174 | cfg->vector = IRQ_VECTOR_UNASSIGNED; |
175 | cfg->domain = CPU_MASK_NONE; | |
e1b30a39 | 176 | irq_status[irq] = IRQ_UNUSED; |
6a4bd8d1 | 177 | cpumask_andnot(&vector_table[vector], &vector_table[vector], &domain); |
cd378f18 YI |
178 | } |
179 | ||
180 | static void clear_irq_vector(int irq) | |
181 | { | |
182 | unsigned long flags; | |
183 | ||
184 | spin_lock_irqsave(&vector_lock, flags); | |
185 | __clear_irq_vector(irq); | |
e1b30a39 YI |
186 | spin_unlock_irqrestore(&vector_lock, flags); |
187 | } | |
1da177e4 LT |
188 | |
189 | int | |
85cbc503 | 190 | ia64_native_assign_irq_vector (int irq) |
1da177e4 | 191 | { |
e1b30a39 | 192 | unsigned long flags; |
4994be1b | 193 | int vector, cpu; |
373167e8 | 194 | cpumask_t domain = CPU_MASK_NONE; |
4994be1b YI |
195 | |
196 | vector = -ENOSPC; | |
e1b30a39 | 197 | |
4994be1b | 198 | spin_lock_irqsave(&vector_lock, flags); |
4994be1b YI |
199 | for_each_online_cpu(cpu) { |
200 | domain = vector_allocation_domain(cpu); | |
201 | vector = find_unassigned_vector(domain); | |
202 | if (vector >= 0) | |
203 | break; | |
204 | } | |
e1b30a39 YI |
205 | if (vector < 0) |
206 | goto out; | |
8f5ad1a8 YI |
207 | if (irq == AUTO_ASSIGN) |
208 | irq = vector; | |
4994be1b | 209 | BUG_ON(__bind_irq_vector(irq, vector, domain)); |
e1b30a39 | 210 | out: |
4994be1b | 211 | spin_unlock_irqrestore(&vector_lock, flags); |
1da177e4 LT |
212 | return vector; |
213 | } | |
214 | ||
215 | void | |
85cbc503 | 216 | ia64_native_free_irq_vector (int vector) |
1da177e4 | 217 | { |
e1b30a39 YI |
218 | if (vector < IA64_FIRST_DEVICE_VECTOR || |
219 | vector > IA64_LAST_DEVICE_VECTOR) | |
1da177e4 | 220 | return; |
e1b30a39 | 221 | clear_irq_vector(vector); |
1da177e4 LT |
222 | } |
223 | ||
10083072 MM |
224 | int |
225 | reserve_irq_vector (int vector) | |
226 | { | |
10083072 MM |
227 | if (vector < IA64_FIRST_DEVICE_VECTOR || |
228 | vector > IA64_LAST_DEVICE_VECTOR) | |
229 | return -EINVAL; | |
4994be1b | 230 | return !!bind_irq_vector(vector, vector, CPU_MASK_ALL); |
e1b30a39 | 231 | } |
10083072 | 232 | |
e1b30a39 YI |
233 | /* |
234 | * Initialize vector_irq on a new cpu. This function must be called | |
235 | * with vector_lock held. | |
236 | */ | |
237 | void __setup_vector_irq(int cpu) | |
238 | { | |
239 | int irq, vector; | |
240 | ||
241 | /* Clear vector_irq */ | |
242 | for (vector = 0; vector < IA64_NUM_VECTORS; ++vector) | |
17764d24 | 243 | per_cpu(vector_irq, cpu)[vector] = -1; |
e1b30a39 YI |
244 | /* Mark the inuse vectors */ |
245 | for (irq = 0; irq < NR_IRQS; ++irq) { | |
5d2068da | 246 | if (!cpumask_test_cpu(cpu, &irq_cfg[irq].domain)) |
4994be1b YI |
247 | continue; |
248 | vector = irq_to_vector(irq); | |
249 | per_cpu(vector_irq, cpu)[vector] = irq; | |
e1b30a39 YI |
250 | } |
251 | } | |
252 | ||
e5bd762b | 253 | #if defined(CONFIG_SMP) && (defined(CONFIG_IA64_GENERIC) || defined(CONFIG_IA64_DIG)) |
a6cd6322 | 254 | |
d080d397 YI |
255 | static enum vector_domain_type { |
256 | VECTOR_DOMAIN_NONE, | |
257 | VECTOR_DOMAIN_PERCPU | |
258 | } vector_domain_type = VECTOR_DOMAIN_NONE; | |
259 | ||
4994be1b YI |
260 | static cpumask_t vector_allocation_domain(int cpu) |
261 | { | |
d080d397 | 262 | if (vector_domain_type == VECTOR_DOMAIN_PERCPU) |
6a4bd8d1 | 263 | return *cpumask_of(cpu); |
4994be1b YI |
264 | return CPU_MASK_ALL; |
265 | } | |
266 | ||
a6cd6322 KK |
267 | static int __irq_prepare_move(int irq, int cpu) |
268 | { | |
269 | struct irq_cfg *cfg = &irq_cfg[irq]; | |
270 | int vector; | |
271 | cpumask_t domain; | |
272 | ||
273 | if (cfg->move_in_progress || cfg->move_cleanup_count) | |
274 | return -EBUSY; | |
275 | if (cfg->vector == IRQ_VECTOR_UNASSIGNED || !cpu_online(cpu)) | |
276 | return -EINVAL; | |
5d2068da | 277 | if (cpumask_test_cpu(cpu, &cfg->domain)) |
a6cd6322 KK |
278 | return 0; |
279 | domain = vector_allocation_domain(cpu); | |
280 | vector = find_unassigned_vector(domain); | |
281 | if (vector < 0) | |
282 | return -ENOSPC; | |
283 | cfg->move_in_progress = 1; | |
284 | cfg->old_domain = cfg->domain; | |
285 | cfg->vector = IRQ_VECTOR_UNASSIGNED; | |
286 | cfg->domain = CPU_MASK_NONE; | |
287 | BUG_ON(__bind_irq_vector(irq, vector, domain)); | |
288 | return 0; | |
289 | } | |
290 | ||
291 | int irq_prepare_move(int irq, int cpu) | |
292 | { | |
293 | unsigned long flags; | |
294 | int ret; | |
295 | ||
296 | spin_lock_irqsave(&vector_lock, flags); | |
297 | ret = __irq_prepare_move(irq, cpu); | |
298 | spin_unlock_irqrestore(&vector_lock, flags); | |
299 | return ret; | |
300 | } | |
301 | ||
302 | void irq_complete_move(unsigned irq) | |
303 | { | |
304 | struct irq_cfg *cfg = &irq_cfg[irq]; | |
305 | cpumask_t cleanup_mask; | |
306 | int i; | |
307 | ||
308 | if (likely(!cfg->move_in_progress)) | |
309 | return; | |
310 | ||
5d2068da | 311 | if (unlikely(cpumask_test_cpu(smp_processor_id(), &cfg->old_domain))) |
a6cd6322 KK |
312 | return; |
313 | ||
7d7f9848 | 314 | cpumask_and(&cleanup_mask, &cfg->old_domain, cpu_online_mask); |
5d2068da RR |
315 | cfg->move_cleanup_count = cpumask_weight(&cleanup_mask); |
316 | for_each_cpu(i, &cleanup_mask) | |
a6cd6322 KK |
317 | platform_send_ipi(i, IA64_IRQ_MOVE_VECTOR, IA64_IPI_DM_INT, 0); |
318 | cfg->move_in_progress = 0; | |
319 | } | |
320 | ||
321 | static irqreturn_t smp_irq_move_cleanup_interrupt(int irq, void *dev_id) | |
322 | { | |
323 | int me = smp_processor_id(); | |
324 | ia64_vector vector; | |
325 | unsigned long flags; | |
326 | ||
327 | for (vector = IA64_FIRST_DEVICE_VECTOR; | |
328 | vector < IA64_LAST_DEVICE_VECTOR; vector++) { | |
329 | int irq; | |
330 | struct irq_desc *desc; | |
331 | struct irq_cfg *cfg; | |
6065a244 | 332 | irq = __this_cpu_read(vector_irq[vector]); |
a6cd6322 KK |
333 | if (irq < 0) |
334 | continue; | |
335 | ||
a2178334 | 336 | desc = irq_to_desc(irq); |
a6cd6322 | 337 | cfg = irq_cfg + irq; |
239007b8 | 338 | raw_spin_lock(&desc->lock); |
a6cd6322 KK |
339 | if (!cfg->move_cleanup_count) |
340 | goto unlock; | |
341 | ||
5d2068da | 342 | if (!cpumask_test_cpu(me, &cfg->old_domain)) |
a6cd6322 KK |
343 | goto unlock; |
344 | ||
345 | spin_lock_irqsave(&vector_lock, flags); | |
6065a244 | 346 | __this_cpu_write(vector_irq[vector], -1); |
5d2068da | 347 | cpumask_clear_cpu(me, &vector_table[vector]); |
a6cd6322 KK |
348 | spin_unlock_irqrestore(&vector_lock, flags); |
349 | cfg->move_cleanup_count--; | |
350 | unlock: | |
239007b8 | 351 | raw_spin_unlock(&desc->lock); |
a6cd6322 KK |
352 | } |
353 | return IRQ_HANDLED; | |
354 | } | |
355 | ||
356 | static struct irqaction irq_move_irqaction = { | |
357 | .handler = smp_irq_move_cleanup_interrupt, | |
a6cd6322 KK |
358 | .name = "irq_move" |
359 | }; | |
360 | ||
d080d397 YI |
361 | static int __init parse_vector_domain(char *arg) |
362 | { | |
363 | if (!arg) | |
364 | return -EINVAL; | |
365 | if (!strcmp(arg, "percpu")) { | |
366 | vector_domain_type = VECTOR_DOMAIN_PERCPU; | |
367 | no_int_routing = 1; | |
368 | } | |
074ff856 | 369 | return 0; |
d080d397 YI |
370 | } |
371 | early_param("vector", parse_vector_domain); | |
372 | #else | |
373 | static cpumask_t vector_allocation_domain(int cpu) | |
374 | { | |
375 | return CPU_MASK_ALL; | |
376 | } | |
377 | #endif | |
378 | ||
4994be1b | 379 | |
e1b30a39 YI |
380 | void destroy_and_reserve_irq(unsigned int irq) |
381 | { | |
216fcd29 KK |
382 | unsigned long flags; |
383 | ||
4debd723 | 384 | irq_init_desc(irq); |
216fcd29 KK |
385 | spin_lock_irqsave(&vector_lock, flags); |
386 | __clear_irq_vector(irq); | |
387 | irq_status[irq] = IRQ_RSVD; | |
388 | spin_unlock_irqrestore(&vector_lock, flags); | |
10083072 MM |
389 | } |
390 | ||
b6cf2583 EB |
391 | /* |
392 | * Dynamic irq allocate and deallocation for MSI | |
393 | */ | |
394 | int create_irq(void) | |
395 | { | |
e1b30a39 | 396 | unsigned long flags; |
4994be1b | 397 | int irq, vector, cpu; |
373167e8 | 398 | cpumask_t domain = CPU_MASK_NONE; |
e1b30a39 | 399 | |
4994be1b | 400 | irq = vector = -ENOSPC; |
e1b30a39 | 401 | spin_lock_irqsave(&vector_lock, flags); |
4994be1b YI |
402 | for_each_online_cpu(cpu) { |
403 | domain = vector_allocation_domain(cpu); | |
404 | vector = find_unassigned_vector(domain); | |
405 | if (vector >= 0) | |
406 | break; | |
407 | } | |
e1b30a39 YI |
408 | if (vector < 0) |
409 | goto out; | |
410 | irq = find_unassigned_irq(); | |
411 | if (irq < 0) | |
412 | goto out; | |
4994be1b | 413 | BUG_ON(__bind_irq_vector(irq, vector, domain)); |
e1b30a39 YI |
414 | out: |
415 | spin_unlock_irqrestore(&vector_lock, flags); | |
416 | if (irq >= 0) | |
4debd723 | 417 | irq_init_desc(irq); |
e1b30a39 | 418 | return irq; |
b6cf2583 EB |
419 | } |
420 | ||
421 | void destroy_irq(unsigned int irq) | |
422 | { | |
4debd723 | 423 | irq_init_desc(irq); |
e1b30a39 | 424 | clear_irq_vector(irq); |
b6cf2583 EB |
425 | } |
426 | ||
1da177e4 LT |
427 | #ifdef CONFIG_SMP |
428 | # define IS_RESCHEDULE(vec) (vec == IA64_IPI_RESCHEDULE) | |
3be44b9c | 429 | # define IS_LOCAL_TLB_FLUSH(vec) (vec == IA64_IPI_LOCAL_TLB_FLUSH) |
1da177e4 LT |
430 | #else |
431 | # define IS_RESCHEDULE(vec) (0) | |
3be44b9c | 432 | # define IS_LOCAL_TLB_FLUSH(vec) (0) |
1da177e4 LT |
433 | #endif |
434 | /* | |
435 | * That's where the IVT branches when we get an external | |
436 | * interrupt. This branches to the correct hardware IRQ handler via | |
437 | * function ptr. | |
438 | */ | |
439 | void | |
440 | ia64_handle_irq (ia64_vector vector, struct pt_regs *regs) | |
441 | { | |
7d12e780 | 442 | struct pt_regs *old_regs = set_irq_regs(regs); |
1da177e4 LT |
443 | unsigned long saved_tpr; |
444 | ||
445 | #if IRQ_DEBUG | |
446 | { | |
447 | unsigned long bsp, sp; | |
448 | ||
449 | /* | |
450 | * Note: if the interrupt happened while executing in | |
451 | * the context switch routine (ia64_switch_to), we may | |
452 | * get a spurious stack overflow here. This is | |
453 | * because the register and the memory stack are not | |
454 | * switched atomically. | |
455 | */ | |
456 | bsp = ia64_getreg(_IA64_REG_AR_BSP); | |
457 | sp = ia64_getreg(_IA64_REG_SP); | |
458 | ||
459 | if ((sp - bsp) < 1024) { | |
7683a3f9 | 460 | static DEFINE_RATELIMIT_STATE(ratelimit, 5 * HZ, 5); |
1da177e4 | 461 | |
7683a3f9 | 462 | if (__ratelimit(&ratelimit)) { |
1da177e4 LT |
463 | printk("ia64_handle_irq: DANGER: less than " |
464 | "1KB of free stack space!!\n" | |
465 | "(bsp=0x%lx, sp=%lx)\n", bsp, sp); | |
466 | } | |
467 | } | |
468 | } | |
469 | #endif /* IRQ_DEBUG */ | |
470 | ||
471 | /* | |
472 | * Always set TPR to limit maximum interrupt nesting depth to | |
473 | * 16 (without this, it would be ~240, which could easily lead | |
474 | * to kernel stack overflows). | |
475 | */ | |
476 | irq_enter(); | |
477 | saved_tpr = ia64_getreg(_IA64_REG_CR_TPR); | |
478 | ia64_srlz_d(); | |
479 | while (vector != IA64_SPURIOUS_INT_VECTOR) { | |
66f3e6af JS |
480 | int irq = local_vector_to_irq(vector); |
481 | ||
3be44b9c JS |
482 | if (unlikely(IS_LOCAL_TLB_FLUSH(vector))) { |
483 | smp_local_flush_tlb(); | |
3611587a | 484 | kstat_incr_irq_this_cpu(irq); |
7c730ccd | 485 | } else if (unlikely(IS_RESCHEDULE(vector))) { |
184748cc | 486 | scheduler_ipi(); |
3611587a | 487 | kstat_incr_irq_this_cpu(irq); |
7c730ccd | 488 | } else { |
1da177e4 LT |
489 | ia64_setreg(_IA64_REG_CR_TPR, vector); |
490 | ia64_srlz_d(); | |
491 | ||
17764d24 KK |
492 | if (unlikely(irq < 0)) { |
493 | printk(KERN_ERR "%s: Unexpected interrupt " | |
494 | "vector %d on CPU %d is not mapped " | |
d4ed8084 | 495 | "to any IRQ!\n", __func__, vector, |
17764d24 KK |
496 | smp_processor_id()); |
497 | } else | |
498 | generic_handle_irq(irq); | |
1da177e4 LT |
499 | |
500 | /* | |
501 | * Disable interrupts and send EOI: | |
502 | */ | |
503 | local_irq_disable(); | |
504 | ia64_setreg(_IA64_REG_CR_TPR, saved_tpr); | |
505 | } | |
506 | ia64_eoi(); | |
507 | vector = ia64_get_ivr(); | |
508 | } | |
509 | /* | |
510 | * This must be done *after* the ia64_eoi(). For example, the keyboard softirq | |
511 | * handler needs to be able to wait for further keyboard interrupts, which can't | |
512 | * come through until ia64_eoi() has been done. | |
513 | */ | |
514 | irq_exit(); | |
7d12e780 | 515 | set_irq_regs(old_regs); |
1da177e4 LT |
516 | } |
517 | ||
518 | #ifdef CONFIG_HOTPLUG_CPU | |
519 | /* | |
520 | * This function emulates a interrupt processing when a cpu is about to be | |
521 | * brought down. | |
522 | */ | |
523 | void ia64_process_pending_intr(void) | |
524 | { | |
525 | ia64_vector vector; | |
526 | unsigned long saved_tpr; | |
527 | extern unsigned int vectors_in_migration[NR_IRQS]; | |
528 | ||
529 | vector = ia64_get_ivr(); | |
530 | ||
66f3e6af JS |
531 | irq_enter(); |
532 | saved_tpr = ia64_getreg(_IA64_REG_CR_TPR); | |
533 | ia64_srlz_d(); | |
1da177e4 LT |
534 | |
535 | /* | |
536 | * Perform normal interrupt style processing | |
537 | */ | |
538 | while (vector != IA64_SPURIOUS_INT_VECTOR) { | |
66f3e6af | 539 | int irq = local_vector_to_irq(vector); |
66f3e6af | 540 | |
3be44b9c JS |
541 | if (unlikely(IS_LOCAL_TLB_FLUSH(vector))) { |
542 | smp_local_flush_tlb(); | |
3611587a | 543 | kstat_incr_irq_this_cpu(irq); |
7c730ccd | 544 | } else if (unlikely(IS_RESCHEDULE(vector))) { |
3611587a | 545 | kstat_incr_irq_this_cpu(irq); |
7c730ccd | 546 | } else { |
8c1addbc TL |
547 | struct pt_regs *old_regs = set_irq_regs(NULL); |
548 | ||
1da177e4 LT |
549 | ia64_setreg(_IA64_REG_CR_TPR, vector); |
550 | ia64_srlz_d(); | |
551 | ||
552 | /* | |
553 | * Now try calling normal ia64_handle_irq as it would have got called | |
554 | * from a real intr handler. Try passing null for pt_regs, hopefully | |
555 | * it will work. I hope it works!. | |
556 | * Probably could shared code. | |
557 | */ | |
17764d24 KK |
558 | if (unlikely(irq < 0)) { |
559 | printk(KERN_ERR "%s: Unexpected interrupt " | |
560 | "vector %d on CPU %d not being mapped " | |
d4ed8084 | 561 | "to any IRQ!!\n", __func__, vector, |
17764d24 KK |
562 | smp_processor_id()); |
563 | } else { | |
564 | vectors_in_migration[irq]=0; | |
565 | generic_handle_irq(irq); | |
566 | } | |
8c1addbc | 567 | set_irq_regs(old_regs); |
1da177e4 LT |
568 | |
569 | /* | |
570 | * Disable interrupts and send EOI | |
571 | */ | |
572 | local_irq_disable(); | |
573 | ia64_setreg(_IA64_REG_CR_TPR, saved_tpr); | |
574 | } | |
575 | ia64_eoi(); | |
576 | vector = ia64_get_ivr(); | |
577 | } | |
578 | irq_exit(); | |
579 | } | |
580 | #endif | |
581 | ||
582 | ||
583 | #ifdef CONFIG_SMP | |
1da177e4 | 584 | |
9b3377f9 JS |
585 | static irqreturn_t dummy_handler (int irq, void *dev_id) |
586 | { | |
587 | BUG(); | |
588 | } | |
589 | ||
1da177e4 LT |
590 | static struct irqaction ipi_irqaction = { |
591 | .handler = handle_IPI, | |
1da177e4 LT |
592 | .name = "IPI" |
593 | }; | |
9b3377f9 | 594 | |
32f88400 MT |
595 | /* |
596 | * KVM uses this interrupt to force a cpu out of guest mode | |
597 | */ | |
9b3377f9 JS |
598 | static struct irqaction resched_irqaction = { |
599 | .handler = dummy_handler, | |
9b3377f9 JS |
600 | .name = "resched" |
601 | }; | |
3be44b9c JS |
602 | |
603 | static struct irqaction tlb_irqaction = { | |
604 | .handler = dummy_handler, | |
3be44b9c JS |
605 | .name = "tlb_flush" |
606 | }; | |
607 | ||
1da177e4 LT |
608 | #endif |
609 | ||
610 | void | |
85cbc503 | 611 | ia64_native_register_percpu_irq (ia64_vector vec, struct irqaction *action) |
1da177e4 | 612 | { |
1da177e4 LT |
613 | unsigned int irq; |
614 | ||
e1b30a39 | 615 | irq = vec; |
4994be1b | 616 | BUG_ON(bind_irq_vector(irq, vec, CPU_MASK_ALL)); |
a2178334 | 617 | irq_set_status_flags(irq, IRQ_PER_CPU); |
53c909c9 | 618 | irq_set_chip(irq, &irq_type_ia64_lsapic); |
e1b30a39 YI |
619 | if (action) |
620 | setup_irq(irq, action); | |
53c909c9 | 621 | irq_set_handler(irq, handle_percpu_irq); |
1da177e4 LT |
622 | } |
623 | ||
624 | void __init | |
85cbc503 | 625 | ia64_native_register_ipi(void) |
1da177e4 | 626 | { |
1da177e4 LT |
627 | #ifdef CONFIG_SMP |
628 | register_percpu_irq(IA64_IPI_VECTOR, &ipi_irqaction); | |
9b3377f9 | 629 | register_percpu_irq(IA64_IPI_RESCHEDULE, &resched_irqaction); |
3be44b9c | 630 | register_percpu_irq(IA64_IPI_LOCAL_TLB_FLUSH, &tlb_irqaction); |
85cbc503 IY |
631 | #endif |
632 | } | |
633 | ||
634 | void __init | |
635 | init_IRQ (void) | |
636 | { | |
4de0a759 TL |
637 | #ifdef CONFIG_ACPI |
638 | acpi_boot_init(); | |
639 | #endif | |
85cbc503 IY |
640 | ia64_register_ipi(); |
641 | register_percpu_irq(IA64_SPURIOUS_INT_VECTOR, NULL); | |
642 | #ifdef CONFIG_SMP | |
a6cd6322 | 643 | #if defined(CONFIG_IA64_GENERIC) || defined(CONFIG_IA64_DIG) |
09b366b7 | 644 | if (vector_domain_type != VECTOR_DOMAIN_NONE) |
a6cd6322 | 645 | register_percpu_irq(IA64_IRQ_MOVE_VECTOR, &irq_move_irqaction); |
a6cd6322 | 646 | #endif |
1da177e4 LT |
647 | #endif |
648 | #ifdef CONFIG_PERFMON | |
649 | pfm_init_percpu(); | |
650 | #endif | |
651 | platform_irq_init(); | |
652 | } | |
653 | ||
654 | void | |
655 | ia64_send_ipi (int cpu, int vector, int delivery_mode, int redirect) | |
656 | { | |
657 | void __iomem *ipi_addr; | |
658 | unsigned long ipi_data; | |
659 | unsigned long phys_cpu_id; | |
660 | ||
1da177e4 | 661 | phys_cpu_id = cpu_physical_id(cpu); |
1da177e4 LT |
662 | |
663 | /* | |
664 | * cpu number is in 8bit ID and 8bit EID | |
665 | */ | |
666 | ||
667 | ipi_data = (delivery_mode << 8) | (vector & 0xff); | |
668 | ipi_addr = ipi_base_addr + ((phys_cpu_id << 4) | ((redirect & 1) << 3)); | |
669 | ||
670 | writeq(ipi_data, ipi_addr); | |
671 | } |