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1da177e4
LT
1/*
2 * linux/arch/ia64/kernel/irq.c
3 *
4 * Copyright (C) 1998-2001 Hewlett-Packard Co
5 * Stephane Eranian <eranian@hpl.hp.com>
6 * David Mosberger-Tang <davidm@hpl.hp.com>
7 *
8 * 6/10/99: Updated to bring in sync with x86 version to facilitate
9 * support for SMP and different interrupt controllers.
10 *
11 * 09/15/00 Goutham Rao <goutham.rao@intel.com> Implemented pci_irq_to_vector
12 * PCI to vector allocation routine.
13 * 04/14/2004 Ashok Raj <ashok.raj@intel.com>
14 * Added CPU Hotplug handling for IPF.
15 */
16
17#include <linux/config.h>
18#include <linux/module.h>
19
20#include <linux/jiffies.h>
21#include <linux/errno.h>
22#include <linux/init.h>
23#include <linux/interrupt.h>
24#include <linux/ioport.h>
25#include <linux/kernel_stat.h>
26#include <linux/slab.h>
27#include <linux/ptrace.h>
28#include <linux/random.h> /* for rand_initialize_irq() */
29#include <linux/signal.h>
30#include <linux/smp.h>
31#include <linux/smp_lock.h>
32#include <linux/threads.h>
33#include <linux/bitops.h>
34
35#include <asm/delay.h>
36#include <asm/intrinsics.h>
37#include <asm/io.h>
38#include <asm/hw_irq.h>
39#include <asm/machvec.h>
40#include <asm/pgtable.h>
41#include <asm/system.h>
42
43#ifdef CONFIG_PERFMON
44# include <asm/perfmon.h>
45#endif
46
47#define IRQ_DEBUG 0
48
10083072
MM
49/* These can be overridden in platform_irq_init */
50int ia64_first_device_vector = IA64_DEF_FIRST_DEVICE_VECTOR;
51int ia64_last_device_vector = IA64_DEF_LAST_DEVICE_VECTOR;
52
1da177e4
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53/* default base addr of IPI table */
54void __iomem *ipi_base_addr = ((void __iomem *)
55 (__IA64_UNCACHED_OFFSET | IA64_IPI_DEFAULT_BASE_ADDR));
56
57/*
58 * Legacy IRQ to IA-64 vector translation table.
59 */
60__u8 isa_irq_to_vector_map[16] = {
61 /* 8259 IRQ translation, first 16 entries */
62 0x2f, 0x20, 0x2e, 0x2d, 0x2c, 0x2b, 0x2a, 0x29,
63 0x28, 0x27, 0x26, 0x25, 0x24, 0x23, 0x22, 0x21
64};
65EXPORT_SYMBOL(isa_irq_to_vector_map);
66
10083072 67static unsigned long ia64_vector_mask[BITS_TO_LONGS(IA64_MAX_DEVICE_VECTORS)];
1da177e4
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68
69int
3b5cc090 70assign_irq_vector (int irq)
1da177e4
LT
71{
72 int pos, vector;
73 again:
74 pos = find_first_zero_bit(ia64_vector_mask, IA64_NUM_DEVICE_VECTORS);
75 vector = IA64_FIRST_DEVICE_VECTOR + pos;
76 if (vector > IA64_LAST_DEVICE_VECTOR)
3b5cc090 77 return -ENOSPC;
1da177e4
LT
78 if (test_and_set_bit(pos, ia64_vector_mask))
79 goto again;
80 return vector;
81}
82
83void
84free_irq_vector (int vector)
85{
86 int pos;
87
88 if (vector < IA64_FIRST_DEVICE_VECTOR || vector > IA64_LAST_DEVICE_VECTOR)
89 return;
90
91 pos = vector - IA64_FIRST_DEVICE_VECTOR;
92 if (!test_and_clear_bit(pos, ia64_vector_mask))
93 printk(KERN_WARNING "%s: double free!\n", __FUNCTION__);
94}
95
10083072
MM
96int
97reserve_irq_vector (int vector)
98{
99 int pos;
100
101 if (vector < IA64_FIRST_DEVICE_VECTOR ||
102 vector > IA64_LAST_DEVICE_VECTOR)
103 return -EINVAL;
104
105 pos = vector - IA64_FIRST_DEVICE_VECTOR;
106 return test_and_set_bit(pos, ia64_vector_mask);
107}
108
1da177e4
LT
109#ifdef CONFIG_SMP
110# define IS_RESCHEDULE(vec) (vec == IA64_IPI_RESCHEDULE)
111#else
112# define IS_RESCHEDULE(vec) (0)
113#endif
114/*
115 * That's where the IVT branches when we get an external
116 * interrupt. This branches to the correct hardware IRQ handler via
117 * function ptr.
118 */
119void
120ia64_handle_irq (ia64_vector vector, struct pt_regs *regs)
121{
122 unsigned long saved_tpr;
123
124#if IRQ_DEBUG
125 {
126 unsigned long bsp, sp;
127
128 /*
129 * Note: if the interrupt happened while executing in
130 * the context switch routine (ia64_switch_to), we may
131 * get a spurious stack overflow here. This is
132 * because the register and the memory stack are not
133 * switched atomically.
134 */
135 bsp = ia64_getreg(_IA64_REG_AR_BSP);
136 sp = ia64_getreg(_IA64_REG_SP);
137
138 if ((sp - bsp) < 1024) {
139 static unsigned char count;
140 static long last_time;
141
142 if (jiffies - last_time > 5*HZ)
143 count = 0;
144 if (++count < 5) {
145 last_time = jiffies;
146 printk("ia64_handle_irq: DANGER: less than "
147 "1KB of free stack space!!\n"
148 "(bsp=0x%lx, sp=%lx)\n", bsp, sp);
149 }
150 }
151 }
152#endif /* IRQ_DEBUG */
153
154 /*
155 * Always set TPR to limit maximum interrupt nesting depth to
156 * 16 (without this, it would be ~240, which could easily lead
157 * to kernel stack overflows).
158 */
159 irq_enter();
160 saved_tpr = ia64_getreg(_IA64_REG_CR_TPR);
161 ia64_srlz_d();
162 while (vector != IA64_SPURIOUS_INT_VECTOR) {
163 if (!IS_RESCHEDULE(vector)) {
164 ia64_setreg(_IA64_REG_CR_TPR, vector);
165 ia64_srlz_d();
166
167 __do_IRQ(local_vector_to_irq(vector), regs);
168
169 /*
170 * Disable interrupts and send EOI:
171 */
172 local_irq_disable();
173 ia64_setreg(_IA64_REG_CR_TPR, saved_tpr);
174 }
175 ia64_eoi();
176 vector = ia64_get_ivr();
177 }
178 /*
179 * This must be done *after* the ia64_eoi(). For example, the keyboard softirq
180 * handler needs to be able to wait for further keyboard interrupts, which can't
181 * come through until ia64_eoi() has been done.
182 */
183 irq_exit();
184}
185
186#ifdef CONFIG_HOTPLUG_CPU
187/*
188 * This function emulates a interrupt processing when a cpu is about to be
189 * brought down.
190 */
191void ia64_process_pending_intr(void)
192{
193 ia64_vector vector;
194 unsigned long saved_tpr;
195 extern unsigned int vectors_in_migration[NR_IRQS];
196
197 vector = ia64_get_ivr();
198
199 irq_enter();
200 saved_tpr = ia64_getreg(_IA64_REG_CR_TPR);
201 ia64_srlz_d();
202
203 /*
204 * Perform normal interrupt style processing
205 */
206 while (vector != IA64_SPURIOUS_INT_VECTOR) {
207 if (!IS_RESCHEDULE(vector)) {
208 ia64_setreg(_IA64_REG_CR_TPR, vector);
209 ia64_srlz_d();
210
211 /*
212 * Now try calling normal ia64_handle_irq as it would have got called
213 * from a real intr handler. Try passing null for pt_regs, hopefully
214 * it will work. I hope it works!.
215 * Probably could shared code.
216 */
217 vectors_in_migration[local_vector_to_irq(vector)]=0;
218 __do_IRQ(local_vector_to_irq(vector), NULL);
219
220 /*
221 * Disable interrupts and send EOI
222 */
223 local_irq_disable();
224 ia64_setreg(_IA64_REG_CR_TPR, saved_tpr);
225 }
226 ia64_eoi();
227 vector = ia64_get_ivr();
228 }
229 irq_exit();
230}
231#endif
232
233
234#ifdef CONFIG_SMP
235extern irqreturn_t handle_IPI (int irq, void *dev_id, struct pt_regs *regs);
236
237static struct irqaction ipi_irqaction = {
238 .handler = handle_IPI,
239 .flags = SA_INTERRUPT,
240 .name = "IPI"
241};
242#endif
243
244void
245register_percpu_irq (ia64_vector vec, struct irqaction *action)
246{
247 irq_desc_t *desc;
248 unsigned int irq;
249
250 for (irq = 0; irq < NR_IRQS; ++irq)
251 if (irq_to_vector(irq) == vec) {
252 desc = irq_descp(irq);
253 desc->status |= IRQ_PER_CPU;
254 desc->handler = &irq_type_ia64_lsapic;
255 if (action)
256 setup_irq(irq, action);
257 }
258}
259
260void __init
261init_IRQ (void)
262{
263 register_percpu_irq(IA64_SPURIOUS_INT_VECTOR, NULL);
264#ifdef CONFIG_SMP
265 register_percpu_irq(IA64_IPI_VECTOR, &ipi_irqaction);
266#endif
267#ifdef CONFIG_PERFMON
268 pfm_init_percpu();
269#endif
270 platform_irq_init();
271}
272
273void
274ia64_send_ipi (int cpu, int vector, int delivery_mode, int redirect)
275{
276 void __iomem *ipi_addr;
277 unsigned long ipi_data;
278 unsigned long phys_cpu_id;
279
280#ifdef CONFIG_SMP
281 phys_cpu_id = cpu_physical_id(cpu);
282#else
283 phys_cpu_id = (ia64_getreg(_IA64_REG_CR_LID) >> 16) & 0xffff;
284#endif
285
286 /*
287 * cpu number is in 8bit ID and 8bit EID
288 */
289
290 ipi_data = (delivery_mode << 8) | (vector & 0xff);
291 ipi_addr = ipi_base_addr + ((phys_cpu_id << 4) | ((redirect & 1) << 3));
292
293 writeq(ipi_data, ipi_addr);
294}