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1da177e4 LT |
1 | /* |
2 | * arch/ia64/kernel/ivt.S | |
3 | * | |
060561ff | 4 | * Copyright (C) 1998-2001, 2003, 2005 Hewlett-Packard Co |
1da177e4 LT |
5 | * Stephane Eranian <eranian@hpl.hp.com> |
6 | * David Mosberger <davidm@hpl.hp.com> | |
7 | * Copyright (C) 2000, 2002-2003 Intel Co | |
8 | * Asit Mallick <asit.k.mallick@intel.com> | |
9 | * Suresh Siddha <suresh.b.siddha@intel.com> | |
10 | * Kenneth Chen <kenneth.w.chen@intel.com> | |
11 | * Fenghua Yu <fenghua.yu@intel.com> | |
12 | * | |
13 | * 00/08/23 Asit Mallick <asit.k.mallick@intel.com> TLB handling for SMP | |
14 | * 00/12/20 David Mosberger-Tang <davidm@hpl.hp.com> DTLB/ITLB handler now uses virtual PT. | |
15 | */ | |
16 | /* | |
17 | * This file defines the interruption vector table used by the CPU. | |
18 | * It does not include one entry per possible cause of interruption. | |
19 | * | |
20 | * The first 20 entries of the table contain 64 bundles each while the | |
21 | * remaining 48 entries contain only 16 bundles each. | |
22 | * | |
23 | * The 64 bundles are used to allow inlining the whole handler for critical | |
24 | * interruptions like TLB misses. | |
25 | * | |
26 | * For each entry, the comment is as follows: | |
27 | * | |
28 | * // 0x1c00 Entry 7 (size 64 bundles) Data Key Miss (12,51) | |
29 | * entry offset ----/ / / / / | |
30 | * entry number ---------/ / / / | |
31 | * size of the entry -------------/ / / | |
32 | * vector name -------------------------------------/ / | |
33 | * interruptions triggering this vector ----------------------/ | |
34 | * | |
35 | * The table is 32KB in size and must be aligned on 32KB boundary. | |
36 | * (The CPU ignores the 15 lower bits of the address) | |
37 | * | |
38 | * Table is based upon EAS2.6 (Oct 1999) | |
39 | */ | |
40 | ||
1da177e4 LT |
41 | |
42 | #include <asm/asmmacro.h> | |
43 | #include <asm/break.h> | |
44 | #include <asm/ia32.h> | |
45 | #include <asm/kregs.h> | |
39e01cb8 | 46 | #include <asm/asm-offsets.h> |
1da177e4 LT |
47 | #include <asm/pgtable.h> |
48 | #include <asm/processor.h> | |
49 | #include <asm/ptrace.h> | |
50 | #include <asm/system.h> | |
51 | #include <asm/thread_info.h> | |
52 | #include <asm/unistd.h> | |
53 | #include <asm/errno.h> | |
54 | ||
55 | #if 1 | |
56 | # define PSR_DEFAULT_BITS psr.ac | |
57 | #else | |
58 | # define PSR_DEFAULT_BITS 0 | |
59 | #endif | |
60 | ||
61 | #if 0 | |
62 | /* | |
63 | * This lets you track the last eight faults that occurred on the CPU. Make sure ar.k2 isn't | |
64 | * needed for something else before enabling this... | |
65 | */ | |
66 | # define DBG_FAULT(i) mov r16=ar.k2;; shl r16=r16,8;; add r16=(i),r16;;mov ar.k2=r16 | |
67 | #else | |
68 | # define DBG_FAULT(i) | |
69 | #endif | |
70 | ||
1da177e4 LT |
71 | #include "minstate.h" |
72 | ||
73 | #define FAULT(n) \ | |
74 | mov r31=pr; \ | |
75 | mov r19=n;; /* prepare to save predicates */ \ | |
76 | br.sptk.many dispatch_to_fault_handler | |
77 | ||
78 | .section .text.ivt,"ax" | |
79 | ||
80 | .align 32768 // align on 32KB boundary | |
81 | .global ia64_ivt | |
82 | ia64_ivt: | |
83 | ///////////////////////////////////////////////////////////////////////////////////////// | |
84 | // 0x0000 Entry 0 (size 64 bundles) VHPT Translation (8,20,47) | |
85 | ENTRY(vhpt_miss) | |
86 | DBG_FAULT(0) | |
87 | /* | |
88 | * The VHPT vector is invoked when the TLB entry for the virtual page table | |
89 | * is missing. This happens only as a result of a previous | |
90 | * (the "original") TLB miss, which may either be caused by an instruction | |
91 | * fetch or a data access (or non-access). | |
92 | * | |
e8aabc47 KC |
93 | * What we do here is normal TLB miss handing for the _original_ miss, |
94 | * followed by inserting the TLB entry for the virtual page table page | |
95 | * that the VHPT walker was attempting to access. The latter gets | |
96 | * inserted as long as page table entry above pte level have valid | |
97 | * mappings for the faulting address. The TLB entry for the original | |
98 | * miss gets inserted only if the pte entry indicates that the page is | |
99 | * present. | |
1da177e4 LT |
100 | * |
101 | * do_page_fault gets invoked in the following cases: | |
102 | * - the faulting virtual address uses unimplemented address bits | |
e8aabc47 | 103 | * - the faulting virtual address has no valid page table mapping |
1da177e4 LT |
104 | */ |
105 | mov r16=cr.ifa // get address that caused the TLB miss | |
106 | #ifdef CONFIG_HUGETLB_PAGE | |
107 | movl r18=PAGE_SHIFT | |
108 | mov r25=cr.itir | |
109 | #endif | |
110 | ;; | |
111 | rsm psr.dt // use physical addressing for data | |
112 | mov r31=pr // save the predicate registers | |
113 | mov r19=IA64_KR(PT_BASE) // get page table base address | |
114 | shl r21=r16,3 // shift bit 60 into sign bit | |
115 | shr.u r17=r16,61 // get the region number into r17 | |
116 | ;; | |
837cd0bd | 117 | shr.u r22=r21,3 |
1da177e4 LT |
118 | #ifdef CONFIG_HUGETLB_PAGE |
119 | extr.u r26=r25,2,6 | |
120 | ;; | |
121 | cmp.ne p8,p0=r18,r26 | |
122 | sub r27=r26,r18 | |
123 | ;; | |
124 | (p8) dep r25=r18,r25,2,6 | |
125 | (p8) shr r22=r22,r27 | |
126 | #endif | |
127 | ;; | |
128 | cmp.eq p6,p7=5,r17 // is IFA pointing into to region 5? | |
e8aabc47 | 129 | shr.u r18=r22,PGDIR_SHIFT // get bottom portion of pgd index bit |
1da177e4 LT |
130 | ;; |
131 | (p7) dep r17=r17,r19,(PAGE_SHIFT-3),3 // put region number bits in place | |
132 | ||
133 | srlz.d | |
134 | LOAD_PHYSICAL(p6, r19, swapper_pg_dir) // region 5 is rooted at swapper_pg_dir | |
135 | ||
136 | .pred.rel "mutex", p6, p7 | |
137 | (p6) shr.u r21=r21,PGDIR_SHIFT+PAGE_SHIFT | |
138 | (p7) shr.u r21=r21,PGDIR_SHIFT+PAGE_SHIFT-3 | |
139 | ;; | |
e8aabc47 KC |
140 | (p6) dep r17=r18,r19,3,(PAGE_SHIFT-3) // r17=pgd_offset for region 5 |
141 | (p7) dep r17=r18,r17,3,(PAGE_SHIFT-6) // r17=pgd_offset for region[0-4] | |
1da177e4 | 142 | cmp.eq p7,p6=0,r21 // unused address bits all zeroes? |
837cd0bd | 143 | #ifdef CONFIG_PGTABLE_4 |
e8aabc47 | 144 | shr.u r28=r22,PUD_SHIFT // shift pud index into position |
837cd0bd | 145 | #else |
e8aabc47 | 146 | shr.u r18=r22,PMD_SHIFT // shift pmd index into position |
837cd0bd | 147 | #endif |
1da177e4 | 148 | ;; |
e8aabc47 | 149 | ld8 r17=[r17] // get *pgd (may be 0) |
1da177e4 | 150 | ;; |
e8aabc47 | 151 | (p7) cmp.eq p6,p7=r17,r0 // was pgd_present(*pgd) == NULL? |
837cd0bd | 152 | #ifdef CONFIG_PGTABLE_4 |
e8aabc47 | 153 | dep r28=r28,r17,3,(PAGE_SHIFT-3) // r28=pud_offset(pgd,addr) |
837cd0bd | 154 | ;; |
e8aabc47 KC |
155 | shr.u r18=r22,PMD_SHIFT // shift pmd index into position |
156 | (p7) ld8 r29=[r28] // get *pud (may be 0) | |
1da177e4 | 157 | ;; |
e8aabc47 KC |
158 | (p7) cmp.eq.or.andcm p6,p7=r29,r0 // was pud_present(*pud) == NULL? |
159 | dep r17=r18,r29,3,(PAGE_SHIFT-3) // r17=pmd_offset(pud,addr) | |
837cd0bd | 160 | #else |
e8aabc47 | 161 | dep r17=r18,r17,3,(PAGE_SHIFT-3) // r17=pmd_offset(pgd,addr) |
837cd0bd | 162 | #endif |
1da177e4 | 163 | ;; |
e8aabc47 KC |
164 | (p7) ld8 r20=[r17] // get *pmd (may be 0) |
165 | shr.u r19=r22,PAGE_SHIFT // shift pte index into position | |
1da177e4 | 166 | ;; |
e8aabc47 KC |
167 | (p7) cmp.eq.or.andcm p6,p7=r20,r0 // was pmd_present(*pmd) == NULL? |
168 | dep r21=r19,r20,3,(PAGE_SHIFT-3) // r21=pte_offset(pmd,addr) | |
837cd0bd | 169 | ;; |
e8aabc47 KC |
170 | (p7) ld8 r18=[r21] // read *pte |
171 | mov r19=cr.isr // cr.isr bit 32 tells us if this is an insn miss | |
1da177e4 LT |
172 | ;; |
173 | (p7) tbit.z p6,p7=r18,_PAGE_P_BIT // page present bit cleared? | |
174 | mov r22=cr.iha // get the VHPT address that caused the TLB miss | |
175 | ;; // avoid RAW on p7 | |
176 | (p7) tbit.nz.unc p10,p11=r19,32 // is it an instruction TLB miss? | |
177 | dep r23=0,r20,0,PAGE_SHIFT // clear low bits to get page address | |
178 | ;; | |
179 | (p10) itc.i r18 // insert the instruction TLB entry | |
180 | (p11) itc.d r18 // insert the data TLB entry | |
181 | (p6) br.cond.spnt.many page_fault // handle bad address/page not present (page fault) | |
182 | mov cr.ifa=r22 | |
183 | ||
184 | #ifdef CONFIG_HUGETLB_PAGE | |
185 | (p8) mov cr.itir=r25 // change to default page-size for VHPT | |
186 | #endif | |
187 | ||
188 | /* | |
189 | * Now compute and insert the TLB entry for the virtual page table. We never | |
190 | * execute in a page table page so there is no need to set the exception deferral | |
191 | * bit. | |
192 | */ | |
193 | adds r24=__DIRTY_BITS_NO_ED|_PAGE_PL_0|_PAGE_AR_RW,r23 | |
194 | ;; | |
195 | (p7) itc.d r24 | |
196 | ;; | |
197 | #ifdef CONFIG_SMP | |
198 | /* | |
199 | * Tell the assemblers dependency-violation checker that the above "itc" instructions | |
200 | * cannot possibly affect the following loads: | |
201 | */ | |
202 | dv_serialize_data | |
203 | ||
204 | /* | |
e8aabc47 | 205 | * Re-check pagetable entry. If they changed, we may have received a ptc.g |
1da177e4 | 206 | * between reading the pagetable and the "itc". If so, flush the entry we |
e8aabc47 KC |
207 | * inserted and retry. At this point, we have: |
208 | * | |
209 | * r28 = equivalent of pud_offset(pgd, ifa) | |
210 | * r17 = equivalent of pmd_offset(pud, ifa) | |
211 | * r21 = equivalent of pte_offset(pmd, ifa) | |
212 | * | |
213 | * r29 = *pud | |
214 | * r20 = *pmd | |
215 | * r18 = *pte | |
1da177e4 | 216 | */ |
e8aabc47 KC |
217 | ld8 r25=[r21] // read *pte again |
218 | ld8 r26=[r17] // read *pmd again | |
837cd0bd | 219 | #ifdef CONFIG_PGTABLE_4 |
e8aabc47 | 220 | ld8 r19=[r28] // read *pud again |
837cd0bd RH |
221 | #endif |
222 | cmp.ne p6,p7=r0,r0 | |
1da177e4 | 223 | ;; |
e8aabc47 | 224 | cmp.ne.or.andcm p6,p7=r26,r20 // did *pmd change |
837cd0bd | 225 | #ifdef CONFIG_PGTABLE_4 |
e8aabc47 | 226 | cmp.ne.or.andcm p6,p7=r19,r29 // did *pud change |
837cd0bd | 227 | #endif |
1da177e4 LT |
228 | mov r27=PAGE_SHIFT<<2 |
229 | ;; | |
230 | (p6) ptc.l r22,r27 // purge PTE page translation | |
e8aabc47 | 231 | (p7) cmp.ne.or.andcm p6,p7=r25,r18 // did *pte change |
1da177e4 LT |
232 | ;; |
233 | (p6) ptc.l r16,r27 // purge translation | |
234 | #endif | |
235 | ||
236 | mov pr=r31,-1 // restore predicate registers | |
237 | rfi | |
238 | END(vhpt_miss) | |
239 | ||
240 | .org ia64_ivt+0x400 | |
241 | ///////////////////////////////////////////////////////////////////////////////////////// | |
242 | // 0x0400 Entry 1 (size 64 bundles) ITLB (21) | |
243 | ENTRY(itlb_miss) | |
244 | DBG_FAULT(1) | |
245 | /* | |
e8aabc47 | 246 | * The ITLB handler accesses the PTE via the virtually mapped linear |
1da177e4 | 247 | * page table. If a nested TLB miss occurs, we switch into physical |
e8aabc47 KC |
248 | * mode, walk the page table, and then re-execute the PTE read and |
249 | * go on normally after that. | |
1da177e4 LT |
250 | */ |
251 | mov r16=cr.ifa // get virtual address | |
252 | mov r29=b0 // save b0 | |
253 | mov r31=pr // save predicates | |
254 | .itlb_fault: | |
e8aabc47 | 255 | mov r17=cr.iha // get virtual address of PTE |
1da177e4 LT |
256 | movl r30=1f // load nested fault continuation point |
257 | ;; | |
e8aabc47 | 258 | 1: ld8 r18=[r17] // read *pte |
1da177e4 LT |
259 | ;; |
260 | mov b0=r29 | |
261 | tbit.z p6,p0=r18,_PAGE_P_BIT // page present bit cleared? | |
262 | (p6) br.cond.spnt page_fault | |
263 | ;; | |
264 | itc.i r18 | |
265 | ;; | |
266 | #ifdef CONFIG_SMP | |
267 | /* | |
268 | * Tell the assemblers dependency-violation checker that the above "itc" instructions | |
269 | * cannot possibly affect the following loads: | |
270 | */ | |
271 | dv_serialize_data | |
272 | ||
e8aabc47 | 273 | ld8 r19=[r17] // read *pte again and see if same |
1da177e4 LT |
274 | mov r20=PAGE_SHIFT<<2 // setup page size for purge |
275 | ;; | |
276 | cmp.ne p7,p0=r18,r19 | |
277 | ;; | |
278 | (p7) ptc.l r16,r20 | |
279 | #endif | |
280 | mov pr=r31,-1 | |
281 | rfi | |
282 | END(itlb_miss) | |
283 | ||
284 | .org ia64_ivt+0x0800 | |
285 | ///////////////////////////////////////////////////////////////////////////////////////// | |
286 | // 0x0800 Entry 2 (size 64 bundles) DTLB (9,48) | |
287 | ENTRY(dtlb_miss) | |
288 | DBG_FAULT(2) | |
289 | /* | |
e8aabc47 | 290 | * The DTLB handler accesses the PTE via the virtually mapped linear |
1da177e4 | 291 | * page table. If a nested TLB miss occurs, we switch into physical |
e8aabc47 KC |
292 | * mode, walk the page table, and then re-execute the PTE read and |
293 | * go on normally after that. | |
1da177e4 LT |
294 | */ |
295 | mov r16=cr.ifa // get virtual address | |
296 | mov r29=b0 // save b0 | |
297 | mov r31=pr // save predicates | |
298 | dtlb_fault: | |
e8aabc47 | 299 | mov r17=cr.iha // get virtual address of PTE |
1da177e4 LT |
300 | movl r30=1f // load nested fault continuation point |
301 | ;; | |
e8aabc47 | 302 | 1: ld8 r18=[r17] // read *pte |
1da177e4 LT |
303 | ;; |
304 | mov b0=r29 | |
305 | tbit.z p6,p0=r18,_PAGE_P_BIT // page present bit cleared? | |
306 | (p6) br.cond.spnt page_fault | |
307 | ;; | |
308 | itc.d r18 | |
309 | ;; | |
310 | #ifdef CONFIG_SMP | |
311 | /* | |
312 | * Tell the assemblers dependency-violation checker that the above "itc" instructions | |
313 | * cannot possibly affect the following loads: | |
314 | */ | |
315 | dv_serialize_data | |
316 | ||
e8aabc47 | 317 | ld8 r19=[r17] // read *pte again and see if same |
1da177e4 LT |
318 | mov r20=PAGE_SHIFT<<2 // setup page size for purge |
319 | ;; | |
320 | cmp.ne p7,p0=r18,r19 | |
321 | ;; | |
322 | (p7) ptc.l r16,r20 | |
323 | #endif | |
324 | mov pr=r31,-1 | |
325 | rfi | |
326 | END(dtlb_miss) | |
327 | ||
328 | .org ia64_ivt+0x0c00 | |
329 | ///////////////////////////////////////////////////////////////////////////////////////// | |
330 | // 0x0c00 Entry 3 (size 64 bundles) Alt ITLB (19) | |
331 | ENTRY(alt_itlb_miss) | |
332 | DBG_FAULT(3) | |
333 | mov r16=cr.ifa // get address that caused the TLB miss | |
334 | movl r17=PAGE_KERNEL | |
335 | mov r21=cr.ipsr | |
336 | movl r19=(((1 << IA64_MAX_PHYS_BITS) - 1) & ~0xfff) | |
337 | mov r31=pr | |
338 | ;; | |
339 | #ifdef CONFIG_DISABLE_VHPT | |
340 | shr.u r22=r16,61 // get the region number into r21 | |
341 | ;; | |
342 | cmp.gt p8,p0=6,r22 // user mode | |
343 | ;; | |
344 | (p8) thash r17=r16 | |
345 | ;; | |
346 | (p8) mov cr.iha=r17 | |
347 | (p8) mov r29=b0 // save b0 | |
348 | (p8) br.cond.dptk .itlb_fault | |
349 | #endif | |
350 | extr.u r23=r21,IA64_PSR_CPL0_BIT,2 // extract psr.cpl | |
351 | and r19=r19,r16 // clear ed, reserved bits, and PTE control bits | |
352 | shr.u r18=r16,57 // move address bit 61 to bit 4 | |
353 | ;; | |
354 | andcm r18=0x10,r18 // bit 4=~address-bit(61) | |
355 | cmp.ne p8,p0=r0,r23 // psr.cpl != 0? | |
356 | or r19=r17,r19 // insert PTE control bits into r19 | |
357 | ;; | |
358 | or r19=r19,r18 // set bit 4 (uncached) if the access was to region 6 | |
359 | (p8) br.cond.spnt page_fault | |
360 | ;; | |
361 | itc.i r19 // insert the TLB entry | |
362 | mov pr=r31,-1 | |
363 | rfi | |
364 | END(alt_itlb_miss) | |
365 | ||
366 | .org ia64_ivt+0x1000 | |
367 | ///////////////////////////////////////////////////////////////////////////////////////// | |
368 | // 0x1000 Entry 4 (size 64 bundles) Alt DTLB (7,46) | |
369 | ENTRY(alt_dtlb_miss) | |
370 | DBG_FAULT(4) | |
371 | mov r16=cr.ifa // get address that caused the TLB miss | |
372 | movl r17=PAGE_KERNEL | |
373 | mov r20=cr.isr | |
374 | movl r19=(((1 << IA64_MAX_PHYS_BITS) - 1) & ~0xfff) | |
375 | mov r21=cr.ipsr | |
376 | mov r31=pr | |
00b65985 | 377 | mov r24=PERCPU_ADDR |
1da177e4 LT |
378 | ;; |
379 | #ifdef CONFIG_DISABLE_VHPT | |
380 | shr.u r22=r16,61 // get the region number into r21 | |
381 | ;; | |
382 | cmp.gt p8,p0=6,r22 // access to region 0-5 | |
383 | ;; | |
384 | (p8) thash r17=r16 | |
385 | ;; | |
386 | (p8) mov cr.iha=r17 | |
387 | (p8) mov r29=b0 // save b0 | |
388 | (p8) br.cond.dptk dtlb_fault | |
389 | #endif | |
00b65985 KC |
390 | cmp.ge p10,p11=r16,r24 // access to per_cpu_data? |
391 | tbit.z p12,p0=r16,61 // access to region 6? | |
392 | mov r25=PERCPU_PAGE_SHIFT << 2 | |
393 | mov r26=PERCPU_PAGE_SIZE | |
394 | nop.m 0 | |
395 | nop.b 0 | |
396 | ;; | |
397 | (p10) mov r19=IA64_KR(PER_CPU_DATA) | |
398 | (p11) and r19=r19,r16 // clear non-ppn fields | |
1da177e4 LT |
399 | extr.u r23=r21,IA64_PSR_CPL0_BIT,2 // extract psr.cpl |
400 | and r22=IA64_ISR_CODE_MASK,r20 // get the isr.code field | |
401 | tbit.nz p6,p7=r20,IA64_ISR_SP_BIT // is speculation bit on? | |
1da177e4 LT |
402 | tbit.nz p9,p0=r20,IA64_ISR_NA_BIT // is non-access bit on? |
403 | ;; | |
00b65985 KC |
404 | (p10) sub r19=r19,r26 |
405 | (p10) mov cr.itir=r25 | |
1da177e4 LT |
406 | cmp.ne p8,p0=r0,r23 |
407 | (p9) cmp.eq.or.andcm p6,p7=IA64_ISR_CODE_LFETCH,r22 // check isr.code field | |
00b65985 | 408 | (p12) dep r17=-1,r17,4,1 // set ma=UC for region 6 addr |
1da177e4 LT |
409 | (p8) br.cond.spnt page_fault |
410 | ||
411 | dep r21=-1,r21,IA64_PSR_ED_BIT,1 | |
1da177e4 | 412 | ;; |
00b65985 | 413 | or r19=r19,r17 // insert PTE control bits into r19 |
1da177e4 LT |
414 | (p6) mov cr.ipsr=r21 |
415 | ;; | |
416 | (p7) itc.d r19 // insert the TLB entry | |
417 | mov pr=r31,-1 | |
418 | rfi | |
419 | END(alt_dtlb_miss) | |
420 | ||
421 | .org ia64_ivt+0x1400 | |
422 | ///////////////////////////////////////////////////////////////////////////////////////// | |
423 | // 0x1400 Entry 5 (size 64 bundles) Data nested TLB (6,45) | |
424 | ENTRY(nested_dtlb_miss) | |
425 | /* | |
426 | * In the absence of kernel bugs, we get here when the virtually mapped linear | |
427 | * page table is accessed non-speculatively (e.g., in the Dirty-bit, Instruction | |
428 | * Access-bit, or Data Access-bit faults). If the DTLB entry for the virtual page | |
429 | * table is missing, a nested TLB miss fault is triggered and control is | |
430 | * transferred to this point. When this happens, we lookup the pte for the | |
431 | * faulting address by walking the page table in physical mode and return to the | |
432 | * continuation point passed in register r30 (or call page_fault if the address is | |
433 | * not mapped). | |
434 | * | |
435 | * Input: r16: faulting address | |
436 | * r29: saved b0 | |
437 | * r30: continuation address | |
438 | * r31: saved pr | |
439 | * | |
e8aabc47 | 440 | * Output: r17: physical address of PTE of faulting address |
1da177e4 LT |
441 | * r29: saved b0 |
442 | * r30: continuation address | |
443 | * r31: saved pr | |
444 | * | |
0393eed5 | 445 | * Clobbered: b0, r18, r19, r21, r22, psr.dt (cleared) |
1da177e4 LT |
446 | */ |
447 | rsm psr.dt // switch to using physical data addressing | |
448 | mov r19=IA64_KR(PT_BASE) // get the page table base address | |
449 | shl r21=r16,3 // shift bit 60 into sign bit | |
0393eed5 | 450 | mov r18=cr.itir |
1da177e4 LT |
451 | ;; |
452 | shr.u r17=r16,61 // get the region number into r17 | |
0393eed5 | 453 | extr.u r18=r18,2,6 // get the faulting page size |
1da177e4 LT |
454 | ;; |
455 | cmp.eq p6,p7=5,r17 // is faulting address in region 5? | |
0393eed5 KC |
456 | add r22=-PAGE_SHIFT,r18 // adjustment for hugetlb address |
457 | add r18=PGDIR_SHIFT-PAGE_SHIFT,r18 | |
1da177e4 | 458 | ;; |
0393eed5 KC |
459 | shr.u r22=r16,r22 |
460 | shr.u r18=r16,r18 | |
1da177e4 LT |
461 | (p7) dep r17=r17,r19,(PAGE_SHIFT-3),3 // put region number bits in place |
462 | ||
463 | srlz.d | |
464 | LOAD_PHYSICAL(p6, r19, swapper_pg_dir) // region 5 is rooted at swapper_pg_dir | |
465 | ||
466 | .pred.rel "mutex", p6, p7 | |
467 | (p6) shr.u r21=r21,PGDIR_SHIFT+PAGE_SHIFT | |
468 | (p7) shr.u r21=r21,PGDIR_SHIFT+PAGE_SHIFT-3 | |
469 | ;; | |
e8aabc47 KC |
470 | (p6) dep r17=r18,r19,3,(PAGE_SHIFT-3) // r17=pgd_offset for region 5 |
471 | (p7) dep r17=r18,r17,3,(PAGE_SHIFT-6) // r17=pgd_offset for region[0-4] | |
1da177e4 | 472 | cmp.eq p7,p6=0,r21 // unused address bits all zeroes? |
837cd0bd | 473 | #ifdef CONFIG_PGTABLE_4 |
e8aabc47 | 474 | shr.u r18=r22,PUD_SHIFT // shift pud index into position |
837cd0bd | 475 | #else |
e8aabc47 | 476 | shr.u r18=r22,PMD_SHIFT // shift pmd index into position |
837cd0bd | 477 | #endif |
1da177e4 | 478 | ;; |
e8aabc47 | 479 | ld8 r17=[r17] // get *pgd (may be 0) |
1da177e4 | 480 | ;; |
e8aabc47 KC |
481 | (p7) cmp.eq p6,p7=r17,r0 // was pgd_present(*pgd) == NULL? |
482 | dep r17=r18,r17,3,(PAGE_SHIFT-3) // r17=p[u|m]d_offset(pgd,addr) | |
1da177e4 | 483 | ;; |
837cd0bd | 484 | #ifdef CONFIG_PGTABLE_4 |
e8aabc47 KC |
485 | (p7) ld8 r17=[r17] // get *pud (may be 0) |
486 | shr.u r18=r22,PMD_SHIFT // shift pmd index into position | |
1da177e4 | 487 | ;; |
e8aabc47 KC |
488 | (p7) cmp.eq.or.andcm p6,p7=r17,r0 // was pud_present(*pud) == NULL? |
489 | dep r17=r18,r17,3,(PAGE_SHIFT-3) // r17=pmd_offset(pud,addr) | |
837cd0bd RH |
490 | ;; |
491 | #endif | |
e8aabc47 KC |
492 | (p7) ld8 r17=[r17] // get *pmd (may be 0) |
493 | shr.u r19=r22,PAGE_SHIFT // shift pte index into position | |
837cd0bd | 494 | ;; |
e8aabc47 KC |
495 | (p7) cmp.eq.or.andcm p6,p7=r17,r0 // was pmd_present(*pmd) == NULL? |
496 | dep r17=r19,r17,3,(PAGE_SHIFT-3) // r17=pte_offset(pmd,addr); | |
1da177e4 LT |
497 | (p6) br.cond.spnt page_fault |
498 | mov b0=r30 | |
499 | br.sptk.many b0 // return to continuation point | |
500 | END(nested_dtlb_miss) | |
501 | ||
502 | .org ia64_ivt+0x1800 | |
503 | ///////////////////////////////////////////////////////////////////////////////////////// | |
504 | // 0x1800 Entry 6 (size 64 bundles) Instruction Key Miss (24) | |
505 | ENTRY(ikey_miss) | |
506 | DBG_FAULT(6) | |
507 | FAULT(6) | |
508 | END(ikey_miss) | |
509 | ||
510 | //----------------------------------------------------------------------------------- | |
511 | // call do_page_fault (predicates are in r31, psr.dt may be off, r16 is faulting address) | |
512 | ENTRY(page_fault) | |
513 | ssm psr.dt | |
514 | ;; | |
515 | srlz.i | |
516 | ;; | |
517 | SAVE_MIN_WITH_COVER | |
518 | alloc r15=ar.pfs,0,0,3,0 | |
519 | mov out0=cr.ifa | |
520 | mov out1=cr.isr | |
521 | adds r3=8,r2 // set up second base pointer | |
522 | ;; | |
523 | ssm psr.ic | PSR_DEFAULT_BITS | |
524 | ;; | |
525 | srlz.i // guarantee that interruption collectin is on | |
526 | ;; | |
527 | (p15) ssm psr.i // restore psr.i | |
528 | movl r14=ia64_leave_kernel | |
529 | ;; | |
530 | SAVE_REST | |
531 | mov rp=r14 | |
532 | ;; | |
533 | adds out2=16,r12 // out2 = pointer to pt_regs | |
534 | br.call.sptk.many b6=ia64_do_page_fault // ignore return address | |
535 | END(page_fault) | |
536 | ||
537 | .org ia64_ivt+0x1c00 | |
538 | ///////////////////////////////////////////////////////////////////////////////////////// | |
539 | // 0x1c00 Entry 7 (size 64 bundles) Data Key Miss (12,51) | |
540 | ENTRY(dkey_miss) | |
541 | DBG_FAULT(7) | |
542 | FAULT(7) | |
543 | END(dkey_miss) | |
544 | ||
545 | .org ia64_ivt+0x2000 | |
546 | ///////////////////////////////////////////////////////////////////////////////////////// | |
547 | // 0x2000 Entry 8 (size 64 bundles) Dirty-bit (54) | |
548 | ENTRY(dirty_bit) | |
549 | DBG_FAULT(8) | |
550 | /* | |
551 | * What we do here is to simply turn on the dirty bit in the PTE. We need to | |
552 | * update both the page-table and the TLB entry. To efficiently access the PTE, | |
553 | * we address it through the virtual page table. Most likely, the TLB entry for | |
554 | * the relevant virtual page table page is still present in the TLB so we can | |
555 | * normally do this without additional TLB misses. In case the necessary virtual | |
556 | * page table TLB entry isn't present, we take a nested TLB miss hit where we look | |
557 | * up the physical address of the L3 PTE and then continue at label 1 below. | |
558 | */ | |
559 | mov r16=cr.ifa // get the address that caused the fault | |
560 | movl r30=1f // load continuation point in case of nested fault | |
561 | ;; | |
562 | thash r17=r16 // compute virtual address of L3 PTE | |
563 | mov r29=b0 // save b0 in case of nested fault | |
564 | mov r31=pr // save pr | |
565 | #ifdef CONFIG_SMP | |
566 | mov r28=ar.ccv // save ar.ccv | |
567 | ;; | |
568 | 1: ld8 r18=[r17] | |
569 | ;; // avoid RAW on r18 | |
570 | mov ar.ccv=r18 // set compare value for cmpxchg | |
571 | or r25=_PAGE_D|_PAGE_A,r18 // set the dirty and accessed bits | |
d8117ce5 | 572 | tbit.z p7,p6 = r18,_PAGE_P_BIT // Check present bit |
1da177e4 | 573 | ;; |
d8117ce5 | 574 | (p6) cmpxchg8.acq r26=[r17],r25,ar.ccv // Only update if page is present |
1da177e4 LT |
575 | mov r24=PAGE_SHIFT<<2 |
576 | ;; | |
d8117ce5 | 577 | (p6) cmp.eq p6,p7=r26,r18 // Only compare if page is present |
1da177e4 LT |
578 | ;; |
579 | (p6) itc.d r25 // install updated PTE | |
580 | ;; | |
581 | /* | |
582 | * Tell the assemblers dependency-violation checker that the above "itc" instructions | |
583 | * cannot possibly affect the following loads: | |
584 | */ | |
585 | dv_serialize_data | |
586 | ||
587 | ld8 r18=[r17] // read PTE again | |
588 | ;; | |
589 | cmp.eq p6,p7=r18,r25 // is it same as the newly installed | |
590 | ;; | |
591 | (p7) ptc.l r16,r24 | |
592 | mov b0=r29 // restore b0 | |
593 | mov ar.ccv=r28 | |
594 | #else | |
595 | ;; | |
596 | 1: ld8 r18=[r17] | |
597 | ;; // avoid RAW on r18 | |
598 | or r18=_PAGE_D|_PAGE_A,r18 // set the dirty and accessed bits | |
599 | mov b0=r29 // restore b0 | |
600 | ;; | |
601 | st8 [r17]=r18 // store back updated PTE | |
602 | itc.d r18 // install updated PTE | |
603 | #endif | |
604 | mov pr=r31,-1 // restore pr | |
605 | rfi | |
606 | END(dirty_bit) | |
607 | ||
608 | .org ia64_ivt+0x2400 | |
609 | ///////////////////////////////////////////////////////////////////////////////////////// | |
610 | // 0x2400 Entry 9 (size 64 bundles) Instruction Access-bit (27) | |
611 | ENTRY(iaccess_bit) | |
612 | DBG_FAULT(9) | |
613 | // Like Entry 8, except for instruction access | |
614 | mov r16=cr.ifa // get the address that caused the fault | |
615 | movl r30=1f // load continuation point in case of nested fault | |
616 | mov r31=pr // save predicates | |
617 | #ifdef CONFIG_ITANIUM | |
618 | /* | |
619 | * Erratum 10 (IFA may contain incorrect address) has "NoFix" status. | |
620 | */ | |
621 | mov r17=cr.ipsr | |
622 | ;; | |
623 | mov r18=cr.iip | |
624 | tbit.z p6,p0=r17,IA64_PSR_IS_BIT // IA64 instruction set? | |
625 | ;; | |
626 | (p6) mov r16=r18 // if so, use cr.iip instead of cr.ifa | |
627 | #endif /* CONFIG_ITANIUM */ | |
628 | ;; | |
629 | thash r17=r16 // compute virtual address of L3 PTE | |
630 | mov r29=b0 // save b0 in case of nested fault) | |
631 | #ifdef CONFIG_SMP | |
632 | mov r28=ar.ccv // save ar.ccv | |
633 | ;; | |
634 | 1: ld8 r18=[r17] | |
635 | ;; | |
636 | mov ar.ccv=r18 // set compare value for cmpxchg | |
637 | or r25=_PAGE_A,r18 // set the accessed bit | |
d8117ce5 | 638 | tbit.z p7,p6 = r18,_PAGE_P_BIT // Check present bit |
1da177e4 | 639 | ;; |
d8117ce5 | 640 | (p6) cmpxchg8.acq r26=[r17],r25,ar.ccv // Only if page present |
1da177e4 LT |
641 | mov r24=PAGE_SHIFT<<2 |
642 | ;; | |
d8117ce5 | 643 | (p6) cmp.eq p6,p7=r26,r18 // Only if page present |
1da177e4 LT |
644 | ;; |
645 | (p6) itc.i r25 // install updated PTE | |
646 | ;; | |
647 | /* | |
648 | * Tell the assemblers dependency-violation checker that the above "itc" instructions | |
649 | * cannot possibly affect the following loads: | |
650 | */ | |
651 | dv_serialize_data | |
652 | ||
653 | ld8 r18=[r17] // read PTE again | |
654 | ;; | |
655 | cmp.eq p6,p7=r18,r25 // is it same as the newly installed | |
656 | ;; | |
657 | (p7) ptc.l r16,r24 | |
658 | mov b0=r29 // restore b0 | |
659 | mov ar.ccv=r28 | |
660 | #else /* !CONFIG_SMP */ | |
661 | ;; | |
662 | 1: ld8 r18=[r17] | |
663 | ;; | |
664 | or r18=_PAGE_A,r18 // set the accessed bit | |
665 | mov b0=r29 // restore b0 | |
666 | ;; | |
667 | st8 [r17]=r18 // store back updated PTE | |
668 | itc.i r18 // install updated PTE | |
669 | #endif /* !CONFIG_SMP */ | |
670 | mov pr=r31,-1 | |
671 | rfi | |
672 | END(iaccess_bit) | |
673 | ||
674 | .org ia64_ivt+0x2800 | |
675 | ///////////////////////////////////////////////////////////////////////////////////////// | |
676 | // 0x2800 Entry 10 (size 64 bundles) Data Access-bit (15,55) | |
677 | ENTRY(daccess_bit) | |
678 | DBG_FAULT(10) | |
679 | // Like Entry 8, except for data access | |
680 | mov r16=cr.ifa // get the address that caused the fault | |
681 | movl r30=1f // load continuation point in case of nested fault | |
682 | ;; | |
683 | thash r17=r16 // compute virtual address of L3 PTE | |
684 | mov r31=pr | |
685 | mov r29=b0 // save b0 in case of nested fault) | |
686 | #ifdef CONFIG_SMP | |
687 | mov r28=ar.ccv // save ar.ccv | |
688 | ;; | |
689 | 1: ld8 r18=[r17] | |
690 | ;; // avoid RAW on r18 | |
691 | mov ar.ccv=r18 // set compare value for cmpxchg | |
692 | or r25=_PAGE_A,r18 // set the dirty bit | |
d8117ce5 | 693 | tbit.z p7,p6 = r18,_PAGE_P_BIT // Check present bit |
1da177e4 | 694 | ;; |
d8117ce5 | 695 | (p6) cmpxchg8.acq r26=[r17],r25,ar.ccv // Only if page is present |
1da177e4 LT |
696 | mov r24=PAGE_SHIFT<<2 |
697 | ;; | |
d8117ce5 | 698 | (p6) cmp.eq p6,p7=r26,r18 // Only if page is present |
1da177e4 LT |
699 | ;; |
700 | (p6) itc.d r25 // install updated PTE | |
701 | /* | |
702 | * Tell the assemblers dependency-violation checker that the above "itc" instructions | |
703 | * cannot possibly affect the following loads: | |
704 | */ | |
705 | dv_serialize_data | |
706 | ;; | |
707 | ld8 r18=[r17] // read PTE again | |
708 | ;; | |
709 | cmp.eq p6,p7=r18,r25 // is it same as the newly installed | |
710 | ;; | |
711 | (p7) ptc.l r16,r24 | |
712 | mov ar.ccv=r28 | |
713 | #else | |
714 | ;; | |
715 | 1: ld8 r18=[r17] | |
716 | ;; // avoid RAW on r18 | |
717 | or r18=_PAGE_A,r18 // set the accessed bit | |
718 | ;; | |
719 | st8 [r17]=r18 // store back updated PTE | |
720 | itc.d r18 // install updated PTE | |
721 | #endif | |
722 | mov b0=r29 // restore b0 | |
723 | mov pr=r31,-1 | |
724 | rfi | |
725 | END(daccess_bit) | |
726 | ||
727 | .org ia64_ivt+0x2c00 | |
728 | ///////////////////////////////////////////////////////////////////////////////////////// | |
729 | // 0x2c00 Entry 11 (size 64 bundles) Break instruction (33) | |
730 | ENTRY(break_fault) | |
731 | /* | |
732 | * The streamlined system call entry/exit paths only save/restore the initial part | |
733 | * of pt_regs. This implies that the callers of system-calls must adhere to the | |
734 | * normal procedure calling conventions. | |
735 | * | |
736 | * Registers to be saved & restored: | |
737 | * CR registers: cr.ipsr, cr.iip, cr.ifs | |
738 | * AR registers: ar.unat, ar.pfs, ar.rsc, ar.rnat, ar.bspstore, ar.fpsr | |
739 | * others: pr, b0, b6, loadrs, r1, r11, r12, r13, r15 | |
740 | * Registers to be restored only: | |
741 | * r8-r11: output value from the system call. | |
742 | * | |
743 | * During system call exit, scratch registers (including r15) are modified/cleared | |
744 | * to prevent leaking bits from kernel to user level. | |
745 | */ | |
746 | DBG_FAULT(11) | |
f8fa5448 DMT |
747 | mov.m r16=IA64_KR(CURRENT) // M2 r16 <- current task (12 cyc) |
748 | mov r29=cr.ipsr // M2 (12 cyc) | |
749 | mov r31=pr // I0 (2 cyc) | |
1da177e4 | 750 | |
f8fa5448 DMT |
751 | mov r17=cr.iim // M2 (2 cyc) |
752 | mov.m r27=ar.rsc // M2 (12 cyc) | |
753 | mov r18=__IA64_BREAK_SYSCALL // A | |
1da177e4 | 754 | |
f8fa5448 DMT |
755 | mov.m ar.rsc=0 // M2 |
756 | mov.m r21=ar.fpsr // M2 (12 cyc) | |
757 | mov r19=b6 // I0 (2 cyc) | |
1da177e4 | 758 | ;; |
f8fa5448 DMT |
759 | mov.m r23=ar.bspstore // M2 (12 cyc) |
760 | mov.m r24=ar.rnat // M2 (5 cyc) | |
761 | mov.i r26=ar.pfs // I0 (2 cyc) | |
1da177e4 | 762 | |
f8fa5448 DMT |
763 | invala // M0|1 |
764 | nop.m 0 // M | |
765 | mov r20=r1 // A save r1 | |
766 | ||
767 | nop.m 0 | |
768 | movl r30=sys_call_table // X | |
769 | ||
770 | mov r28=cr.iip // M2 (2 cyc) | |
771 | cmp.eq p0,p7=r18,r17 // I0 is this a system call? | |
772 | (p7) br.cond.spnt non_syscall // B no -> | |
773 | // | |
774 | // From this point on, we are definitely on the syscall-path | |
775 | // and we can use (non-banked) scratch registers. | |
776 | // | |
777 | /////////////////////////////////////////////////////////////////////// | |
778 | mov r1=r16 // A move task-pointer to "addl"-addressable reg | |
779 | mov r2=r16 // A setup r2 for ia64_syscall_setup | |
780 | add r9=TI_FLAGS+IA64_TASK_SIZE,r16 // A r9 = ¤t_thread_info()->flags | |
781 | ||
782 | adds r16=IA64_TASK_THREAD_ON_USTACK_OFFSET,r16 | |
783 | adds r15=-1024,r15 // A subtract 1024 from syscall number | |
1da177e4 LT |
784 | mov r3=NR_syscalls - 1 |
785 | ;; | |
f8fa5448 DMT |
786 | ld1.bias r17=[r16] // M0|1 r17 = current->thread.on_ustack flag |
787 | ld4 r9=[r9] // M0|1 r9 = current_thread_info()->flags | |
788 | extr.u r8=r29,41,2 // I0 extract ei field from cr.ipsr | |
1da177e4 | 789 | |
f8fa5448 DMT |
790 | shladd r30=r15,3,r30 // A r30 = sys_call_table + 8*(syscall-1024) |
791 | addl r22=IA64_RBS_OFFSET,r1 // A compute base of RBS | |
792 | cmp.leu p6,p7=r15,r3 // A syscall number in range? | |
1da177e4 | 793 | ;; |
1da177e4 | 794 | |
f8fa5448 DMT |
795 | lfetch.fault.excl.nt1 [r22] // M0|1 prefetch RBS |
796 | (p6) ld8 r30=[r30] // M0|1 load address of syscall entry point | |
797 | tnat.nz.or p7,p0=r15 // I0 is syscall nr a NaT? | |
798 | ||
799 | mov.m ar.bspstore=r22 // M2 switch to kernel RBS | |
800 | cmp.eq p8,p9=2,r8 // A isr.ei==2? | |
1da177e4 | 801 | ;; |
f8fa5448 DMT |
802 | |
803 | (p8) mov r8=0 // A clear ei to 0 | |
804 | (p7) movl r30=sys_ni_syscall // X | |
805 | ||
806 | (p8) adds r28=16,r28 // A switch cr.iip to next bundle | |
807 | (p9) adds r8=1,r8 // A increment ei to next slot | |
b64f34cd HS |
808 | #ifdef CONFIG_VIRT_CPU_ACCOUNTING |
809 | ;; | |
810 | mov b6=r30 // I0 setup syscall handler branch reg early | |
811 | #else | |
f8fa5448 | 812 | nop.i 0 |
1da177e4 | 813 | ;; |
b64f34cd | 814 | #endif |
f8fa5448 DMT |
815 | |
816 | mov.m r25=ar.unat // M2 (5 cyc) | |
817 | dep r29=r8,r29,41,2 // I0 insert new ei into cr.ipsr | |
818 | adds r15=1024,r15 // A restore original syscall number | |
819 | // | |
820 | // If any of the above loads miss in L1D, we'll stall here until | |
821 | // the data arrives. | |
822 | // | |
823 | /////////////////////////////////////////////////////////////////////// | |
824 | st1 [r16]=r0 // M2|3 clear current->thread.on_ustack flag | |
b64f34cd HS |
825 | #ifdef CONFIG_VIRT_CPU_ACCOUNTING |
826 | mov.m r30=ar.itc // M get cycle for accounting | |
827 | #else | |
f8fa5448 | 828 | mov b6=r30 // I0 setup syscall handler branch reg early |
b64f34cd | 829 | #endif |
f8fa5448 DMT |
830 | cmp.eq pKStk,pUStk=r0,r17 // A were we on kernel stacks already? |
831 | ||
832 | and r9=_TIF_SYSCALL_TRACEAUDIT,r9 // A mask trace or audit | |
833 | mov r18=ar.bsp // M2 (12 cyc) | |
834 | (pKStk) br.cond.spnt .break_fixup // B we're already in kernel-mode -- fix up RBS | |
835 | ;; | |
836 | .back_from_break_fixup: | |
837 | (pUStk) addl r1=IA64_STK_OFFSET-IA64_PT_REGS_SIZE,r1 // A compute base of memory stack | |
838 | cmp.eq p14,p0=r9,r0 // A are syscalls being traced/audited? | |
839 | br.call.sptk.many b7=ia64_syscall_setup // B | |
840 | 1: | |
b64f34cd HS |
841 | #ifdef CONFIG_VIRT_CPU_ACCOUNTING |
842 | // mov.m r30=ar.itc is called in advance, and r13 is current | |
843 | add r16=TI_AC_STAMP+IA64_TASK_SIZE,r13 // A | |
844 | add r17=TI_AC_LEAVE+IA64_TASK_SIZE,r13 // A | |
845 | (pKStk) br.cond.spnt .skip_accounting // B unlikely skip | |
846 | ;; | |
847 | ld8 r18=[r16],TI_AC_STIME-TI_AC_STAMP // M get last stamp | |
848 | ld8 r19=[r17],TI_AC_UTIME-TI_AC_LEAVE // M time at leave | |
849 | ;; | |
850 | ld8 r20=[r16],TI_AC_STAMP-TI_AC_STIME // M cumulated stime | |
851 | ld8 r21=[r17] // M cumulated utime | |
852 | sub r22=r19,r18 // A stime before leave | |
853 | ;; | |
854 | st8 [r16]=r30,TI_AC_STIME-TI_AC_STAMP // M update stamp | |
855 | sub r18=r30,r19 // A elapsed time in user | |
856 | ;; | |
857 | add r20=r20,r22 // A sum stime | |
858 | add r21=r21,r18 // A sum utime | |
859 | ;; | |
860 | st8 [r16]=r20 // M update stime | |
861 | st8 [r17]=r21 // M update utime | |
862 | ;; | |
863 | .skip_accounting: | |
864 | #endif | |
f8fa5448 DMT |
865 | mov ar.rsc=0x3 // M2 set eager mode, pl 0, LE, loadrs=0 |
866 | nop 0 | |
867 | bsw.1 // B (6 cyc) regs are saved, switch to bank 1 | |
1da177e4 | 868 | ;; |
f8fa5448 DMT |
869 | |
870 | ssm psr.ic | PSR_DEFAULT_BITS // M2 now it's safe to re-enable intr.-collection | |
871 | movl r3=ia64_ret_from_syscall // X | |
1da177e4 | 872 | ;; |
f8fa5448 DMT |
873 | |
874 | srlz.i // M0 ensure interruption collection is on | |
875 | mov rp=r3 // I0 set the real return addr | |
876 | (p10) br.cond.spnt.many ia64_ret_from_syscall // B return if bad call-frame or r15 is a NaT | |
877 | ||
878 | (p15) ssm psr.i // M2 restore psr.i | |
879 | (p14) br.call.sptk.many b6=b6 // B invoke syscall-handker (ignore return addr) | |
880 | br.cond.spnt.many ia64_trace_syscall // B do syscall-tracing thingamagic | |
1da177e4 | 881 | // NOT REACHED |
f8fa5448 DMT |
882 | /////////////////////////////////////////////////////////////////////// |
883 | // On entry, we optimistically assumed that we're coming from user-space. | |
884 | // For the rare cases where a system-call is done from within the kernel, | |
885 | // we fix things up at this point: | |
886 | .break_fixup: | |
887 | add r1=-IA64_PT_REGS_SIZE,sp // A allocate space for pt_regs structure | |
888 | mov ar.rnat=r24 // M2 restore kernel's AR.RNAT | |
889 | ;; | |
890 | mov ar.bspstore=r23 // M2 restore kernel's AR.BSPSTORE | |
891 | br.cond.sptk .back_from_break_fixup | |
1da177e4 LT |
892 | END(break_fault) |
893 | ||
894 | .org ia64_ivt+0x3000 | |
895 | ///////////////////////////////////////////////////////////////////////////////////////// | |
896 | // 0x3000 Entry 12 (size 64 bundles) External Interrupt (4) | |
897 | ENTRY(interrupt) | |
898 | DBG_FAULT(12) | |
899 | mov r31=pr // prepare to save predicates | |
900 | ;; | |
901 | SAVE_MIN_WITH_COVER // uses r31; defines r2 and r3 | |
902 | ssm psr.ic | PSR_DEFAULT_BITS | |
903 | ;; | |
904 | adds r3=8,r2 // set up second base pointer for SAVE_REST | |
905 | srlz.i // ensure everybody knows psr.ic is back on | |
906 | ;; | |
907 | SAVE_REST | |
908 | ;; | |
d2a28ad9 | 909 | MCA_RECOVER_RANGE(interrupt) |
1da177e4 LT |
910 | alloc r14=ar.pfs,0,0,2,0 // must be first in an insn group |
911 | mov out0=cr.ivr // pass cr.ivr as first arg | |
912 | add out1=16,sp // pass pointer to pt_regs as second arg | |
913 | ;; | |
914 | srlz.d // make sure we see the effect of cr.ivr | |
915 | movl r14=ia64_leave_kernel | |
916 | ;; | |
917 | mov rp=r14 | |
918 | br.call.sptk.many b6=ia64_handle_irq | |
919 | END(interrupt) | |
920 | ||
921 | .org ia64_ivt+0x3400 | |
922 | ///////////////////////////////////////////////////////////////////////////////////////// | |
923 | // 0x3400 Entry 13 (size 64 bundles) Reserved | |
924 | DBG_FAULT(13) | |
925 | FAULT(13) | |
926 | ||
927 | .org ia64_ivt+0x3800 | |
928 | ///////////////////////////////////////////////////////////////////////////////////////// | |
929 | // 0x3800 Entry 14 (size 64 bundles) Reserved | |
930 | DBG_FAULT(14) | |
931 | FAULT(14) | |
932 | ||
933 | /* | |
934 | * There is no particular reason for this code to be here, other than that | |
935 | * there happens to be space here that would go unused otherwise. If this | |
936 | * fault ever gets "unreserved", simply moved the following code to a more | |
937 | * suitable spot... | |
938 | * | |
939 | * ia64_syscall_setup() is a separate subroutine so that it can | |
940 | * allocate stacked registers so it can safely demine any | |
941 | * potential NaT values from the input registers. | |
942 | * | |
943 | * On entry: | |
944 | * - executing on bank 0 or bank 1 register set (doesn't matter) | |
945 | * - r1: stack pointer | |
946 | * - r2: current task pointer | |
947 | * - r3: preserved | |
948 | * - r11: original contents (saved ar.pfs to be saved) | |
949 | * - r12: original contents (sp to be saved) | |
950 | * - r13: original contents (tp to be saved) | |
951 | * - r15: original contents (syscall # to be saved) | |
952 | * - r18: saved bsp (after switching to kernel stack) | |
953 | * - r19: saved b6 | |
954 | * - r20: saved r1 (gp) | |
955 | * - r21: saved ar.fpsr | |
956 | * - r22: kernel's register backing store base (krbs_base) | |
957 | * - r23: saved ar.bspstore | |
958 | * - r24: saved ar.rnat | |
959 | * - r25: saved ar.unat | |
960 | * - r26: saved ar.pfs | |
961 | * - r27: saved ar.rsc | |
962 | * - r28: saved cr.iip | |
963 | * - r29: saved cr.ipsr | |
b64f34cd | 964 | * - r30: ar.itc for accounting (don't touch) |
1da177e4 LT |
965 | * - r31: saved pr |
966 | * - b0: original contents (to be saved) | |
967 | * On exit: | |
1da177e4 LT |
968 | * - p10: TRUE if syscall is invoked with more than 8 out |
969 | * registers or r15's Nat is true | |
970 | * - r1: kernel's gp | |
971 | * - r3: preserved (same as on entry) | |
972 | * - r8: -EINVAL if p10 is true | |
973 | * - r12: points to kernel stack | |
974 | * - r13: points to current task | |
f8fa5448 DMT |
975 | * - r14: preserved (same as on entry) |
976 | * - p13: preserved | |
1da177e4 LT |
977 | * - p15: TRUE if interrupts need to be re-enabled |
978 | * - ar.fpsr: set to kernel settings | |
f8fa5448 | 979 | * - b6: preserved (same as on entry) |
1da177e4 LT |
980 | */ |
981 | GLOBAL_ENTRY(ia64_syscall_setup) | |
982 | #if PT(B6) != 0 | |
983 | # error This code assumes that b6 is the first field in pt_regs. | |
984 | #endif | |
985 | st8 [r1]=r19 // save b6 | |
986 | add r16=PT(CR_IPSR),r1 // initialize first base pointer | |
987 | add r17=PT(R11),r1 // initialize second base pointer | |
988 | ;; | |
989 | alloc r19=ar.pfs,8,0,0,0 // ensure in0-in7 are writable | |
990 | st8 [r16]=r29,PT(AR_PFS)-PT(CR_IPSR) // save cr.ipsr | |
991 | tnat.nz p8,p0=in0 | |
992 | ||
993 | st8.spill [r17]=r11,PT(CR_IIP)-PT(R11) // save r11 | |
994 | tnat.nz p9,p0=in1 | |
995 | (pKStk) mov r18=r0 // make sure r18 isn't NaT | |
996 | ;; | |
997 | ||
998 | st8 [r16]=r26,PT(CR_IFS)-PT(AR_PFS) // save ar.pfs | |
999 | st8 [r17]=r28,PT(AR_UNAT)-PT(CR_IIP) // save cr.iip | |
1000 | mov r28=b0 // save b0 (2 cyc) | |
1001 | ;; | |
1002 | ||
1003 | st8 [r17]=r25,PT(AR_RSC)-PT(AR_UNAT) // save ar.unat | |
1004 | dep r19=0,r19,38,26 // clear all bits but 0..37 [I0] | |
1005 | (p8) mov in0=-1 | |
1006 | ;; | |
1007 | ||
1008 | st8 [r16]=r19,PT(AR_RNAT)-PT(CR_IFS) // store ar.pfs.pfm in cr.ifs | |
1009 | extr.u r11=r19,7,7 // I0 // get sol of ar.pfs | |
1010 | and r8=0x7f,r19 // A // get sof of ar.pfs | |
1011 | ||
1012 | st8 [r17]=r27,PT(AR_BSPSTORE)-PT(AR_RSC)// save ar.rsc | |
1013 | tbit.nz p15,p0=r29,IA64_PSR_I_BIT // I0 | |
1014 | (p9) mov in1=-1 | |
1015 | ;; | |
1016 | ||
1017 | (pUStk) sub r18=r18,r22 // r18=RSE.ndirty*8 | |
1018 | tnat.nz p10,p0=in2 | |
1019 | add r11=8,r11 | |
1020 | ;; | |
1021 | (pKStk) adds r16=PT(PR)-PT(AR_RNAT),r16 // skip over ar_rnat field | |
1022 | (pKStk) adds r17=PT(B0)-PT(AR_BSPSTORE),r17 // skip over ar_bspstore field | |
1023 | tnat.nz p11,p0=in3 | |
1024 | ;; | |
1025 | (p10) mov in2=-1 | |
1026 | tnat.nz p12,p0=in4 // [I0] | |
1027 | (p11) mov in3=-1 | |
1028 | ;; | |
1029 | (pUStk) st8 [r16]=r24,PT(PR)-PT(AR_RNAT) // save ar.rnat | |
1030 | (pUStk) st8 [r17]=r23,PT(B0)-PT(AR_BSPSTORE) // save ar.bspstore | |
1031 | shl r18=r18,16 // compute ar.rsc to be used for "loadrs" | |
1032 | ;; | |
1033 | st8 [r16]=r31,PT(LOADRS)-PT(PR) // save predicates | |
1034 | st8 [r17]=r28,PT(R1)-PT(B0) // save b0 | |
1035 | tnat.nz p13,p0=in5 // [I0] | |
1036 | ;; | |
1037 | st8 [r16]=r18,PT(R12)-PT(LOADRS) // save ar.rsc value for "loadrs" | |
1038 | st8.spill [r17]=r20,PT(R13)-PT(R1) // save original r1 | |
1039 | (p12) mov in4=-1 | |
1040 | ;; | |
1041 | ||
1042 | .mem.offset 0,0; st8.spill [r16]=r12,PT(AR_FPSR)-PT(R12) // save r12 | |
1043 | .mem.offset 8,0; st8.spill [r17]=r13,PT(R15)-PT(R13) // save r13 | |
1044 | (p13) mov in5=-1 | |
1045 | ;; | |
1046 | st8 [r16]=r21,PT(R8)-PT(AR_FPSR) // save ar.fpsr | |
f8fa5448 | 1047 | tnat.nz p13,p0=in6 |
1da177e4 LT |
1048 | cmp.lt p10,p9=r11,r8 // frame size can't be more than local+8 |
1049 | ;; | |
060561ff | 1050 | mov r8=1 |
1da177e4 LT |
1051 | (p9) tnat.nz p10,p0=r15 |
1052 | adds r12=-16,r1 // switch to kernel memory stack (with 16 bytes of scratch) | |
1053 | ||
1054 | st8.spill [r17]=r15 // save r15 | |
1055 | tnat.nz p8,p0=in7 | |
1056 | nop.i 0 | |
1057 | ||
1058 | mov r13=r2 // establish `current' | |
1059 | movl r1=__gp // establish kernel global pointer | |
1060 | ;; | |
060561ff | 1061 | st8 [r16]=r8 // ensure pt_regs.r8 != 0 (see handle_syscall_error) |
f8fa5448 | 1062 | (p13) mov in6=-1 |
1da177e4 | 1063 | (p8) mov in7=-1 |
1da177e4 LT |
1064 | |
1065 | cmp.eq pSys,pNonSys=r0,r0 // set pSys=1, pNonSys=0 | |
1066 | movl r17=FPSR_DEFAULT | |
1067 | ;; | |
1068 | mov.m ar.fpsr=r17 // set ar.fpsr to kernel default value | |
1069 | (p10) mov r8=-EINVAL | |
1070 | br.ret.sptk.many b7 | |
1071 | END(ia64_syscall_setup) | |
1072 | ||
1073 | .org ia64_ivt+0x3c00 | |
1074 | ///////////////////////////////////////////////////////////////////////////////////////// | |
1075 | // 0x3c00 Entry 15 (size 64 bundles) Reserved | |
1076 | DBG_FAULT(15) | |
1077 | FAULT(15) | |
1078 | ||
1079 | /* | |
1080 | * Squatting in this space ... | |
1081 | * | |
1082 | * This special case dispatcher for illegal operation faults allows preserved | |
1083 | * registers to be modified through a callback function (asm only) that is handed | |
1084 | * back from the fault handler in r8. Up to three arguments can be passed to the | |
1085 | * callback function by returning an aggregate with the callback as its first | |
1086 | * element, followed by the arguments. | |
1087 | */ | |
1088 | ENTRY(dispatch_illegal_op_fault) | |
1089 | .prologue | |
1090 | .body | |
1091 | SAVE_MIN_WITH_COVER | |
1092 | ssm psr.ic | PSR_DEFAULT_BITS | |
1093 | ;; | |
1094 | srlz.i // guarantee that interruption collection is on | |
1095 | ;; | |
1096 | (p15) ssm psr.i // restore psr.i | |
1097 | adds r3=8,r2 // set up second base pointer for SAVE_REST | |
1098 | ;; | |
1099 | alloc r14=ar.pfs,0,0,1,0 // must be first in insn group | |
1100 | mov out0=ar.ec | |
1101 | ;; | |
1102 | SAVE_REST | |
1103 | PT_REGS_UNWIND_INFO(0) | |
1104 | ;; | |
1105 | br.call.sptk.many rp=ia64_illegal_op_fault | |
1106 | .ret0: ;; | |
1107 | alloc r14=ar.pfs,0,0,3,0 // must be first in insn group | |
1108 | mov out0=r9 | |
1109 | mov out1=r10 | |
1110 | mov out2=r11 | |
1111 | movl r15=ia64_leave_kernel | |
1112 | ;; | |
1113 | mov rp=r15 | |
1114 | mov b6=r8 | |
1115 | ;; | |
1116 | cmp.ne p6,p0=0,r8 | |
1117 | (p6) br.call.dpnt.many b6=b6 // call returns to ia64_leave_kernel | |
1118 | br.sptk.many ia64_leave_kernel | |
1119 | END(dispatch_illegal_op_fault) | |
1120 | ||
1121 | .org ia64_ivt+0x4000 | |
1122 | ///////////////////////////////////////////////////////////////////////////////////////// | |
1123 | // 0x4000 Entry 16 (size 64 bundles) Reserved | |
1124 | DBG_FAULT(16) | |
1125 | FAULT(16) | |
1126 | ||
b64f34cd HS |
1127 | #ifdef CONFIG_VIRT_CPU_ACCOUNTING |
1128 | /* | |
1129 | * There is no particular reason for this code to be here, other than | |
1130 | * that there happens to be space here that would go unused otherwise. | |
1131 | * If this fault ever gets "unreserved", simply moved the following | |
1132 | * code to a more suitable spot... | |
1133 | * | |
1134 | * account_sys_enter is called from SAVE_MIN* macros if accounting is | |
1135 | * enabled and if the macro is entered from user mode. | |
1136 | */ | |
1137 | ENTRY(account_sys_enter) | |
1138 | // mov.m r20=ar.itc is called in advance, and r13 is current | |
1139 | add r16=TI_AC_STAMP+IA64_TASK_SIZE,r13 | |
1140 | add r17=TI_AC_LEAVE+IA64_TASK_SIZE,r13 | |
1141 | ;; | |
1142 | ld8 r18=[r16],TI_AC_STIME-TI_AC_STAMP // time at last check in kernel | |
1143 | ld8 r19=[r17],TI_AC_UTIME-TI_AC_LEAVE // time at left from kernel | |
1144 | ;; | |
1145 | ld8 r23=[r16],TI_AC_STAMP-TI_AC_STIME // cumulated stime | |
1146 | ld8 r21=[r17] // cumulated utime | |
1147 | sub r22=r19,r18 // stime before leave kernel | |
1148 | ;; | |
1149 | st8 [r16]=r20,TI_AC_STIME-TI_AC_STAMP // update stamp | |
1150 | sub r18=r20,r19 // elapsed time in user mode | |
1151 | ;; | |
1152 | add r23=r23,r22 // sum stime | |
1153 | add r21=r21,r18 // sum utime | |
1154 | ;; | |
1155 | st8 [r16]=r23 // update stime | |
1156 | st8 [r17]=r21 // update utime | |
1157 | ;; | |
1158 | br.ret.sptk.many rp | |
1159 | END(account_sys_enter) | |
1160 | #endif | |
1161 | ||
1da177e4 LT |
1162 | .org ia64_ivt+0x4400 |
1163 | ///////////////////////////////////////////////////////////////////////////////////////// | |
1164 | // 0x4400 Entry 17 (size 64 bundles) Reserved | |
1165 | DBG_FAULT(17) | |
1166 | FAULT(17) | |
1167 | ||
1168 | ENTRY(non_syscall) | |
f8fa5448 DMT |
1169 | mov ar.rsc=r27 // restore ar.rsc before SAVE_MIN_WITH_COVER |
1170 | ;; | |
1da177e4 LT |
1171 | SAVE_MIN_WITH_COVER |
1172 | ||
1173 | // There is no particular reason for this code to be here, other than that | |
1174 | // there happens to be space here that would go unused otherwise. If this | |
1175 | // fault ever gets "unreserved", simply moved the following code to a more | |
1176 | // suitable spot... | |
1177 | ||
1178 | alloc r14=ar.pfs,0,0,2,0 | |
1179 | mov out0=cr.iim | |
1180 | add out1=16,sp | |
1181 | adds r3=8,r2 // set up second base pointer for SAVE_REST | |
1182 | ||
1183 | ssm psr.ic | PSR_DEFAULT_BITS | |
1184 | ;; | |
1185 | srlz.i // guarantee that interruption collection is on | |
1186 | ;; | |
1187 | (p15) ssm psr.i // restore psr.i | |
1188 | movl r15=ia64_leave_kernel | |
1189 | ;; | |
1190 | SAVE_REST | |
1191 | mov rp=r15 | |
1192 | ;; | |
1193 | br.call.sptk.many b6=ia64_bad_break // avoid WAW on CFM and ignore return addr | |
1194 | END(non_syscall) | |
1195 | ||
1196 | .org ia64_ivt+0x4800 | |
1197 | ///////////////////////////////////////////////////////////////////////////////////////// | |
1198 | // 0x4800 Entry 18 (size 64 bundles) Reserved | |
1199 | DBG_FAULT(18) | |
1200 | FAULT(18) | |
1201 | ||
1202 | /* | |
1203 | * There is no particular reason for this code to be here, other than that | |
1204 | * there happens to be space here that would go unused otherwise. If this | |
1205 | * fault ever gets "unreserved", simply moved the following code to a more | |
1206 | * suitable spot... | |
1207 | */ | |
1208 | ||
1209 | ENTRY(dispatch_unaligned_handler) | |
1210 | SAVE_MIN_WITH_COVER | |
1211 | ;; | |
1212 | alloc r14=ar.pfs,0,0,2,0 // now it's safe (must be first in insn group!) | |
1213 | mov out0=cr.ifa | |
1214 | adds out1=16,sp | |
1215 | ||
1216 | ssm psr.ic | PSR_DEFAULT_BITS | |
1217 | ;; | |
1218 | srlz.i // guarantee that interruption collection is on | |
1219 | ;; | |
1220 | (p15) ssm psr.i // restore psr.i | |
1221 | adds r3=8,r2 // set up second base pointer | |
1222 | ;; | |
1223 | SAVE_REST | |
1224 | movl r14=ia64_leave_kernel | |
1225 | ;; | |
1226 | mov rp=r14 | |
1227 | br.sptk.many ia64_prepare_handle_unaligned | |
1228 | END(dispatch_unaligned_handler) | |
1229 | ||
1230 | .org ia64_ivt+0x4c00 | |
1231 | ///////////////////////////////////////////////////////////////////////////////////////// | |
1232 | // 0x4c00 Entry 19 (size 64 bundles) Reserved | |
1233 | DBG_FAULT(19) | |
1234 | FAULT(19) | |
1235 | ||
1236 | /* | |
1237 | * There is no particular reason for this code to be here, other than that | |
1238 | * there happens to be space here that would go unused otherwise. If this | |
1239 | * fault ever gets "unreserved", simply moved the following code to a more | |
1240 | * suitable spot... | |
1241 | */ | |
1242 | ||
1243 | ENTRY(dispatch_to_fault_handler) | |
1244 | /* | |
1245 | * Input: | |
1246 | * psr.ic: off | |
1247 | * r19: fault vector number (e.g., 24 for General Exception) | |
1248 | * r31: contains saved predicates (pr) | |
1249 | */ | |
1250 | SAVE_MIN_WITH_COVER_R19 | |
1251 | alloc r14=ar.pfs,0,0,5,0 | |
1252 | mov out0=r15 | |
1253 | mov out1=cr.isr | |
1254 | mov out2=cr.ifa | |
1255 | mov out3=cr.iim | |
1256 | mov out4=cr.itir | |
1257 | ;; | |
1258 | ssm psr.ic | PSR_DEFAULT_BITS | |
1259 | ;; | |
1260 | srlz.i // guarantee that interruption collection is on | |
1261 | ;; | |
1262 | (p15) ssm psr.i // restore psr.i | |
1263 | adds r3=8,r2 // set up second base pointer for SAVE_REST | |
1264 | ;; | |
1265 | SAVE_REST | |
1266 | movl r14=ia64_leave_kernel | |
1267 | ;; | |
1268 | mov rp=r14 | |
1269 | br.call.sptk.many b6=ia64_fault | |
1270 | END(dispatch_to_fault_handler) | |
1271 | ||
1272 | // | |
1273 | // --- End of long entries, Beginning of short entries | |
1274 | // | |
1275 | ||
1276 | .org ia64_ivt+0x5000 | |
1277 | ///////////////////////////////////////////////////////////////////////////////////////// | |
1278 | // 0x5000 Entry 20 (size 16 bundles) Page Not Present (10,22,49) | |
1279 | ENTRY(page_not_present) | |
1280 | DBG_FAULT(20) | |
1281 | mov r16=cr.ifa | |
1282 | rsm psr.dt | |
1283 | /* | |
1284 | * The Linux page fault handler doesn't expect non-present pages to be in | |
1285 | * the TLB. Flush the existing entry now, so we meet that expectation. | |
1286 | */ | |
1287 | mov r17=PAGE_SHIFT<<2 | |
1288 | ;; | |
1289 | ptc.l r16,r17 | |
1290 | ;; | |
1291 | mov r31=pr | |
1292 | srlz.d | |
1293 | br.sptk.many page_fault | |
1294 | END(page_not_present) | |
1295 | ||
1296 | .org ia64_ivt+0x5100 | |
1297 | ///////////////////////////////////////////////////////////////////////////////////////// | |
1298 | // 0x5100 Entry 21 (size 16 bundles) Key Permission (13,25,52) | |
1299 | ENTRY(key_permission) | |
1300 | DBG_FAULT(21) | |
1301 | mov r16=cr.ifa | |
1302 | rsm psr.dt | |
1303 | mov r31=pr | |
1304 | ;; | |
1305 | srlz.d | |
1306 | br.sptk.many page_fault | |
1307 | END(key_permission) | |
1308 | ||
1309 | .org ia64_ivt+0x5200 | |
1310 | ///////////////////////////////////////////////////////////////////////////////////////// | |
1311 | // 0x5200 Entry 22 (size 16 bundles) Instruction Access Rights (26) | |
1312 | ENTRY(iaccess_rights) | |
1313 | DBG_FAULT(22) | |
1314 | mov r16=cr.ifa | |
1315 | rsm psr.dt | |
1316 | mov r31=pr | |
1317 | ;; | |
1318 | srlz.d | |
1319 | br.sptk.many page_fault | |
1320 | END(iaccess_rights) | |
1321 | ||
1322 | .org ia64_ivt+0x5300 | |
1323 | ///////////////////////////////////////////////////////////////////////////////////////// | |
1324 | // 0x5300 Entry 23 (size 16 bundles) Data Access Rights (14,53) | |
1325 | ENTRY(daccess_rights) | |
1326 | DBG_FAULT(23) | |
1327 | mov r16=cr.ifa | |
1328 | rsm psr.dt | |
1329 | mov r31=pr | |
1330 | ;; | |
1331 | srlz.d | |
1332 | br.sptk.many page_fault | |
1333 | END(daccess_rights) | |
1334 | ||
1335 | .org ia64_ivt+0x5400 | |
1336 | ///////////////////////////////////////////////////////////////////////////////////////// | |
1337 | // 0x5400 Entry 24 (size 16 bundles) General Exception (5,32,34,36,38,39) | |
1338 | ENTRY(general_exception) | |
1339 | DBG_FAULT(24) | |
1340 | mov r16=cr.isr | |
1341 | mov r31=pr | |
1342 | ;; | |
1343 | cmp4.eq p6,p0=0,r16 | |
1344 | (p6) br.sptk.many dispatch_illegal_op_fault | |
1345 | ;; | |
1346 | mov r19=24 // fault number | |
1347 | br.sptk.many dispatch_to_fault_handler | |
1348 | END(general_exception) | |
1349 | ||
1350 | .org ia64_ivt+0x5500 | |
1351 | ///////////////////////////////////////////////////////////////////////////////////////// | |
1352 | // 0x5500 Entry 25 (size 16 bundles) Disabled FP-Register (35) | |
1353 | ENTRY(disabled_fp_reg) | |
1354 | DBG_FAULT(25) | |
1355 | rsm psr.dfh // ensure we can access fph | |
1356 | ;; | |
1357 | srlz.d | |
1358 | mov r31=pr | |
1359 | mov r19=25 | |
1360 | br.sptk.many dispatch_to_fault_handler | |
1361 | END(disabled_fp_reg) | |
1362 | ||
1363 | .org ia64_ivt+0x5600 | |
1364 | ///////////////////////////////////////////////////////////////////////////////////////// | |
1365 | // 0x5600 Entry 26 (size 16 bundles) Nat Consumption (11,23,37,50) | |
1366 | ENTRY(nat_consumption) | |
1367 | DBG_FAULT(26) | |
458f9355 DMT |
1368 | |
1369 | mov r16=cr.ipsr | |
1370 | mov r17=cr.isr | |
1371 | mov r31=pr // save PR | |
1372 | ;; | |
1373 | and r18=0xf,r17 // r18 = cr.ipsr.code{3:0} | |
1374 | tbit.z p6,p0=r17,IA64_ISR_NA_BIT | |
1375 | ;; | |
1376 | cmp.ne.or p6,p0=IA64_ISR_CODE_LFETCH,r18 | |
1377 | dep r16=-1,r16,IA64_PSR_ED_BIT,1 | |
1378 | (p6) br.cond.spnt 1f // branch if (cr.ispr.na == 0 || cr.ipsr.code{3:0} != LFETCH) | |
1379 | ;; | |
1380 | mov cr.ipsr=r16 // set cr.ipsr.na | |
1381 | mov pr=r31,-1 | |
1382 | ;; | |
1383 | rfi | |
1384 | ||
1385 | 1: mov pr=r31,-1 | |
1386 | ;; | |
1da177e4 LT |
1387 | FAULT(26) |
1388 | END(nat_consumption) | |
1389 | ||
1390 | .org ia64_ivt+0x5700 | |
1391 | ///////////////////////////////////////////////////////////////////////////////////////// | |
1392 | // 0x5700 Entry 27 (size 16 bundles) Speculation (40) | |
1393 | ENTRY(speculation_vector) | |
1394 | DBG_FAULT(27) | |
1395 | /* | |
1396 | * A [f]chk.[as] instruction needs to take the branch to the recovery code but | |
1397 | * this part of the architecture is not implemented in hardware on some CPUs, such | |
1398 | * as Itanium. Thus, in general we need to emulate the behavior. IIM contains | |
1399 | * the relative target (not yet sign extended). So after sign extending it we | |
1400 | * simply add it to IIP. We also need to reset the EI field of the IPSR to zero, | |
1401 | * i.e., the slot to restart into. | |
1402 | * | |
1403 | * cr.imm contains zero_ext(imm21) | |
1404 | */ | |
1405 | mov r18=cr.iim | |
1406 | ;; | |
1407 | mov r17=cr.iip | |
1408 | shl r18=r18,43 // put sign bit in position (43=64-21) | |
1409 | ;; | |
1410 | ||
1411 | mov r16=cr.ipsr | |
1412 | shr r18=r18,39 // sign extend (39=43-4) | |
1413 | ;; | |
1414 | ||
1415 | add r17=r17,r18 // now add the offset | |
1416 | ;; | |
1417 | mov cr.iip=r17 | |
1418 | dep r16=0,r16,41,2 // clear EI | |
1419 | ;; | |
1420 | ||
1421 | mov cr.ipsr=r16 | |
1422 | ;; | |
1423 | ||
1424 | rfi // and go back | |
1425 | END(speculation_vector) | |
1426 | ||
1427 | .org ia64_ivt+0x5800 | |
1428 | ///////////////////////////////////////////////////////////////////////////////////////// | |
1429 | // 0x5800 Entry 28 (size 16 bundles) Reserved | |
1430 | DBG_FAULT(28) | |
1431 | FAULT(28) | |
1432 | ||
1433 | .org ia64_ivt+0x5900 | |
1434 | ///////////////////////////////////////////////////////////////////////////////////////// | |
1435 | // 0x5900 Entry 29 (size 16 bundles) Debug (16,28,56) | |
1436 | ENTRY(debug_vector) | |
1437 | DBG_FAULT(29) | |
1438 | FAULT(29) | |
1439 | END(debug_vector) | |
1440 | ||
1441 | .org ia64_ivt+0x5a00 | |
1442 | ///////////////////////////////////////////////////////////////////////////////////////// | |
1443 | // 0x5a00 Entry 30 (size 16 bundles) Unaligned Reference (57) | |
1444 | ENTRY(unaligned_access) | |
1445 | DBG_FAULT(30) | |
1da177e4 LT |
1446 | mov r31=pr // prepare to save predicates |
1447 | ;; | |
1448 | br.sptk.many dispatch_unaligned_handler | |
1449 | END(unaligned_access) | |
1450 | ||
1451 | .org ia64_ivt+0x5b00 | |
1452 | ///////////////////////////////////////////////////////////////////////////////////////// | |
1453 | // 0x5b00 Entry 31 (size 16 bundles) Unsupported Data Reference (57) | |
1454 | ENTRY(unsupported_data_reference) | |
1455 | DBG_FAULT(31) | |
1456 | FAULT(31) | |
1457 | END(unsupported_data_reference) | |
1458 | ||
1459 | .org ia64_ivt+0x5c00 | |
1460 | ///////////////////////////////////////////////////////////////////////////////////////// | |
1461 | // 0x5c00 Entry 32 (size 16 bundles) Floating-Point Fault (64) | |
1462 | ENTRY(floating_point_fault) | |
1463 | DBG_FAULT(32) | |
1464 | FAULT(32) | |
1465 | END(floating_point_fault) | |
1466 | ||
1467 | .org ia64_ivt+0x5d00 | |
1468 | ///////////////////////////////////////////////////////////////////////////////////////// | |
1469 | // 0x5d00 Entry 33 (size 16 bundles) Floating Point Trap (66) | |
1470 | ENTRY(floating_point_trap) | |
1471 | DBG_FAULT(33) | |
1472 | FAULT(33) | |
1473 | END(floating_point_trap) | |
1474 | ||
1475 | .org ia64_ivt+0x5e00 | |
1476 | ///////////////////////////////////////////////////////////////////////////////////////// | |
1477 | // 0x5e00 Entry 34 (size 16 bundles) Lower Privilege Transfer Trap (66) | |
1478 | ENTRY(lower_privilege_trap) | |
1479 | DBG_FAULT(34) | |
1480 | FAULT(34) | |
1481 | END(lower_privilege_trap) | |
1482 | ||
1483 | .org ia64_ivt+0x5f00 | |
1484 | ///////////////////////////////////////////////////////////////////////////////////////// | |
1485 | // 0x5f00 Entry 35 (size 16 bundles) Taken Branch Trap (68) | |
1486 | ENTRY(taken_branch_trap) | |
1487 | DBG_FAULT(35) | |
1488 | FAULT(35) | |
1489 | END(taken_branch_trap) | |
1490 | ||
1491 | .org ia64_ivt+0x6000 | |
1492 | ///////////////////////////////////////////////////////////////////////////////////////// | |
1493 | // 0x6000 Entry 36 (size 16 bundles) Single Step Trap (69) | |
1494 | ENTRY(single_step_trap) | |
1495 | DBG_FAULT(36) | |
1496 | FAULT(36) | |
1497 | END(single_step_trap) | |
1498 | ||
1499 | .org ia64_ivt+0x6100 | |
1500 | ///////////////////////////////////////////////////////////////////////////////////////// | |
1501 | // 0x6100 Entry 37 (size 16 bundles) Reserved | |
1502 | DBG_FAULT(37) | |
1503 | FAULT(37) | |
1504 | ||
1505 | .org ia64_ivt+0x6200 | |
1506 | ///////////////////////////////////////////////////////////////////////////////////////// | |
1507 | // 0x6200 Entry 38 (size 16 bundles) Reserved | |
1508 | DBG_FAULT(38) | |
1509 | FAULT(38) | |
1510 | ||
1511 | .org ia64_ivt+0x6300 | |
1512 | ///////////////////////////////////////////////////////////////////////////////////////// | |
1513 | // 0x6300 Entry 39 (size 16 bundles) Reserved | |
1514 | DBG_FAULT(39) | |
1515 | FAULT(39) | |
1516 | ||
1517 | .org ia64_ivt+0x6400 | |
1518 | ///////////////////////////////////////////////////////////////////////////////////////// | |
1519 | // 0x6400 Entry 40 (size 16 bundles) Reserved | |
1520 | DBG_FAULT(40) | |
1521 | FAULT(40) | |
1522 | ||
1523 | .org ia64_ivt+0x6500 | |
1524 | ///////////////////////////////////////////////////////////////////////////////////////// | |
1525 | // 0x6500 Entry 41 (size 16 bundles) Reserved | |
1526 | DBG_FAULT(41) | |
1527 | FAULT(41) | |
1528 | ||
1529 | .org ia64_ivt+0x6600 | |
1530 | ///////////////////////////////////////////////////////////////////////////////////////// | |
1531 | // 0x6600 Entry 42 (size 16 bundles) Reserved | |
1532 | DBG_FAULT(42) | |
1533 | FAULT(42) | |
1534 | ||
1535 | .org ia64_ivt+0x6700 | |
1536 | ///////////////////////////////////////////////////////////////////////////////////////// | |
1537 | // 0x6700 Entry 43 (size 16 bundles) Reserved | |
1538 | DBG_FAULT(43) | |
1539 | FAULT(43) | |
1540 | ||
1541 | .org ia64_ivt+0x6800 | |
1542 | ///////////////////////////////////////////////////////////////////////////////////////// | |
1543 | // 0x6800 Entry 44 (size 16 bundles) Reserved | |
1544 | DBG_FAULT(44) | |
1545 | FAULT(44) | |
1546 | ||
1547 | .org ia64_ivt+0x6900 | |
1548 | ///////////////////////////////////////////////////////////////////////////////////////// | |
1549 | // 0x6900 Entry 45 (size 16 bundles) IA-32 Exeception (17,18,29,41,42,43,44,58,60,61,62,72,73,75,76,77) | |
1550 | ENTRY(ia32_exception) | |
1551 | DBG_FAULT(45) | |
1552 | FAULT(45) | |
1553 | END(ia32_exception) | |
1554 | ||
1555 | .org ia64_ivt+0x6a00 | |
1556 | ///////////////////////////////////////////////////////////////////////////////////////// | |
1557 | // 0x6a00 Entry 46 (size 16 bundles) IA-32 Intercept (30,31,59,70,71) | |
1558 | ENTRY(ia32_intercept) | |
1559 | DBG_FAULT(46) | |
1560 | #ifdef CONFIG_IA32_SUPPORT | |
1561 | mov r31=pr | |
1562 | mov r16=cr.isr | |
1563 | ;; | |
1564 | extr.u r17=r16,16,8 // get ISR.code | |
1565 | mov r18=ar.eflag | |
1566 | mov r19=cr.iim // old eflag value | |
1567 | ;; | |
1568 | cmp.ne p6,p0=2,r17 | |
1569 | (p6) br.cond.spnt 1f // not a system flag fault | |
1570 | xor r16=r18,r19 | |
1571 | ;; | |
1572 | extr.u r17=r16,18,1 // get the eflags.ac bit | |
1573 | ;; | |
1574 | cmp.eq p6,p0=0,r17 | |
1575 | (p6) br.cond.spnt 1f // eflags.ac bit didn't change | |
1576 | ;; | |
1577 | mov pr=r31,-1 // restore predicate registers | |
1578 | rfi | |
1579 | ||
1580 | 1: | |
1581 | #endif // CONFIG_IA32_SUPPORT | |
1582 | FAULT(46) | |
1583 | END(ia32_intercept) | |
1584 | ||
1585 | .org ia64_ivt+0x6b00 | |
1586 | ///////////////////////////////////////////////////////////////////////////////////////// | |
1587 | // 0x6b00 Entry 47 (size 16 bundles) IA-32 Interrupt (74) | |
1588 | ENTRY(ia32_interrupt) | |
1589 | DBG_FAULT(47) | |
1590 | #ifdef CONFIG_IA32_SUPPORT | |
1591 | mov r31=pr | |
1592 | br.sptk.many dispatch_to_ia32_handler | |
1593 | #else | |
1594 | FAULT(47) | |
1595 | #endif | |
1596 | END(ia32_interrupt) | |
1597 | ||
1598 | .org ia64_ivt+0x6c00 | |
1599 | ///////////////////////////////////////////////////////////////////////////////////////// | |
1600 | // 0x6c00 Entry 48 (size 16 bundles) Reserved | |
1601 | DBG_FAULT(48) | |
1602 | FAULT(48) | |
1603 | ||
1604 | .org ia64_ivt+0x6d00 | |
1605 | ///////////////////////////////////////////////////////////////////////////////////////// | |
1606 | // 0x6d00 Entry 49 (size 16 bundles) Reserved | |
1607 | DBG_FAULT(49) | |
1608 | FAULT(49) | |
1609 | ||
1610 | .org ia64_ivt+0x6e00 | |
1611 | ///////////////////////////////////////////////////////////////////////////////////////// | |
1612 | // 0x6e00 Entry 50 (size 16 bundles) Reserved | |
1613 | DBG_FAULT(50) | |
1614 | FAULT(50) | |
1615 | ||
1616 | .org ia64_ivt+0x6f00 | |
1617 | ///////////////////////////////////////////////////////////////////////////////////////// | |
1618 | // 0x6f00 Entry 51 (size 16 bundles) Reserved | |
1619 | DBG_FAULT(51) | |
1620 | FAULT(51) | |
1621 | ||
1622 | .org ia64_ivt+0x7000 | |
1623 | ///////////////////////////////////////////////////////////////////////////////////////// | |
1624 | // 0x7000 Entry 52 (size 16 bundles) Reserved | |
1625 | DBG_FAULT(52) | |
1626 | FAULT(52) | |
1627 | ||
1628 | .org ia64_ivt+0x7100 | |
1629 | ///////////////////////////////////////////////////////////////////////////////////////// | |
1630 | // 0x7100 Entry 53 (size 16 bundles) Reserved | |
1631 | DBG_FAULT(53) | |
1632 | FAULT(53) | |
1633 | ||
1634 | .org ia64_ivt+0x7200 | |
1635 | ///////////////////////////////////////////////////////////////////////////////////////// | |
1636 | // 0x7200 Entry 54 (size 16 bundles) Reserved | |
1637 | DBG_FAULT(54) | |
1638 | FAULT(54) | |
1639 | ||
1640 | .org ia64_ivt+0x7300 | |
1641 | ///////////////////////////////////////////////////////////////////////////////////////// | |
1642 | // 0x7300 Entry 55 (size 16 bundles) Reserved | |
1643 | DBG_FAULT(55) | |
1644 | FAULT(55) | |
1645 | ||
1646 | .org ia64_ivt+0x7400 | |
1647 | ///////////////////////////////////////////////////////////////////////////////////////// | |
1648 | // 0x7400 Entry 56 (size 16 bundles) Reserved | |
1649 | DBG_FAULT(56) | |
1650 | FAULT(56) | |
1651 | ||
1652 | .org ia64_ivt+0x7500 | |
1653 | ///////////////////////////////////////////////////////////////////////////////////////// | |
1654 | // 0x7500 Entry 57 (size 16 bundles) Reserved | |
1655 | DBG_FAULT(57) | |
1656 | FAULT(57) | |
1657 | ||
1658 | .org ia64_ivt+0x7600 | |
1659 | ///////////////////////////////////////////////////////////////////////////////////////// | |
1660 | // 0x7600 Entry 58 (size 16 bundles) Reserved | |
1661 | DBG_FAULT(58) | |
1662 | FAULT(58) | |
1663 | ||
1664 | .org ia64_ivt+0x7700 | |
1665 | ///////////////////////////////////////////////////////////////////////////////////////// | |
1666 | // 0x7700 Entry 59 (size 16 bundles) Reserved | |
1667 | DBG_FAULT(59) | |
1668 | FAULT(59) | |
1669 | ||
1670 | .org ia64_ivt+0x7800 | |
1671 | ///////////////////////////////////////////////////////////////////////////////////////// | |
1672 | // 0x7800 Entry 60 (size 16 bundles) Reserved | |
1673 | DBG_FAULT(60) | |
1674 | FAULT(60) | |
1675 | ||
1676 | .org ia64_ivt+0x7900 | |
1677 | ///////////////////////////////////////////////////////////////////////////////////////// | |
1678 | // 0x7900 Entry 61 (size 16 bundles) Reserved | |
1679 | DBG_FAULT(61) | |
1680 | FAULT(61) | |
1681 | ||
1682 | .org ia64_ivt+0x7a00 | |
1683 | ///////////////////////////////////////////////////////////////////////////////////////// | |
1684 | // 0x7a00 Entry 62 (size 16 bundles) Reserved | |
1685 | DBG_FAULT(62) | |
1686 | FAULT(62) | |
1687 | ||
1688 | .org ia64_ivt+0x7b00 | |
1689 | ///////////////////////////////////////////////////////////////////////////////////////// | |
1690 | // 0x7b00 Entry 63 (size 16 bundles) Reserved | |
1691 | DBG_FAULT(63) | |
1692 | FAULT(63) | |
1693 | ||
1694 | .org ia64_ivt+0x7c00 | |
1695 | ///////////////////////////////////////////////////////////////////////////////////////// | |
1696 | // 0x7c00 Entry 64 (size 16 bundles) Reserved | |
1697 | DBG_FAULT(64) | |
1698 | FAULT(64) | |
1699 | ||
1700 | .org ia64_ivt+0x7d00 | |
1701 | ///////////////////////////////////////////////////////////////////////////////////////// | |
1702 | // 0x7d00 Entry 65 (size 16 bundles) Reserved | |
1703 | DBG_FAULT(65) | |
1704 | FAULT(65) | |
1705 | ||
1706 | .org ia64_ivt+0x7e00 | |
1707 | ///////////////////////////////////////////////////////////////////////////////////////// | |
1708 | // 0x7e00 Entry 66 (size 16 bundles) Reserved | |
1709 | DBG_FAULT(66) | |
1710 | FAULT(66) | |
1711 | ||
1712 | .org ia64_ivt+0x7f00 | |
1713 | ///////////////////////////////////////////////////////////////////////////////////////// | |
1714 | // 0x7f00 Entry 67 (size 16 bundles) Reserved | |
1715 | DBG_FAULT(67) | |
1716 | FAULT(67) | |
1717 | ||
1718 | #ifdef CONFIG_IA32_SUPPORT | |
1719 | ||
1720 | /* | |
1721 | * There is no particular reason for this code to be here, other than that | |
1722 | * there happens to be space here that would go unused otherwise. If this | |
1723 | * fault ever gets "unreserved", simply moved the following code to a more | |
1724 | * suitable spot... | |
1725 | */ | |
1726 | ||
1727 | // IA32 interrupt entry point | |
1728 | ||
1729 | ENTRY(dispatch_to_ia32_handler) | |
1730 | SAVE_MIN | |
1731 | ;; | |
1732 | mov r14=cr.isr | |
1733 | ssm psr.ic | PSR_DEFAULT_BITS | |
1734 | ;; | |
1735 | srlz.i // guarantee that interruption collection is on | |
1736 | ;; | |
1737 | (p15) ssm psr.i | |
1738 | adds r3=8,r2 // Base pointer for SAVE_REST | |
1739 | ;; | |
1740 | SAVE_REST | |
1741 | ;; | |
1742 | mov r15=0x80 | |
1743 | shr r14=r14,16 // Get interrupt number | |
1744 | ;; | |
1745 | cmp.ne p6,p0=r14,r15 | |
1746 | (p6) br.call.dpnt.many b6=non_ia32_syscall | |
1747 | ||
1748 | adds r14=IA64_PT_REGS_R8_OFFSET + 16,sp // 16 byte hole per SW conventions | |
1749 | adds r15=IA64_PT_REGS_R1_OFFSET + 16,sp | |
1750 | ;; | |
1751 | cmp.eq pSys,pNonSys=r0,r0 // set pSys=1, pNonSys=0 | |
1752 | ld8 r8=[r14] // get r8 | |
1753 | ;; | |
1754 | st8 [r15]=r8 // save original EAX in r1 (IA32 procs don't use the GP) | |
1755 | ;; | |
1756 | alloc r15=ar.pfs,0,0,6,0 // must first in an insn group | |
1757 | ;; | |
1758 | ld4 r8=[r14],8 // r8 == eax (syscall number) | |
1759 | mov r15=IA32_NR_syscalls | |
1760 | ;; | |
1761 | cmp.ltu.unc p6,p7=r8,r15 | |
1762 | ld4 out1=[r14],8 // r9 == ecx | |
1763 | ;; | |
1764 | ld4 out2=[r14],8 // r10 == edx | |
1765 | ;; | |
1766 | ld4 out0=[r14] // r11 == ebx | |
1767 | adds r14=(IA64_PT_REGS_R13_OFFSET) + 16,sp | |
1768 | ;; | |
1769 | ld4 out5=[r14],PT(R14)-PT(R13) // r13 == ebp | |
1770 | ;; | |
1771 | ld4 out3=[r14],PT(R15)-PT(R14) // r14 == esi | |
1772 | adds r2=TI_FLAGS+IA64_TASK_SIZE,r13 | |
1773 | ;; | |
1774 | ld4 out4=[r14] // r15 == edi | |
1775 | movl r16=ia32_syscall_table | |
1776 | ;; | |
1777 | (p6) shladd r16=r8,3,r16 // force ni_syscall if not valid syscall number | |
1778 | ld4 r2=[r2] // r2 = current_thread_info()->flags | |
1779 | ;; | |
1780 | ld8 r16=[r16] | |
1781 | and r2=_TIF_SYSCALL_TRACEAUDIT,r2 // mask trace or audit | |
1782 | ;; | |
1783 | mov b6=r16 | |
1784 | movl r15=ia32_ret_from_syscall | |
1785 | cmp.eq p8,p0=r2,r0 | |
1786 | ;; | |
1787 | mov rp=r15 | |
1788 | (p8) br.call.sptk.many b6=b6 | |
1789 | br.cond.sptk ia32_trace_syscall | |
1790 | ||
1791 | non_ia32_syscall: | |
1792 | alloc r15=ar.pfs,0,0,2,0 | |
1793 | mov out0=r14 // interrupt # | |
1794 | add out1=16,sp // pointer to pt_regs | |
1795 | ;; // avoid WAW on CFM | |
1796 | br.call.sptk.many rp=ia32_bad_interrupt | |
1797 | .ret1: movl r15=ia64_leave_kernel | |
1798 | ;; | |
1799 | mov rp=r15 | |
1800 | br.ret.sptk.many rp | |
1801 | END(dispatch_to_ia32_handler) | |
1802 | ||
1803 | #endif /* CONFIG_IA32_SUPPORT */ |