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Commit | Line | Data |
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b2441318 | 1 | // SPDX-License-Identifier: GPL-2.0 |
fd58e55f MM |
2 | /* |
3 | * MSI hooks for standard x86 apic | |
4 | */ | |
5 | ||
6 | #include <linux/pci.h> | |
7 | #include <linux/irq.h> | |
3b7d1921 | 8 | #include <linux/msi.h> |
62fdd767 | 9 | #include <linux/dmar.h> |
a4cffb64 | 10 | #include <asm/smp.h> |
2fa8937f | 11 | #include <asm/msidef.h> |
fd58e55f | 12 | |
3b7d1921 | 13 | static struct irq_chip ia64_msi_chip; |
fd58e55f | 14 | |
3b7d1921 | 15 | #ifdef CONFIG_SMP |
f1f701e9 TG |
16 | static int ia64_set_msi_irq_affinity(struct irq_data *idata, |
17 | const cpumask_t *cpu_mask, bool force) | |
fd58e55f | 18 | { |
3b7d1921 | 19 | struct msi_msg msg; |
cd378f18 | 20 | u32 addr, data; |
785aebd0 | 21 | int cpu = cpumask_first_and(cpu_mask, cpu_online_mask); |
f1f701e9 | 22 | unsigned int irq = idata->irq; |
3b7d1921 | 23 | |
a6cd6322 | 24 | if (irq_prepare_move(irq, cpu)) |
d5dedd45 | 25 | return -1; |
4994be1b | 26 | |
507a883e | 27 | __get_cached_msi_msg(irq_data_get_msi_desc(idata), &msg); |
fd58e55f | 28 | |
3b7d1921 | 29 | addr = msg.address_lo; |
2fa8937f XZ |
30 | addr &= MSI_ADDR_DEST_ID_MASK; |
31 | addr |= MSI_ADDR_DEST_ID_CPU(cpu_physical_id(cpu)); | |
3b7d1921 | 32 | msg.address_lo = addr; |
fd58e55f | 33 | |
cd378f18 YI |
34 | data = msg.data; |
35 | data &= MSI_DATA_VECTOR_MASK; | |
36 | data |= MSI_DATA_VECTOR(irq_to_vector(irq)); | |
37 | msg.data = data; | |
38 | ||
83a18912 | 39 | pci_write_msi_msg(irq, &msg); |
c42574ed | 40 | cpumask_copy(irq_data_get_affinity_mask(idata), cpumask_of(cpu)); |
d5dedd45 YL |
41 | |
42 | return 0; | |
fd58e55f | 43 | } |
3b7d1921 | 44 | #endif /* CONFIG_SMP */ |
fd58e55f | 45 | |
f7feaca7 | 46 | int ia64_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc) |
fd58e55f | 47 | { |
3b7d1921 | 48 | struct msi_msg msg; |
fd58e55f | 49 | unsigned long dest_phys_id; |
8a3a0ee7 | 50 | int irq, vector; |
fd58e55f | 51 | |
f7feaca7 EB |
52 | irq = create_irq(); |
53 | if (irq < 0) | |
54 | return irq; | |
55 | ||
53c909c9 | 56 | irq_set_msi_desc(irq, desc); |
51f7bd85 RR |
57 | dest_phys_id = cpu_physical_id(cpumask_any_and(&(irq_to_domain(irq)), |
58 | cpu_online_mask)); | |
9438a121 | 59 | vector = irq_to_vector(irq); |
fd58e55f | 60 | |
3b7d1921 EB |
61 | msg.address_hi = 0; |
62 | msg.address_lo = | |
38bc0361 | 63 | MSI_ADDR_HEADER | |
2fa8937f | 64 | MSI_ADDR_DEST_MODE_PHYS | |
38bc0361 | 65 | MSI_ADDR_REDIRECTION_CPU | |
2fa8937f | 66 | MSI_ADDR_DEST_ID_CPU(dest_phys_id); |
fd58e55f | 67 | |
3b7d1921 | 68 | msg.data = |
38bc0361 | 69 | MSI_DATA_TRIGGER_EDGE | |
fd58e55f MM |
70 | MSI_DATA_LEVEL_ASSERT | |
71 | MSI_DATA_DELIVERY_FIXED | | |
72 | MSI_DATA_VECTOR(vector); | |
73 | ||
83a18912 | 74 | pci_write_msi_msg(irq, &msg); |
53c909c9 | 75 | irq_set_chip_and_handler(irq, &ia64_msi_chip, handle_edge_irq); |
3b7d1921 | 76 | |
3aff0373 | 77 | return 0; |
fd58e55f MM |
78 | } |
79 | ||
3b7d1921 | 80 | void ia64_teardown_msi_irq(unsigned int irq) |
fd58e55f | 81 | { |
f7feaca7 | 82 | destroy_irq(irq); |
fd58e55f MM |
83 | } |
84 | ||
f1f701e9 | 85 | static void ia64_ack_msi_irq(struct irq_data *data) |
3b7d1921 | 86 | { |
f1f701e9 | 87 | irq_complete_move(data->irq); |
97499b2e | 88 | irq_move_irq(data); |
3b7d1921 EB |
89 | ia64_eoi(); |
90 | } | |
91 | ||
f1f701e9 | 92 | static int ia64_msi_retrigger_irq(struct irq_data *data) |
3b7d1921 | 93 | { |
f1f701e9 | 94 | unsigned int vector = irq_to_vector(data->irq); |
3b7d1921 EB |
95 | ia64_resend_irq(vector); |
96 | ||
97 | return 1; | |
98 | } | |
99 | ||
fd58e55f | 100 | /* |
3b7d1921 | 101 | * Generic ops used on most IA64 platforms. |
fd58e55f | 102 | */ |
3b7d1921 | 103 | static struct irq_chip ia64_msi_chip = { |
f1f701e9 | 104 | .name = "PCI-MSI", |
280510f1 TG |
105 | .irq_mask = pci_msi_mask_irq, |
106 | .irq_unmask = pci_msi_unmask_irq, | |
f1f701e9 | 107 | .irq_ack = ia64_ack_msi_irq, |
3b7d1921 | 108 | #ifdef CONFIG_SMP |
f1f701e9 | 109 | .irq_set_affinity = ia64_set_msi_irq_affinity, |
3b7d1921 | 110 | #endif |
f1f701e9 | 111 | .irq_retrigger = ia64_msi_retrigger_irq, |
fd58e55f | 112 | }; |
3b7d1921 EB |
113 | |
114 | ||
f7feaca7 | 115 | int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc) |
3b7d1921 EB |
116 | { |
117 | if (platform_setup_msi_irq) | |
f7feaca7 | 118 | return platform_setup_msi_irq(pdev, desc); |
3b7d1921 | 119 | |
f7feaca7 | 120 | return ia64_setup_msi_irq(pdev, desc); |
3b7d1921 EB |
121 | } |
122 | ||
123 | void arch_teardown_msi_irq(unsigned int irq) | |
124 | { | |
125 | if (platform_teardown_msi_irq) | |
126 | return platform_teardown_msi_irq(irq); | |
127 | ||
128 | return ia64_teardown_msi_irq(irq); | |
129 | } | |
62fdd767 | 130 | |
d3f13810 | 131 | #ifdef CONFIG_INTEL_IOMMU |
62fdd767 | 132 | #ifdef CONFIG_SMP |
f1f701e9 TG |
133 | static int dmar_msi_set_affinity(struct irq_data *data, |
134 | const struct cpumask *mask, bool force) | |
62fdd767 | 135 | { |
f1f701e9 | 136 | unsigned int irq = data->irq; |
62fdd767 FY |
137 | struct irq_cfg *cfg = irq_cfg + irq; |
138 | struct msi_msg msg; | |
785aebd0 | 139 | int cpu = cpumask_first_and(mask, cpu_online_mask); |
62fdd767 FY |
140 | |
141 | if (irq_prepare_move(irq, cpu)) | |
d5dedd45 | 142 | return -1; |
62fdd767 FY |
143 | |
144 | dmar_msi_read(irq, &msg); | |
145 | ||
146 | msg.data &= ~MSI_DATA_VECTOR_MASK; | |
147 | msg.data |= MSI_DATA_VECTOR(cfg->vector); | |
2fa8937f XZ |
148 | msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; |
149 | msg.address_lo |= MSI_ADDR_DEST_ID_CPU(cpu_physical_id(cpu)); | |
62fdd767 FY |
150 | |
151 | dmar_msi_write(irq, &msg); | |
c42574ed | 152 | cpumask_copy(irq_data_get_affinity_mask(data), mask); |
d5dedd45 YL |
153 | |
154 | return 0; | |
62fdd767 FY |
155 | } |
156 | #endif /* CONFIG_SMP */ | |
157 | ||
9542b21e | 158 | static struct irq_chip dmar_msi_type = { |
62fdd767 | 159 | .name = "DMAR_MSI", |
5c2837fb TG |
160 | .irq_unmask = dmar_msi_unmask, |
161 | .irq_mask = dmar_msi_mask, | |
f1f701e9 | 162 | .irq_ack = ia64_ack_msi_irq, |
62fdd767 | 163 | #ifdef CONFIG_SMP |
f1f701e9 | 164 | .irq_set_affinity = dmar_msi_set_affinity, |
62fdd767 | 165 | #endif |
f1f701e9 | 166 | .irq_retrigger = ia64_msi_retrigger_irq, |
62fdd767 FY |
167 | }; |
168 | ||
34742db8 | 169 | static void |
62fdd767 FY |
170 | msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg) |
171 | { | |
172 | struct irq_cfg *cfg = irq_cfg + irq; | |
173 | unsigned dest; | |
62fdd767 | 174 | |
51f7bd85 RR |
175 | dest = cpu_physical_id(cpumask_first_and(&(irq_to_domain(irq)), |
176 | cpu_online_mask)); | |
62fdd767 FY |
177 | |
178 | msg->address_hi = 0; | |
179 | msg->address_lo = | |
180 | MSI_ADDR_HEADER | | |
2fa8937f | 181 | MSI_ADDR_DEST_MODE_PHYS | |
62fdd767 | 182 | MSI_ADDR_REDIRECTION_CPU | |
2fa8937f | 183 | MSI_ADDR_DEST_ID_CPU(dest); |
62fdd767 FY |
184 | |
185 | msg->data = | |
186 | MSI_DATA_TRIGGER_EDGE | | |
187 | MSI_DATA_LEVEL_ASSERT | | |
188 | MSI_DATA_DELIVERY_FIXED | | |
189 | MSI_DATA_VECTOR(cfg->vector); | |
62fdd767 FY |
190 | } |
191 | ||
34742db8 | 192 | int dmar_alloc_hwirq(int id, int node, void *arg) |
62fdd767 | 193 | { |
34742db8 | 194 | int irq; |
62fdd767 FY |
195 | struct msi_msg msg; |
196 | ||
34742db8 JL |
197 | irq = create_irq(); |
198 | if (irq > 0) { | |
199 | irq_set_handler_data(irq, arg); | |
200 | irq_set_chip_and_handler_name(irq, &dmar_msi_type, | |
201 | handle_edge_irq, "edge"); | |
202 | msi_compose_msg(NULL, irq, &msg); | |
203 | dmar_msi_write(irq, &msg); | |
204 | } | |
205 | ||
206 | return irq; | |
207 | } | |
208 | ||
209 | void dmar_free_hwirq(int irq) | |
210 | { | |
211 | irq_set_handler_data(irq, NULL); | |
212 | destroy_irq(irq); | |
62fdd767 | 213 | } |
d3f13810 | 214 | #endif /* CONFIG_INTEL_IOMMU */ |
62fdd767 | 215 |