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Commit | Line | Data |
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62fdd767 FY |
1 | /* |
2 | * Dynamic DMA mapping support. | |
3 | */ | |
4 | ||
5 | #include <linux/types.h> | |
6 | #include <linux/mm.h> | |
7 | #include <linux/string.h> | |
8 | #include <linux/pci.h> | |
9 | #include <linux/module.h> | |
10 | #include <linux/dmar.h> | |
11 | #include <asm/iommu.h> | |
12 | #include <asm/machvec.h> | |
13 | #include <linux/dma-mapping.h> | |
14 | ||
62fdd767 FY |
15 | #include <asm/system.h> |
16 | ||
17 | #ifdef CONFIG_DMAR | |
18 | ||
19 | #include <linux/kernel.h> | |
62fdd767 FY |
20 | |
21 | #include <asm/page.h> | |
62fdd767 FY |
22 | |
23 | dma_addr_t bad_dma_address __read_mostly; | |
24 | EXPORT_SYMBOL(bad_dma_address); | |
25 | ||
26 | static int iommu_sac_force __read_mostly; | |
27 | ||
28 | int no_iommu __read_mostly; | |
29 | #ifdef CONFIG_IOMMU_DEBUG | |
30 | int force_iommu __read_mostly = 1; | |
31 | #else | |
32 | int force_iommu __read_mostly; | |
33 | #endif | |
34 | ||
aed5d5f4 FY |
35 | int iommu_pass_through; |
36 | ||
62fdd767 FY |
37 | /* Dummy device used for NULL arguments (normally ISA). Better would |
38 | be probably a smaller DMA mask, but this is bug-to-bug compatible | |
39 | to i386. */ | |
40 | struct device fallback_dev = { | |
48ef2bb4 | 41 | .init_name = "fallback device", |
284901a9 | 42 | .coherent_dma_mask = DMA_BIT_MASK(32), |
62fdd767 FY |
43 | .dma_mask = &fallback_dev.coherent_dma_mask, |
44 | }; | |
45 | ||
160c1d8e | 46 | extern struct dma_map_ops intel_dma_ops; |
62fdd767 FY |
47 | |
48 | static int __init pci_iommu_init(void) | |
49 | { | |
50 | if (iommu_detected) | |
51 | intel_iommu_init(); | |
52 | ||
53 | return 0; | |
54 | } | |
55 | ||
56 | /* Must execute after PCI subsystem */ | |
57 | fs_initcall(pci_iommu_init); | |
58 | ||
59 | void pci_iommu_shutdown(void) | |
60 | { | |
61 | return; | |
62 | } | |
63 | ||
64 | void __init | |
65 | iommu_dma_init(void) | |
66 | { | |
67 | return; | |
68 | } | |
69 | ||
62fdd767 FY |
70 | int iommu_dma_supported(struct device *dev, u64 mask) |
71 | { | |
62fdd767 FY |
72 | /* Copied from i386. Doesn't make much sense, because it will |
73 | only work for pci_alloc_coherent. | |
74 | The caller just has to use GFP_DMA in this case. */ | |
2f4f27d4 | 75 | if (mask < DMA_BIT_MASK(24)) |
62fdd767 FY |
76 | return 0; |
77 | ||
78 | /* Tell the device to use SAC when IOMMU force is on. This | |
79 | allows the driver to use cheaper accesses in some cases. | |
80 | ||
81 | Problem with this is that if we overflow the IOMMU area and | |
82 | return DAC as fallback address the device may not handle it | |
83 | correctly. | |
84 | ||
85 | As a special case some controllers have a 39bit address | |
86 | mode that is as efficient as 32bit (aic79xx). Don't force | |
87 | SAC for these. Assume all masks <= 40 bits are of this | |
88 | type. Normally this doesn't make any difference, but gives | |
89 | more gentle handling of IOMMU overflow. */ | |
50cf156a | 90 | if (iommu_sac_force && (mask >= DMA_BIT_MASK(40))) { |
e088a4ad | 91 | dev_info(dev, "Force SAC with mask %llx\n", mask); |
62fdd767 FY |
92 | return 0; |
93 | } | |
94 | ||
95 | return 1; | |
96 | } | |
97 | EXPORT_SYMBOL(iommu_dma_supported); | |
98 | ||
160c1d8e FT |
99 | void __init pci_iommu_alloc(void) |
100 | { | |
101 | dma_ops = &intel_dma_ops; | |
102 | ||
103 | dma_ops->sync_single_for_cpu = machvec_dma_sync_single; | |
104 | dma_ops->sync_sg_for_cpu = machvec_dma_sync_sg; | |
105 | dma_ops->sync_single_for_device = machvec_dma_sync_single; | |
106 | dma_ops->sync_sg_for_device = machvec_dma_sync_sg; | |
107 | dma_ops->dma_supported = iommu_dma_supported; | |
160c1d8e FT |
108 | |
109 | /* | |
110 | * The order of these functions is important for | |
111 | * fall-back/fail-over reasons | |
112 | */ | |
113 | detect_intel_iommu(); | |
114 | ||
115 | #ifdef CONFIG_SWIOTLB | |
116 | pci_swiotlb_init(); | |
117 | #endif | |
118 | } | |
119 | ||
62fdd767 | 120 | #endif |