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1da177e4 LT |
1 | /* |
2 | * Architecture-specific setup. | |
3 | * | |
4 | * Copyright (C) 1998-2001, 2003-2004 Hewlett-Packard Co | |
5 | * David Mosberger-Tang <davidm@hpl.hp.com> | |
6 | * Stephane Eranian <eranian@hpl.hp.com> | |
e927ecb0 SS |
7 | * Copyright (C) 2000, 2004 Intel Corp |
8 | * Rohit Seth <rohit.seth@intel.com> | |
9 | * Suresh Siddha <suresh.b.siddha@intel.com> | |
10 | * Gordon Jin <gordon.jin@intel.com> | |
1da177e4 LT |
11 | * Copyright (C) 1999 VA Linux Systems |
12 | * Copyright (C) 1999 Walt Drummond <drummond@valinux.com> | |
13 | * | |
e927ecb0 SS |
14 | * 12/26/04 S.Siddha, G.Jin, R.Seth |
15 | * Add multi-threading and multi-core detection | |
1da177e4 LT |
16 | * 11/12/01 D.Mosberger Convert get_cpuinfo() to seq_file based show_cpuinfo(). |
17 | * 04/04/00 D.Mosberger renamed cpu_initialized to cpu_online_map | |
18 | * 03/31/00 R.Seth cpu_initialized and current->processor fixes | |
19 | * 02/04/00 D.Mosberger some more get_cpuinfo fixes... | |
20 | * 02/01/00 R.Seth fixed get_cpuinfo for SMP | |
21 | * 01/07/99 S.Eranian added the support for command line argument | |
22 | * 06/24/99 W.Drummond added boot_cpu_data. | |
08357f82 | 23 | * 05/28/05 Z. Menyhart Dynamic stride size for "flush_icache_range()" |
1da177e4 | 24 | */ |
1da177e4 LT |
25 | #include <linux/module.h> |
26 | #include <linux/init.h> | |
27 | ||
28 | #include <linux/acpi.h> | |
29 | #include <linux/bootmem.h> | |
30 | #include <linux/console.h> | |
31 | #include <linux/delay.h> | |
32 | #include <linux/kernel.h> | |
33 | #include <linux/reboot.h> | |
34 | #include <linux/sched.h> | |
35 | #include <linux/seq_file.h> | |
36 | #include <linux/string.h> | |
37 | #include <linux/threads.h> | |
894673ee | 38 | #include <linux/screen_info.h> |
3ed3bce8 | 39 | #include <linux/dmi.h> |
1da177e4 LT |
40 | #include <linux/serial.h> |
41 | #include <linux/serial_core.h> | |
42 | #include <linux/efi.h> | |
43 | #include <linux/initrd.h> | |
6c4fa560 | 44 | #include <linux/pm.h> |
95235ca2 | 45 | #include <linux/cpufreq.h> |
a7956113 ZN |
46 | #include <linux/kexec.h> |
47 | #include <linux/crash_dump.h> | |
1da177e4 LT |
48 | |
49 | #include <asm/ia32.h> | |
50 | #include <asm/machvec.h> | |
51 | #include <asm/mca.h> | |
52 | #include <asm/meminit.h> | |
53 | #include <asm/page.h> | |
54 | #include <asm/patch.h> | |
55 | #include <asm/pgtable.h> | |
56 | #include <asm/processor.h> | |
57 | #include <asm/sal.h> | |
58 | #include <asm/sections.h> | |
1da177e4 LT |
59 | #include <asm/setup.h> |
60 | #include <asm/smp.h> | |
61 | #include <asm/system.h> | |
2046b94e | 62 | #include <asm/tlbflush.h> |
1da177e4 | 63 | #include <asm/unistd.h> |
8b713c67 | 64 | #include <asm/hpsim.h> |
1da177e4 LT |
65 | |
66 | #if defined(CONFIG_SMP) && (IA64_CPU_SIZE > PAGE_SIZE) | |
67 | # error "struct cpuinfo_ia64 too big!" | |
68 | #endif | |
69 | ||
70 | #ifdef CONFIG_SMP | |
71 | unsigned long __per_cpu_offset[NR_CPUS]; | |
72 | EXPORT_SYMBOL(__per_cpu_offset); | |
73 | #endif | |
74 | ||
75 | DEFINE_PER_CPU(struct cpuinfo_ia64, cpu_info); | |
76 | DEFINE_PER_CPU(unsigned long, local_per_cpu_offset); | |
1da177e4 LT |
77 | unsigned long ia64_cycles_per_usec; |
78 | struct ia64_boot_param *ia64_boot_param; | |
79 | struct screen_info screen_info; | |
66b7f8a3 MM |
80 | unsigned long vga_console_iobase; |
81 | unsigned long vga_console_membase; | |
1da177e4 | 82 | |
be379124 KA |
83 | static struct resource data_resource = { |
84 | .name = "Kernel data", | |
85 | .flags = IORESOURCE_BUSY | IORESOURCE_MEM | |
86 | }; | |
87 | ||
88 | static struct resource code_resource = { | |
89 | .name = "Kernel code", | |
90 | .flags = IORESOURCE_BUSY | IORESOURCE_MEM | |
91 | }; | |
00bf4098 BW |
92 | |
93 | static struct resource bss_resource = { | |
94 | .name = "Kernel bss", | |
95 | .flags = IORESOURCE_BUSY | IORESOURCE_MEM | |
96 | }; | |
be379124 | 97 | |
1da177e4 | 98 | unsigned long ia64_max_cacheline_size; |
e1531b42 JL |
99 | |
100 | int dma_get_cache_alignment(void) | |
101 | { | |
102 | return ia64_max_cacheline_size; | |
103 | } | |
104 | EXPORT_SYMBOL(dma_get_cache_alignment); | |
105 | ||
1da177e4 LT |
106 | unsigned long ia64_iobase; /* virtual address for I/O accesses */ |
107 | EXPORT_SYMBOL(ia64_iobase); | |
108 | struct io_space io_space[MAX_IO_SPACES]; | |
109 | EXPORT_SYMBOL(io_space); | |
110 | unsigned int num_io_spaces; | |
111 | ||
08357f82 ZM |
112 | /* |
113 | * "flush_icache_range()" needs to know what processor dependent stride size to use | |
114 | * when it makes i-cache(s) coherent with d-caches. | |
115 | */ | |
116 | #define I_CACHE_STRIDE_SHIFT 5 /* Safest way to go: 32 bytes by 32 bytes */ | |
117 | unsigned long ia64_i_cache_stride_shift = ~0; | |
118 | ||
1da177e4 LT |
119 | /* |
120 | * The merge_mask variable needs to be set to (max(iommu_page_size(iommu)) - 1). This | |
121 | * mask specifies a mask of address bits that must be 0 in order for two buffers to be | |
122 | * mergeable by the I/O MMU (i.e., the end address of the first buffer and the start | |
123 | * address of the second buffer must be aligned to (merge_mask+1) in order to be | |
124 | * mergeable). By default, we assume there is no I/O MMU which can merge physically | |
125 | * discontiguous buffers, so we set the merge_mask to ~0UL, which corresponds to a iommu | |
126 | * page-size of 2^64. | |
127 | */ | |
128 | unsigned long ia64_max_iommu_merge_mask = ~0UL; | |
129 | EXPORT_SYMBOL(ia64_max_iommu_merge_mask); | |
130 | ||
131 | /* | |
132 | * We use a special marker for the end of memory and it uses the extra (+1) slot | |
133 | */ | |
dae28066 KC |
134 | struct rsvd_region rsvd_region[IA64_MAX_RSVD_REGIONS + 1] __initdata; |
135 | int num_rsvd_regions __initdata; | |
1da177e4 LT |
136 | |
137 | ||
138 | /* | |
139 | * Filter incoming memory segments based on the primitive map created from the boot | |
140 | * parameters. Segments contained in the map are removed from the memory ranges. A | |
141 | * caller-specified function is called with the memory ranges that remain after filtering. | |
142 | * This routine does not assume the incoming segments are sorted. | |
143 | */ | |
dae28066 | 144 | int __init |
1da177e4 LT |
145 | filter_rsvd_memory (unsigned long start, unsigned long end, void *arg) |
146 | { | |
147 | unsigned long range_start, range_end, prev_start; | |
148 | void (*func)(unsigned long, unsigned long, int); | |
149 | int i; | |
150 | ||
151 | #if IGNORE_PFN0 | |
152 | if (start == PAGE_OFFSET) { | |
153 | printk(KERN_WARNING "warning: skipping physical page 0\n"); | |
154 | start += PAGE_SIZE; | |
155 | if (start >= end) return 0; | |
156 | } | |
157 | #endif | |
158 | /* | |
159 | * lowest possible address(walker uses virtual) | |
160 | */ | |
161 | prev_start = PAGE_OFFSET; | |
162 | func = arg; | |
163 | ||
164 | for (i = 0; i < num_rsvd_regions; ++i) { | |
165 | range_start = max(start, prev_start); | |
166 | range_end = min(end, rsvd_region[i].start); | |
167 | ||
168 | if (range_start < range_end) | |
169 | call_pernode_memory(__pa(range_start), range_end - range_start, func); | |
170 | ||
171 | /* nothing more available in this segment */ | |
172 | if (range_end == end) return 0; | |
173 | ||
174 | prev_start = rsvd_region[i].end; | |
175 | } | |
176 | /* end of memory marker allows full processing inside loop body */ | |
177 | return 0; | |
178 | } | |
179 | ||
98075d24 ZM |
180 | /* |
181 | * Similar to "filter_rsvd_memory()", but the reserved memory ranges | |
182 | * are not filtered out. | |
183 | */ | |
184 | int __init | |
185 | filter_memory(unsigned long start, unsigned long end, void *arg) | |
186 | { | |
187 | void (*func)(unsigned long, unsigned long, int); | |
188 | ||
189 | #if IGNORE_PFN0 | |
190 | if (start == PAGE_OFFSET) { | |
191 | printk(KERN_WARNING "warning: skipping physical page 0\n"); | |
192 | start += PAGE_SIZE; | |
193 | if (start >= end) | |
194 | return 0; | |
195 | } | |
196 | #endif | |
197 | func = arg; | |
198 | if (start < end) | |
199 | call_pernode_memory(__pa(start), end - start, func); | |
200 | return 0; | |
201 | } | |
202 | ||
dae28066 | 203 | static void __init |
1da177e4 LT |
204 | sort_regions (struct rsvd_region *rsvd_region, int max) |
205 | { | |
206 | int j; | |
207 | ||
208 | /* simple bubble sorting */ | |
209 | while (max--) { | |
210 | for (j = 0; j < max; ++j) { | |
211 | if (rsvd_region[j].start > rsvd_region[j+1].start) { | |
212 | struct rsvd_region tmp; | |
213 | tmp = rsvd_region[j]; | |
214 | rsvd_region[j] = rsvd_region[j + 1]; | |
215 | rsvd_region[j + 1] = tmp; | |
216 | } | |
217 | } | |
218 | } | |
219 | } | |
220 | ||
be379124 KA |
221 | /* |
222 | * Request address space for all standard resources | |
223 | */ | |
224 | static int __init register_memory(void) | |
225 | { | |
226 | code_resource.start = ia64_tpa(_text); | |
227 | code_resource.end = ia64_tpa(_etext) - 1; | |
228 | data_resource.start = ia64_tpa(_etext); | |
00bf4098 | 229 | data_resource.end = ia64_tpa(_edata) - 1; |
b898a424 | 230 | bss_resource.start = ia64_tpa(__bss_start); |
00bf4098 BW |
231 | bss_resource.end = ia64_tpa(_end) - 1; |
232 | efi_initialize_iomem_resources(&code_resource, &data_resource, | |
233 | &bss_resource); | |
be379124 KA |
234 | |
235 | return 0; | |
236 | } | |
237 | ||
238 | __initcall(register_memory); | |
239 | ||
cb380853 BW |
240 | |
241 | #ifdef CONFIG_KEXEC | |
8a3360f0 BW |
242 | |
243 | /* | |
244 | * This function checks if the reserved crashkernel is allowed on the specific | |
245 | * IA64 machine flavour. Machines without an IO TLB use swiotlb and require | |
246 | * some memory below 4 GB (i.e. in 32 bit area), see the implementation of | |
247 | * lib/swiotlb.c. The hpzx1 architecture has an IO TLB but cannot use that | |
248 | * in kdump case. See the comment in sba_init() in sba_iommu.c. | |
249 | * | |
250 | * So, the only machvec that really supports loading the kdump kernel | |
251 | * over 4 GB is "sn2". | |
252 | */ | |
253 | static int __init check_crashkernel_memory(unsigned long pbase, size_t size) | |
254 | { | |
255 | if (ia64_platform_is("sn2") || ia64_platform_is("uv")) | |
256 | return 1; | |
257 | else | |
258 | return pbase < (1UL << 32); | |
259 | } | |
260 | ||
cb380853 BW |
261 | static void __init setup_crashkernel(unsigned long total, int *n) |
262 | { | |
263 | unsigned long long base = 0, size = 0; | |
264 | int ret; | |
265 | ||
266 | ret = parse_crashkernel(boot_command_line, total, | |
267 | &size, &base); | |
268 | if (ret == 0 && size > 0) { | |
269 | if (!base) { | |
270 | sort_regions(rsvd_region, *n); | |
271 | base = kdump_find_rsvd_region(size, | |
272 | rsvd_region, *n); | |
273 | } | |
8a3360f0 BW |
274 | |
275 | if (!check_crashkernel_memory(base, size)) { | |
276 | pr_warning("crashkernel: There would be kdump memory " | |
277 | "at %ld GB but this is unusable because it " | |
278 | "must\nbe below 4 GB. Change the memory " | |
279 | "configuration of the machine.\n", | |
280 | (unsigned long)(base >> 30)); | |
281 | return; | |
282 | } | |
283 | ||
cb380853 BW |
284 | if (base != ~0UL) { |
285 | printk(KERN_INFO "Reserving %ldMB of memory at %ldMB " | |
286 | "for crashkernel (System RAM: %ldMB)\n", | |
287 | (unsigned long)(size >> 20), | |
288 | (unsigned long)(base >> 20), | |
289 | (unsigned long)(total >> 20)); | |
290 | rsvd_region[*n].start = | |
291 | (unsigned long)__va(base); | |
292 | rsvd_region[*n].end = | |
293 | (unsigned long)__va(base + size); | |
294 | (*n)++; | |
295 | crashk_res.start = base; | |
296 | crashk_res.end = base + size - 1; | |
297 | } | |
298 | } | |
299 | efi_memmap_res.start = ia64_boot_param->efi_memmap; | |
300 | efi_memmap_res.end = efi_memmap_res.start + | |
301 | ia64_boot_param->efi_memmap_size; | |
302 | boot_param_res.start = __pa(ia64_boot_param); | |
303 | boot_param_res.end = boot_param_res.start + | |
304 | sizeof(*ia64_boot_param); | |
305 | } | |
306 | #else | |
307 | static inline void __init setup_crashkernel(unsigned long total, int *n) | |
308 | {} | |
309 | #endif | |
310 | ||
1da177e4 LT |
311 | /** |
312 | * reserve_memory - setup reserved memory areas | |
313 | * | |
314 | * Setup the reserved memory areas set aside for the boot parameters, | |
315 | * initrd, etc. There are currently %IA64_MAX_RSVD_REGIONS defined, | |
316 | * see include/asm-ia64/meminit.h if you need to define more. | |
317 | */ | |
dae28066 | 318 | void __init |
1da177e4 LT |
319 | reserve_memory (void) |
320 | { | |
321 | int n = 0; | |
cb380853 | 322 | unsigned long total_memory; |
1da177e4 LT |
323 | |
324 | /* | |
325 | * none of the entries in this table overlap | |
326 | */ | |
327 | rsvd_region[n].start = (unsigned long) ia64_boot_param; | |
328 | rsvd_region[n].end = rsvd_region[n].start + sizeof(*ia64_boot_param); | |
329 | n++; | |
330 | ||
331 | rsvd_region[n].start = (unsigned long) __va(ia64_boot_param->efi_memmap); | |
332 | rsvd_region[n].end = rsvd_region[n].start + ia64_boot_param->efi_memmap_size; | |
333 | n++; | |
334 | ||
335 | rsvd_region[n].start = (unsigned long) __va(ia64_boot_param->command_line); | |
336 | rsvd_region[n].end = (rsvd_region[n].start | |
337 | + strlen(__va(ia64_boot_param->command_line)) + 1); | |
338 | n++; | |
339 | ||
340 | rsvd_region[n].start = (unsigned long) ia64_imva((void *)KERNEL_START); | |
341 | rsvd_region[n].end = (unsigned long) ia64_imva(_end); | |
342 | n++; | |
343 | ||
344 | #ifdef CONFIG_BLK_DEV_INITRD | |
345 | if (ia64_boot_param->initrd_start) { | |
346 | rsvd_region[n].start = (unsigned long)__va(ia64_boot_param->initrd_start); | |
347 | rsvd_region[n].end = rsvd_region[n].start + ia64_boot_param->initrd_size; | |
348 | n++; | |
349 | } | |
350 | #endif | |
351 | ||
cee87af2 MD |
352 | #ifdef CONFIG_PROC_VMCORE |
353 | if (reserve_elfcorehdr(&rsvd_region[n].start, | |
354 | &rsvd_region[n].end) == 0) | |
355 | n++; | |
356 | #endif | |
357 | ||
cb380853 | 358 | total_memory = efi_memmap_init(&rsvd_region[n].start, &rsvd_region[n].end); |
d8c97d5f TL |
359 | n++; |
360 | ||
cb380853 BW |
361 | setup_crashkernel(total_memory, &n); |
362 | ||
1da177e4 LT |
363 | /* end of memory marker */ |
364 | rsvd_region[n].start = ~0UL; | |
365 | rsvd_region[n].end = ~0UL; | |
366 | n++; | |
367 | ||
368 | num_rsvd_regions = n; | |
5eb1d63f | 369 | BUG_ON(IA64_MAX_RSVD_REGIONS + 1 < n); |
1da177e4 LT |
370 | |
371 | sort_regions(rsvd_region, num_rsvd_regions); | |
372 | } | |
373 | ||
a7956113 | 374 | |
1da177e4 LT |
375 | /** |
376 | * find_initrd - get initrd parameters from the boot parameter structure | |
377 | * | |
378 | * Grab the initrd start and end from the boot parameter struct given us by | |
379 | * the boot loader. | |
380 | */ | |
dae28066 | 381 | void __init |
1da177e4 LT |
382 | find_initrd (void) |
383 | { | |
384 | #ifdef CONFIG_BLK_DEV_INITRD | |
385 | if (ia64_boot_param->initrd_start) { | |
386 | initrd_start = (unsigned long)__va(ia64_boot_param->initrd_start); | |
387 | initrd_end = initrd_start+ia64_boot_param->initrd_size; | |
388 | ||
389 | printk(KERN_INFO "Initial ramdisk at: 0x%lx (%lu bytes)\n", | |
390 | initrd_start, ia64_boot_param->initrd_size); | |
391 | } | |
392 | #endif | |
393 | } | |
394 | ||
395 | static void __init | |
396 | io_port_init (void) | |
397 | { | |
1da177e4 LT |
398 | unsigned long phys_iobase; |
399 | ||
400 | /* | |
44c45120 BH |
401 | * Set `iobase' based on the EFI memory map or, failing that, the |
402 | * value firmware left in ar.k0. | |
1da177e4 | 403 | * |
44c45120 BH |
404 | * Note that in ia32 mode, IN/OUT instructions use ar.k0 to compute |
405 | * the port's virtual address, so ia32_load_state() loads it with a | |
406 | * user virtual address. But in ia64 mode, glibc uses the | |
407 | * *physical* address in ar.k0 to mmap the appropriate area from | |
408 | * /dev/mem, and the inX()/outX() interfaces use MMIO. In both | |
409 | * cases, user-mode can only use the legacy 0-64K I/O port space. | |
410 | * | |
411 | * ar.k0 is not involved in kernel I/O port accesses, which can use | |
412 | * any of the I/O port spaces and are done via MMIO using the | |
413 | * virtual mmio_base from the appropriate io_space[]. | |
1da177e4 LT |
414 | */ |
415 | phys_iobase = efi_get_iobase(); | |
44c45120 | 416 | if (!phys_iobase) { |
1da177e4 | 417 | phys_iobase = ia64_get_kr(IA64_KR_IO_BASE); |
44c45120 BH |
418 | printk(KERN_INFO "No I/O port range found in EFI memory map, " |
419 | "falling back to AR.KR0 (0x%lx)\n", phys_iobase); | |
1da177e4 LT |
420 | } |
421 | ia64_iobase = (unsigned long) ioremap(phys_iobase, 0); | |
44c45120 | 422 | ia64_set_kr(IA64_KR_IO_BASE, __pa(ia64_iobase)); |
1da177e4 LT |
423 | |
424 | /* setup legacy IO port space */ | |
425 | io_space[0].mmio_base = ia64_iobase; | |
426 | io_space[0].sparse = 1; | |
427 | num_io_spaces = 1; | |
428 | } | |
429 | ||
430 | /** | |
431 | * early_console_setup - setup debugging console | |
432 | * | |
433 | * Consoles started here require little enough setup that we can start using | |
434 | * them very early in the boot process, either right after the machine | |
435 | * vector initialization, or even before if the drivers can detect their hw. | |
436 | * | |
437 | * Returns non-zero if a console couldn't be setup. | |
438 | */ | |
439 | static inline int __init | |
440 | early_console_setup (char *cmdline) | |
441 | { | |
66b7f8a3 MM |
442 | int earlycons = 0; |
443 | ||
1da177e4 LT |
444 | #ifdef CONFIG_SERIAL_SGI_L1_CONSOLE |
445 | { | |
446 | extern int sn_serial_console_early_setup(void); | |
447 | if (!sn_serial_console_early_setup()) | |
66b7f8a3 | 448 | earlycons++; |
1da177e4 LT |
449 | } |
450 | #endif | |
451 | #ifdef CONFIG_EFI_PCDP | |
452 | if (!efi_setup_pcdp_console(cmdline)) | |
66b7f8a3 | 453 | earlycons++; |
1da177e4 | 454 | #endif |
8b713c67 | 455 | if (!simcons_register()) |
471e7a44 | 456 | earlycons++; |
1da177e4 | 457 | |
66b7f8a3 | 458 | return (earlycons) ? 0 : -1; |
1da177e4 LT |
459 | } |
460 | ||
461 | static inline void | |
462 | mark_bsp_online (void) | |
463 | { | |
464 | #ifdef CONFIG_SMP | |
465 | /* If we register an early console, allow CPU 0 to printk */ | |
466 | cpu_set(smp_processor_id(), cpu_online_map); | |
467 | #endif | |
468 | } | |
469 | ||
a5b00bb4 H |
470 | static __initdata int nomca; |
471 | static __init int setup_nomca(char *s) | |
472 | { | |
473 | nomca = 1; | |
474 | return 0; | |
475 | } | |
476 | early_param("nomca", setup_nomca); | |
477 | ||
45a98fc6 H |
478 | #ifdef CONFIG_PROC_VMCORE |
479 | /* elfcorehdr= specifies the location of elf core header | |
480 | * stored by the crashed kernel. | |
481 | */ | |
482 | static int __init parse_elfcorehdr(char *arg) | |
483 | { | |
484 | if (!arg) | |
485 | return -EINVAL; | |
486 | ||
487 | elfcorehdr_addr = memparse(arg, &arg); | |
488 | return 0; | |
489 | } | |
490 | early_param("elfcorehdr", parse_elfcorehdr); | |
cee87af2 MD |
491 | |
492 | int __init reserve_elfcorehdr(unsigned long *start, unsigned long *end) | |
493 | { | |
494 | unsigned long length; | |
495 | ||
496 | /* We get the address using the kernel command line, | |
497 | * but the size is extracted from the EFI tables. | |
498 | * Both address and size are required for reservation | |
499 | * to work properly. | |
500 | */ | |
501 | ||
502 | if (elfcorehdr_addr >= ELFCORE_ADDR_MAX) | |
503 | return -EINVAL; | |
504 | ||
505 | if ((length = vmcore_find_descriptor_size(elfcorehdr_addr)) == 0) { | |
506 | elfcorehdr_addr = ELFCORE_ADDR_MAX; | |
507 | return -EINVAL; | |
508 | } | |
509 | ||
510 | *start = (unsigned long)__va(elfcorehdr_addr); | |
511 | *end = *start + length; | |
512 | return 0; | |
513 | } | |
514 | ||
45a98fc6 H |
515 | #endif /* CONFIG_PROC_VMCORE */ |
516 | ||
1da177e4 LT |
517 | void __init |
518 | setup_arch (char **cmdline_p) | |
519 | { | |
520 | unw_init(); | |
521 | ||
522 | ia64_patch_vtop((u64) __start___vtop_patchlist, (u64) __end___vtop_patchlist); | |
523 | ||
524 | *cmdline_p = __va(ia64_boot_param->command_line); | |
a8d91b84 | 525 | strlcpy(boot_command_line, *cmdline_p, COMMAND_LINE_SIZE); |
1da177e4 LT |
526 | |
527 | efi_init(); | |
528 | io_port_init(); | |
529 | ||
530 | #ifdef CONFIG_IA64_GENERIC | |
a07ee862 H |
531 | /* machvec needs to be parsed from the command line |
532 | * before parse_early_param() is called to ensure | |
533 | * that ia64_mv is initialised before any command line | |
534 | * settings may cause console setup to occur | |
535 | */ | |
536 | machvec_init_from_cmdline(*cmdline_p); | |
1da177e4 LT |
537 | #endif |
538 | ||
a07ee862 H |
539 | parse_early_param(); |
540 | ||
1da177e4 LT |
541 | if (early_console_setup(*cmdline_p) == 0) |
542 | mark_bsp_online(); | |
543 | ||
888ba6c6 | 544 | #ifdef CONFIG_ACPI |
1da177e4 LT |
545 | /* Initialize the ACPI boot-time table parser */ |
546 | acpi_table_init(); | |
547 | # ifdef CONFIG_ACPI_NUMA | |
548 | acpi_numa_init(); | |
2c6e6db4 | 549 | per_cpu_scan_finalize((cpus_weight(early_cpu_possible_map) == 0 ? |
550 | 32 : cpus_weight(early_cpu_possible_map)), additional_cpus); | |
1da177e4 LT |
551 | # endif |
552 | #else | |
553 | # ifdef CONFIG_SMP | |
554 | smp_build_cpu_map(); /* happens, e.g., with the Ski simulator */ | |
555 | # endif | |
556 | #endif /* CONFIG_APCI_BOOT */ | |
557 | ||
558 | find_memory(); | |
559 | ||
560 | /* process SAL system table: */ | |
b2c99e3c | 561 | ia64_sal_init(__va(efi.sal_systab)); |
1da177e4 | 562 | |
4dcc29e1 TL |
563 | #ifdef CONFIG_ITANIUM |
564 | ia64_patch_rse((u64) __start___rse_patchlist, (u64) __end___rse_patchlist); | |
565 | #else | |
566 | { | |
567 | u64 num_phys_stacked; | |
568 | ||
569 | if (ia64_pal_rse_info(&num_phys_stacked, 0) == 0 && num_phys_stacked > 96) | |
570 | ia64_patch_rse((u64) __start___rse_patchlist, (u64) __end___rse_patchlist); | |
571 | } | |
572 | #endif | |
573 | ||
1da177e4 LT |
574 | #ifdef CONFIG_SMP |
575 | cpu_physical_id(0) = hard_smp_processor_id(); | |
576 | #endif | |
577 | ||
578 | cpu_init(); /* initialize the bootstrap CPU */ | |
dcc17d1b | 579 | mmu_context_init(); /* initialize context_id bitmap */ |
1da177e4 | 580 | |
888ba6c6 | 581 | #ifdef CONFIG_ACPI |
1da177e4 LT |
582 | acpi_boot_init(); |
583 | #endif | |
584 | ||
585 | #ifdef CONFIG_VT | |
586 | if (!conswitchp) { | |
587 | # if defined(CONFIG_DUMMY_CONSOLE) | |
588 | conswitchp = &dummy_con; | |
589 | # endif | |
590 | # if defined(CONFIG_VGA_CONSOLE) | |
591 | /* | |
592 | * Non-legacy systems may route legacy VGA MMIO range to system | |
593 | * memory. vga_con probes the MMIO hole, so memory looks like | |
594 | * a VGA device to it. The EFI memory map can tell us if it's | |
595 | * memory so we can avoid this problem. | |
596 | */ | |
597 | if (efi_mem_type(0xA0000) != EFI_CONVENTIONAL_MEMORY) | |
598 | conswitchp = &vga_con; | |
599 | # endif | |
600 | } | |
601 | #endif | |
602 | ||
603 | /* enable IA-64 Machine Check Abort Handling unless disabled */ | |
a5b00bb4 | 604 | if (!nomca) |
1da177e4 LT |
605 | ia64_mca_init(); |
606 | ||
607 | platform_setup(cmdline_p); | |
2826f8c0 | 608 | check_sal_cache_flush(); |
1da177e4 LT |
609 | paging_init(); |
610 | } | |
611 | ||
612 | /* | |
72fdbdce | 613 | * Display cpu info for all CPUs. |
1da177e4 LT |
614 | */ |
615 | static int | |
616 | show_cpuinfo (struct seq_file *m, void *v) | |
617 | { | |
618 | #ifdef CONFIG_SMP | |
619 | # define lpj c->loops_per_jiffy | |
620 | # define cpunum c->cpu | |
621 | #else | |
622 | # define lpj loops_per_jiffy | |
623 | # define cpunum 0 | |
624 | #endif | |
625 | static struct { | |
626 | unsigned long mask; | |
627 | const char *feature_name; | |
628 | } feature_bits[] = { | |
629 | { 1UL << 0, "branchlong" }, | |
630 | { 1UL << 1, "spontaneous deferral"}, | |
631 | { 1UL << 2, "16-byte atomic ops" } | |
632 | }; | |
ae0af3e3 | 633 | char features[128], *cp, *sep; |
1da177e4 LT |
634 | struct cpuinfo_ia64 *c = v; |
635 | unsigned long mask; | |
38c0b2c2 | 636 | unsigned long proc_freq; |
ae0af3e3 | 637 | int i, size; |
1da177e4 LT |
638 | |
639 | mask = c->features; | |
640 | ||
1da177e4 | 641 | /* build the feature string: */ |
ae0af3e3 | 642 | memcpy(features, "standard", 9); |
1da177e4 | 643 | cp = features; |
ae0af3e3 AG |
644 | size = sizeof(features); |
645 | sep = ""; | |
646 | for (i = 0; i < ARRAY_SIZE(feature_bits) && size > 1; ++i) { | |
1da177e4 | 647 | if (mask & feature_bits[i].mask) { |
ae0af3e3 AG |
648 | cp += snprintf(cp, size, "%s%s", sep, |
649 | feature_bits[i].feature_name), | |
650 | sep = ", "; | |
1da177e4 | 651 | mask &= ~feature_bits[i].mask; |
ae0af3e3 | 652 | size = sizeof(features) - (cp - features); |
1da177e4 LT |
653 | } |
654 | } | |
ae0af3e3 AG |
655 | if (mask && size > 1) { |
656 | /* print unknown features as a hex value */ | |
657 | snprintf(cp, size, "%s0x%lx", sep, mask); | |
1da177e4 LT |
658 | } |
659 | ||
95235ca2 VP |
660 | proc_freq = cpufreq_quick_get(cpunum); |
661 | if (!proc_freq) | |
662 | proc_freq = c->proc_freq / 1000; | |
663 | ||
1da177e4 LT |
664 | seq_printf(m, |
665 | "processor : %d\n" | |
666 | "vendor : %s\n" | |
667 | "arch : IA-64\n" | |
76d08bb3 | 668 | "family : %u\n" |
1da177e4 | 669 | "model : %u\n" |
76d08bb3 | 670 | "model name : %s\n" |
1da177e4 LT |
671 | "revision : %u\n" |
672 | "archrev : %u\n" | |
ae0af3e3 | 673 | "features : %s\n" |
1da177e4 LT |
674 | "cpu number : %lu\n" |
675 | "cpu regs : %u\n" | |
8a3a78d1 | 676 | "cpu MHz : %lu.%03lu\n" |
1da177e4 | 677 | "itc MHz : %lu.%06lu\n" |
e927ecb0 | 678 | "BogoMIPS : %lu.%02lu\n", |
76d08bb3 TL |
679 | cpunum, c->vendor, c->family, c->model, |
680 | c->model_name, c->revision, c->archrev, | |
1da177e4 | 681 | features, c->ppn, c->number, |
95235ca2 | 682 | proc_freq / 1000, proc_freq % 1000, |
1da177e4 LT |
683 | c->itc_freq / 1000000, c->itc_freq % 1000000, |
684 | lpj*HZ/500000, (lpj*HZ/5000) % 100); | |
e927ecb0 | 685 | #ifdef CONFIG_SMP |
ce6e71ad | 686 | seq_printf(m, "siblings : %u\n", cpus_weight(cpu_core_map[cpunum])); |
113134fc AC |
687 | if (c->socket_id != -1) |
688 | seq_printf(m, "physical id: %u\n", c->socket_id); | |
e927ecb0 SS |
689 | if (c->threads_per_core > 1 || c->cores_per_socket > 1) |
690 | seq_printf(m, | |
113134fc AC |
691 | "core id : %u\n" |
692 | "thread id : %u\n", | |
693 | c->core_id, c->thread_id); | |
e927ecb0 SS |
694 | #endif |
695 | seq_printf(m,"\n"); | |
696 | ||
1da177e4 LT |
697 | return 0; |
698 | } | |
699 | ||
700 | static void * | |
701 | c_start (struct seq_file *m, loff_t *pos) | |
702 | { | |
703 | #ifdef CONFIG_SMP | |
704 | while (*pos < NR_CPUS && !cpu_isset(*pos, cpu_online_map)) | |
705 | ++*pos; | |
706 | #endif | |
707 | return *pos < NR_CPUS ? cpu_data(*pos) : NULL; | |
708 | } | |
709 | ||
710 | static void * | |
711 | c_next (struct seq_file *m, void *v, loff_t *pos) | |
712 | { | |
713 | ++*pos; | |
714 | return c_start(m, pos); | |
715 | } | |
716 | ||
717 | static void | |
718 | c_stop (struct seq_file *m, void *v) | |
719 | { | |
720 | } | |
721 | ||
a23fe55e | 722 | const struct seq_operations cpuinfo_op = { |
1da177e4 LT |
723 | .start = c_start, |
724 | .next = c_next, | |
725 | .stop = c_stop, | |
726 | .show = show_cpuinfo | |
727 | }; | |
728 | ||
c5e83e3f JS |
729 | #define MAX_BRANDS 8 |
730 | static char brandname[MAX_BRANDS][128]; | |
76d08bb3 TL |
731 | |
732 | static char * __cpuinit | |
733 | get_model_name(__u8 family, __u8 model) | |
734 | { | |
c5e83e3f | 735 | static int overflow; |
76d08bb3 | 736 | char brand[128]; |
c5e83e3f | 737 | int i; |
76d08bb3 | 738 | |
75f6a1de | 739 | memcpy(brand, "Unknown", 8); |
76d08bb3 TL |
740 | if (ia64_pal_get_brand_info(brand)) { |
741 | if (family == 0x7) | |
742 | memcpy(brand, "Merced", 7); | |
743 | else if (family == 0x1f) switch (model) { | |
744 | case 0: memcpy(brand, "McKinley", 9); break; | |
745 | case 1: memcpy(brand, "Madison", 8); break; | |
746 | case 2: memcpy(brand, "Madison up to 9M cache", 23); break; | |
75f6a1de | 747 | } |
76d08bb3 | 748 | } |
c5e83e3f JS |
749 | for (i = 0; i < MAX_BRANDS; i++) |
750 | if (strcmp(brandname[i], brand) == 0) | |
751 | return brandname[i]; | |
752 | for (i = 0; i < MAX_BRANDS; i++) | |
753 | if (brandname[i][0] == '\0') | |
754 | return strcpy(brandname[i], brand); | |
755 | if (overflow++ == 0) | |
756 | printk(KERN_ERR | |
757 | "%s: Table overflow. Some processor model information will be missing\n", | |
d4ed8084 | 758 | __func__); |
c5e83e3f | 759 | return "Unknown"; |
76d08bb3 TL |
760 | } |
761 | ||
244fd545 | 762 | static void __cpuinit |
1da177e4 LT |
763 | identify_cpu (struct cpuinfo_ia64 *c) |
764 | { | |
765 | union { | |
766 | unsigned long bits[5]; | |
767 | struct { | |
768 | /* id 0 & 1: */ | |
769 | char vendor[16]; | |
770 | ||
771 | /* id 2 */ | |
772 | u64 ppn; /* processor serial number */ | |
773 | ||
774 | /* id 3: */ | |
775 | unsigned number : 8; | |
776 | unsigned revision : 8; | |
777 | unsigned model : 8; | |
778 | unsigned family : 8; | |
779 | unsigned archrev : 8; | |
780 | unsigned reserved : 24; | |
781 | ||
782 | /* id 4: */ | |
783 | u64 features; | |
784 | } field; | |
785 | } cpuid; | |
786 | pal_vm_info_1_u_t vm1; | |
787 | pal_vm_info_2_u_t vm2; | |
788 | pal_status_t status; | |
789 | unsigned long impl_va_msb = 50, phys_addr_size = 44; /* Itanium defaults */ | |
790 | int i; | |
1da177e4 LT |
791 | for (i = 0; i < 5; ++i) |
792 | cpuid.bits[i] = ia64_get_cpuid(i); | |
793 | ||
794 | memcpy(c->vendor, cpuid.field.vendor, 16); | |
795 | #ifdef CONFIG_SMP | |
796 | c->cpu = smp_processor_id(); | |
e927ecb0 SS |
797 | |
798 | /* below default values will be overwritten by identify_siblings() | |
72fdbdce | 799 | * for Multi-Threading/Multi-Core capable CPUs |
e927ecb0 SS |
800 | */ |
801 | c->threads_per_core = c->cores_per_socket = c->num_log = 1; | |
802 | c->socket_id = -1; | |
803 | ||
804 | identify_siblings(c); | |
113134fc AC |
805 | |
806 | if (c->threads_per_core > smp_num_siblings) | |
807 | smp_num_siblings = c->threads_per_core; | |
1da177e4 LT |
808 | #endif |
809 | c->ppn = cpuid.field.ppn; | |
810 | c->number = cpuid.field.number; | |
811 | c->revision = cpuid.field.revision; | |
812 | c->model = cpuid.field.model; | |
813 | c->family = cpuid.field.family; | |
814 | c->archrev = cpuid.field.archrev; | |
815 | c->features = cpuid.field.features; | |
76d08bb3 | 816 | c->model_name = get_model_name(c->family, c->model); |
1da177e4 LT |
817 | |
818 | status = ia64_pal_vm_summary(&vm1, &vm2); | |
819 | if (status == PAL_STATUS_SUCCESS) { | |
820 | impl_va_msb = vm2.pal_vm_info_2_s.impl_va_msb; | |
821 | phys_addr_size = vm1.pal_vm_info_1_s.phys_add_size; | |
822 | } | |
823 | c->unimpl_va_mask = ~((7L<<61) | ((1L << (impl_va_msb + 1)) - 1)); | |
824 | c->unimpl_pa_mask = ~((1L<<63) | ((1L << phys_addr_size) - 1)); | |
825 | } | |
826 | ||
0f7ac29e | 827 | void __init |
1da177e4 LT |
828 | setup_per_cpu_areas (void) |
829 | { | |
830 | /* start_kernel() requires this... */ | |
a6b14fa6 AR |
831 | #ifdef CONFIG_ACPI_HOTPLUG_CPU |
832 | prefill_possible_map(); | |
833 | #endif | |
1da177e4 LT |
834 | } |
835 | ||
08357f82 ZM |
836 | /* |
837 | * Calculate the max. cache line size. | |
838 | * | |
839 | * In addition, the minimum of the i-cache stride sizes is calculated for | |
840 | * "flush_icache_range()". | |
841 | */ | |
244fd545 | 842 | static void __cpuinit |
1da177e4 LT |
843 | get_max_cacheline_size (void) |
844 | { | |
845 | unsigned long line_size, max = 1; | |
846 | u64 l, levels, unique_caches; | |
847 | pal_cache_config_info_t cci; | |
848 | s64 status; | |
849 | ||
850 | status = ia64_pal_cache_summary(&levels, &unique_caches); | |
851 | if (status != 0) { | |
852 | printk(KERN_ERR "%s: ia64_pal_cache_summary() failed (status=%ld)\n", | |
d4ed8084 | 853 | __func__, status); |
1da177e4 | 854 | max = SMP_CACHE_BYTES; |
08357f82 ZM |
855 | /* Safest setup for "flush_icache_range()" */ |
856 | ia64_i_cache_stride_shift = I_CACHE_STRIDE_SHIFT; | |
1da177e4 LT |
857 | goto out; |
858 | } | |
859 | ||
860 | for (l = 0; l < levels; ++l) { | |
861 | status = ia64_pal_cache_config_info(l, /* cache_type (data_or_unified)= */ 2, | |
862 | &cci); | |
863 | if (status != 0) { | |
864 | printk(KERN_ERR | |
08357f82 | 865 | "%s: ia64_pal_cache_config_info(l=%lu, 2) failed (status=%ld)\n", |
d4ed8084 | 866 | __func__, l, status); |
1da177e4 | 867 | max = SMP_CACHE_BYTES; |
08357f82 ZM |
868 | /* The safest setup for "flush_icache_range()" */ |
869 | cci.pcci_stride = I_CACHE_STRIDE_SHIFT; | |
870 | cci.pcci_unified = 1; | |
1da177e4 LT |
871 | } |
872 | line_size = 1 << cci.pcci_line_size; | |
873 | if (line_size > max) | |
874 | max = line_size; | |
08357f82 ZM |
875 | if (!cci.pcci_unified) { |
876 | status = ia64_pal_cache_config_info(l, | |
877 | /* cache_type (instruction)= */ 1, | |
878 | &cci); | |
879 | if (status != 0) { | |
880 | printk(KERN_ERR | |
881 | "%s: ia64_pal_cache_config_info(l=%lu, 1) failed (status=%ld)\n", | |
d4ed8084 | 882 | __func__, l, status); |
08357f82 ZM |
883 | /* The safest setup for "flush_icache_range()" */ |
884 | cci.pcci_stride = I_CACHE_STRIDE_SHIFT; | |
885 | } | |
886 | } | |
887 | if (cci.pcci_stride < ia64_i_cache_stride_shift) | |
888 | ia64_i_cache_stride_shift = cci.pcci_stride; | |
889 | } | |
1da177e4 LT |
890 | out: |
891 | if (max > ia64_max_cacheline_size) | |
892 | ia64_max_cacheline_size = max; | |
893 | } | |
894 | ||
895 | /* | |
896 | * cpu_init() initializes state that is per-CPU. This function acts | |
897 | * as a 'CPU state barrier', nothing should get across. | |
898 | */ | |
244fd545 | 899 | void __cpuinit |
1da177e4 LT |
900 | cpu_init (void) |
901 | { | |
244fd545 | 902 | extern void __cpuinit ia64_mmu_init (void *); |
a0776ec8 | 903 | static unsigned long max_num_phys_stacked = IA64_NUM_PHYS_STACK_REG; |
1da177e4 LT |
904 | unsigned long num_phys_stacked; |
905 | pal_vm_info_2_u_t vmi; | |
906 | unsigned int max_ctx; | |
907 | struct cpuinfo_ia64 *cpu_info; | |
908 | void *cpu_data; | |
909 | ||
910 | cpu_data = per_cpu_init(); | |
4d1efed5 | 911 | #ifdef CONFIG_SMP |
d5a7430d MT |
912 | /* |
913 | * insert boot cpu into sibling and core mapes | |
914 | * (must be done after per_cpu area is setup) | |
915 | */ | |
916 | if (smp_processor_id() == 0) { | |
917 | cpu_set(0, per_cpu(cpu_sibling_map, 0)); | |
918 | cpu_set(0, cpu_core_map[0]); | |
919 | } | |
4d1efed5 | 920 | #endif |
1da177e4 LT |
921 | |
922 | /* | |
923 | * We set ar.k3 so that assembly code in MCA handler can compute | |
924 | * physical addresses of per cpu variables with a simple: | |
925 | * phys = ar.k3 + &per_cpu_var | |
926 | */ | |
927 | ia64_set_kr(IA64_KR_PER_CPU_DATA, | |
928 | ia64_tpa(cpu_data) - (long) __per_cpu_start); | |
929 | ||
930 | get_max_cacheline_size(); | |
931 | ||
932 | /* | |
933 | * We can't pass "local_cpu_data" to identify_cpu() because we haven't called | |
934 | * ia64_mmu_init() yet. And we can't call ia64_mmu_init() first because it | |
935 | * depends on the data returned by identify_cpu(). We break the dependency by | |
936 | * accessing cpu_data() through the canonical per-CPU address. | |
937 | */ | |
938 | cpu_info = cpu_data + ((char *) &__ia64_per_cpu_var(cpu_info) - __per_cpu_start); | |
939 | identify_cpu(cpu_info); | |
940 | ||
941 | #ifdef CONFIG_MCKINLEY | |
942 | { | |
943 | # define FEATURE_SET 16 | |
944 | struct ia64_pal_retval iprv; | |
945 | ||
946 | if (cpu_info->family == 0x1f) { | |
947 | PAL_CALL_PHYS(iprv, PAL_PROC_GET_FEATURES, 0, FEATURE_SET, 0); | |
948 | if ((iprv.status == 0) && (iprv.v0 & 0x80) && (iprv.v2 & 0x80)) | |
949 | PAL_CALL_PHYS(iprv, PAL_PROC_SET_FEATURES, | |
950 | (iprv.v1 | 0x80), FEATURE_SET, 0); | |
951 | } | |
952 | } | |
953 | #endif | |
954 | ||
955 | /* Clear the stack memory reserved for pt_regs: */ | |
6450578f | 956 | memset(task_pt_regs(current), 0, sizeof(struct pt_regs)); |
1da177e4 LT |
957 | |
958 | ia64_set_kr(IA64_KR_FPU_OWNER, 0); | |
959 | ||
960 | /* | |
961 | * Initialize the page-table base register to a global | |
962 | * directory with all zeroes. This ensure that we can handle | |
963 | * TLB-misses to user address-space even before we created the | |
964 | * first user address-space. This may happen, e.g., due to | |
965 | * aggressive use of lfetch.fault. | |
966 | */ | |
967 | ia64_set_kr(IA64_KR_PT_BASE, __pa(ia64_imva(empty_zero_page))); | |
968 | ||
969 | /* | |
86ebacd3 TL |
970 | * Initialize default control register to defer speculative faults except |
971 | * for those arising from TLB misses, which are not deferred. The | |
1da177e4 LT |
972 | * kernel MUST NOT depend on a particular setting of these bits (in other words, |
973 | * the kernel must have recovery code for all speculative accesses). Turn on | |
974 | * dcr.lc as per recommendation by the architecture team. Most IA-32 apps | |
975 | * shouldn't be affected by this (moral: keep your ia32 locks aligned and you'll | |
976 | * be fine). | |
977 | */ | |
978 | ia64_setreg(_IA64_REG_CR_DCR, ( IA64_DCR_DP | IA64_DCR_DK | IA64_DCR_DX | IA64_DCR_DR | |
979 | | IA64_DCR_DA | IA64_DCR_DD | IA64_DCR_LC)); | |
980 | atomic_inc(&init_mm.mm_count); | |
981 | current->active_mm = &init_mm; | |
982 | if (current->mm) | |
983 | BUG(); | |
984 | ||
985 | ia64_mmu_init(ia64_imva(cpu_data)); | |
986 | ia64_mca_cpu_init(ia64_imva(cpu_data)); | |
987 | ||
988 | #ifdef CONFIG_IA32_SUPPORT | |
989 | ia32_cpu_init(); | |
990 | #endif | |
991 | ||
72fdbdce | 992 | /* Clear ITC to eliminate sched_clock() overflows in human time. */ |
1da177e4 LT |
993 | ia64_set_itc(0); |
994 | ||
995 | /* disable all local interrupt sources: */ | |
996 | ia64_set_itv(1 << 16); | |
997 | ia64_set_lrr0(1 << 16); | |
998 | ia64_set_lrr1(1 << 16); | |
999 | ia64_setreg(_IA64_REG_CR_PMV, 1 << 16); | |
1000 | ia64_setreg(_IA64_REG_CR_CMCV, 1 << 16); | |
1001 | ||
1002 | /* clear TPR & XTP to enable all interrupt classes: */ | |
1003 | ia64_setreg(_IA64_REG_CR_TPR, 0); | |
f740e6c9 KK |
1004 | |
1005 | /* Clear any pending interrupts left by SAL/EFI */ | |
1006 | while (ia64_get_ivr() != IA64_SPURIOUS_INT_VECTOR) | |
1007 | ia64_eoi(); | |
1008 | ||
1da177e4 LT |
1009 | #ifdef CONFIG_SMP |
1010 | normal_xtp(); | |
1011 | #endif | |
1012 | ||
1013 | /* set ia64_ctx.max_rid to the maximum RID that is supported by all CPUs: */ | |
2046b94e | 1014 | if (ia64_pal_vm_summary(NULL, &vmi) == 0) { |
1da177e4 | 1015 | max_ctx = (1U << (vmi.pal_vm_info_2_s.rid_size - 3)) - 1; |
a6c75b86 | 1016 | setup_ptcg_sem(vmi.pal_vm_info_2_s.max_purges, NPTCG_FROM_PAL); |
2046b94e | 1017 | } else { |
1da177e4 LT |
1018 | printk(KERN_WARNING "cpu_init: PAL VM summary failed, assuming 18 RID bits\n"); |
1019 | max_ctx = (1U << 15) - 1; /* use architected minimum */ | |
1020 | } | |
1021 | while (max_ctx < ia64_ctx.max_ctx) { | |
1022 | unsigned int old = ia64_ctx.max_ctx; | |
1023 | if (cmpxchg(&ia64_ctx.max_ctx, old, max_ctx) == old) | |
1024 | break; | |
1025 | } | |
1026 | ||
1027 | if (ia64_pal_rse_info(&num_phys_stacked, NULL) != 0) { | |
1028 | printk(KERN_WARNING "cpu_init: PAL RSE info failed; assuming 96 physical " | |
1029 | "stacked regs\n"); | |
1030 | num_phys_stacked = 96; | |
1031 | } | |
1032 | /* size of physical stacked register partition plus 8 bytes: */ | |
a0776ec8 KC |
1033 | if (num_phys_stacked > max_num_phys_stacked) { |
1034 | ia64_patch_phys_stack_reg(num_phys_stacked*8 + 8); | |
1035 | max_num_phys_stacked = num_phys_stacked; | |
1036 | } | |
1da177e4 | 1037 | platform_cpu_init(); |
6c4fa560 | 1038 | pm_idle = default_idle; |
1da177e4 LT |
1039 | } |
1040 | ||
244fd545 | 1041 | void __init |
1da177e4 LT |
1042 | check_bugs (void) |
1043 | { | |
1044 | ia64_patch_mckinley_e9((unsigned long) __start___mckinley_e9_bundles, | |
1045 | (unsigned long) __end___mckinley_e9_bundles); | |
1046 | } | |
3ed3bce8 MD |
1047 | |
1048 | static int __init run_dmi_scan(void) | |
1049 | { | |
1050 | dmi_scan_machine(); | |
1051 | return 0; | |
1052 | } | |
1053 | core_initcall(run_dmi_scan); |