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1da177e4 LT |
1 | /* |
2 | * linux/arch/ia64/kernel/time.c | |
3 | * | |
4 | * Copyright (C) 1998-2003 Hewlett-Packard Co | |
5 | * Stephane Eranian <eranian@hpl.hp.com> | |
6 | * David Mosberger <davidm@hpl.hp.com> | |
7 | * Copyright (C) 1999 Don Dugger <don.dugger@intel.com> | |
8 | * Copyright (C) 1999-2000 VA Linux Systems | |
9 | * Copyright (C) 1999-2000 Walt Drummond <drummond@valinux.com> | |
10 | */ | |
1da177e4 LT |
11 | |
12 | #include <linux/cpu.h> | |
13 | #include <linux/init.h> | |
14 | #include <linux/kernel.h> | |
15 | #include <linux/module.h> | |
16 | #include <linux/profile.h> | |
17 | #include <linux/sched.h> | |
18 | #include <linux/time.h> | |
19 | #include <linux/interrupt.h> | |
20 | #include <linux/efi.h> | |
1da177e4 | 21 | #include <linux/timex.h> |
189374ae | 22 | #include <linux/timekeeper_internal.h> |
5e3fd9e5 | 23 | #include <linux/platform_device.h> |
1da177e4 LT |
24 | |
25 | #include <asm/machvec.h> | |
26 | #include <asm/delay.h> | |
27 | #include <asm/hw_irq.h> | |
28 | #include <asm/ptrace.h> | |
29 | #include <asm/sal.h> | |
30 | #include <asm/sections.h> | |
1da177e4 | 31 | |
0aa366f3 TL |
32 | #include "fsyscall_gtod_data.h" |
33 | ||
8e19608e | 34 | static cycle_t itc_get_cycles(struct clocksource *cs); |
0aa366f3 | 35 | |
74a622be | 36 | struct fsyscall_gtod_data_t fsyscall_gtod_data; |
0aa366f3 TL |
37 | |
38 | struct itc_jitter_data_t itc_jitter_data; | |
39 | ||
ff741906 | 40 | volatile int time_keeper_id = 0; /* smp_processor_id() of time-keeper */ |
1da177e4 LT |
41 | |
42 | #ifdef CONFIG_IA64_DEBUG_IRQ | |
43 | ||
44 | unsigned long last_cli_ip; | |
45 | EXPORT_SYMBOL(last_cli_ip); | |
46 | ||
47 | #endif | |
48 | ||
0aa366f3 | 49 | static struct clocksource clocksource_itc = { |
3eb05676 LZ |
50 | .name = "itc", |
51 | .rating = 350, | |
52 | .read = itc_get_cycles, | |
53 | .mask = CLOCKSOURCE_MASK(64), | |
3eb05676 | 54 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, |
1da177e4 | 55 | }; |
0aa366f3 | 56 | static struct clocksource *itc_clocksource; |
1da177e4 | 57 | |
abf917cd | 58 | #ifdef CONFIG_VIRT_CPU_ACCOUNTING_NATIVE |
b64f34cd HS |
59 | |
60 | #include <linux/kernel_stat.h> | |
61 | ||
62 | extern cputime_t cycle_to_cputime(u64 cyc); | |
63 | ||
bcebdf84 | 64 | void vtime_account_user(struct task_struct *tsk) |
5bf412cd FW |
65 | { |
66 | cputime_t delta_utime; | |
67 | struct thread_info *ti = task_thread_info(tsk); | |
68 | ||
69 | if (ti->ac_utime) { | |
70 | delta_utime = cycle_to_cputime(ti->ac_utime); | |
71 | account_user_time(tsk, delta_utime, delta_utime); | |
72 | ti->ac_utime = 0; | |
73 | } | |
74 | } | |
75 | ||
b64f34cd HS |
76 | /* |
77 | * Called from the context switch with interrupts disabled, to charge all | |
78 | * accumulated times to the current process, and to prepare accounting on | |
79 | * the next process. | |
80 | */ | |
e3942ba0 | 81 | void arch_vtime_task_switch(struct task_struct *prev) |
b64f34cd HS |
82 | { |
83 | struct thread_info *pi = task_thread_info(prev); | |
baa36046 | 84 | struct thread_info *ni = task_thread_info(current); |
b64f34cd | 85 | |
9dc16f64 | 86 | pi->ac_stamp = ni->ac_stamp; |
b64f34cd HS |
87 | ni->ac_stime = ni->ac_utime = 0; |
88 | } | |
89 | ||
90 | /* | |
91 | * Account time for a transition between system, hard irq or soft irq state. | |
92 | * Note that this function is called with interrupts enabled. | |
93 | */ | |
a7e1a9e3 | 94 | static cputime_t vtime_delta(struct task_struct *tsk) |
b64f34cd HS |
95 | { |
96 | struct thread_info *ti = task_thread_info(tsk); | |
b64f34cd HS |
97 | cputime_t delta_stime; |
98 | __u64 now; | |
99 | ||
1b2852b1 FW |
100 | WARN_ON_ONCE(!irqs_disabled()); |
101 | ||
b64f34cd HS |
102 | now = ia64_get_itc(); |
103 | ||
104 | delta_stime = cycle_to_cputime(ti->ac_stime + (now - ti->ac_stamp)); | |
b64f34cd | 105 | ti->ac_stime = 0; |
b64f34cd HS |
106 | ti->ac_stamp = now; |
107 | ||
a7e1a9e3 FW |
108 | return delta_stime; |
109 | } | |
110 | ||
fd25b4c2 | 111 | void vtime_account_system(struct task_struct *tsk) |
a7e1a9e3 FW |
112 | { |
113 | cputime_t delta = vtime_delta(tsk); | |
114 | ||
115 | account_system_time(tsk, 0, delta, delta); | |
116 | } | |
c11f11fc | 117 | EXPORT_SYMBOL_GPL(vtime_account_system); |
a7e1a9e3 | 118 | |
fd25b4c2 | 119 | void vtime_account_idle(struct task_struct *tsk) |
a7e1a9e3 FW |
120 | { |
121 | account_idle_time(vtime_delta(tsk)); | |
b64f34cd HS |
122 | } |
123 | ||
abf917cd | 124 | #endif /* CONFIG_VIRT_CPU_ACCOUNTING_NATIVE */ |
b64f34cd | 125 | |
1da177e4 | 126 | static irqreturn_t |
7d12e780 | 127 | timer_interrupt (int irq, void *dev_id) |
1da177e4 LT |
128 | { |
129 | unsigned long new_itm; | |
130 | ||
e7d28253 | 131 | if (cpu_is_offline(smp_processor_id())) { |
1da177e4 LT |
132 | return IRQ_HANDLED; |
133 | } | |
134 | ||
7d12e780 | 135 | platform_timer_interrupt(irq, dev_id); |
1da177e4 LT |
136 | |
137 | new_itm = local_cpu_data->itm_next; | |
138 | ||
139 | if (!time_after(ia64_get_itc(), new_itm)) | |
140 | printk(KERN_ERR "Oops: timer tick before it's due (itc=%lx,itm=%lx)\n", | |
141 | ia64_get_itc(), new_itm); | |
142 | ||
7d12e780 | 143 | profile_tick(CPU_PROFILING); |
1da177e4 LT |
144 | |
145 | while (1) { | |
7d12e780 | 146 | update_process_times(user_mode(get_irq_regs())); |
1da177e4 LT |
147 | |
148 | new_itm += local_cpu_data->itm_delta; | |
149 | ||
1aabd67d TH |
150 | if (smp_processor_id() == time_keeper_id) |
151 | xtime_update(1); | |
152 | ||
153 | local_cpu_data->itm_next = new_itm; | |
1da177e4 LT |
154 | |
155 | if (time_after(new_itm, ia64_get_itc())) | |
156 | break; | |
accaddb2 JS |
157 | |
158 | /* | |
159 | * Allow IPIs to interrupt the timer loop. | |
160 | */ | |
161 | local_irq_enable(); | |
162 | local_irq_disable(); | |
1da177e4 LT |
163 | } |
164 | ||
165 | do { | |
166 | /* | |
167 | * If we're too close to the next clock tick for | |
168 | * comfort, we increase the safety margin by | |
169 | * intentionally dropping the next tick(s). We do NOT | |
170 | * update itm.next because that would force us to call | |
1aabd67d | 171 | * xtime_update() which in turn would let our clock run |
1da177e4 LT |
172 | * too fast (with the potentially devastating effect |
173 | * of losing monotony of time). | |
174 | */ | |
175 | while (!time_after(new_itm, ia64_get_itc() + local_cpu_data->itm_delta/2)) | |
176 | new_itm += local_cpu_data->itm_delta; | |
177 | ia64_set_itm(new_itm); | |
178 | /* double check, in case we got hit by a (slow) PMI: */ | |
179 | } while (time_after_eq(ia64_get_itc(), new_itm)); | |
180 | return IRQ_HANDLED; | |
181 | } | |
182 | ||
183 | /* | |
184 | * Encapsulate access to the itm structure for SMP. | |
185 | */ | |
186 | void | |
187 | ia64_cpu_local_tick (void) | |
188 | { | |
189 | int cpu = smp_processor_id(); | |
190 | unsigned long shift = 0, delta; | |
191 | ||
192 | /* arrange for the cycle counter to generate a timer interrupt: */ | |
193 | ia64_set_itv(IA64_TIMER_VECTOR); | |
194 | ||
195 | delta = local_cpu_data->itm_delta; | |
196 | /* | |
197 | * Stagger the timer tick for each CPU so they don't occur all at (almost) the | |
198 | * same time: | |
199 | */ | |
200 | if (cpu) { | |
201 | unsigned long hi = 1UL << ia64_fls(cpu); | |
202 | shift = (2*(cpu - hi) + 1) * delta/hi/2; | |
203 | } | |
204 | local_cpu_data->itm_next = ia64_get_itc() + delta + shift; | |
205 | ia64_set_itm(local_cpu_data->itm_next); | |
206 | } | |
207 | ||
208 | static int nojitter; | |
209 | ||
210 | static int __init nojitter_setup(char *str) | |
211 | { | |
212 | nojitter = 1; | |
213 | printk("Jitter checking for ITC timers disabled\n"); | |
214 | return 1; | |
215 | } | |
216 | ||
217 | __setup("nojitter", nojitter_setup); | |
218 | ||
219 | ||
5b5e76e9 | 220 | void ia64_init_itm(void) |
1da177e4 LT |
221 | { |
222 | unsigned long platform_base_freq, itc_freq; | |
223 | struct pal_freq_ratio itc_ratio, proc_ratio; | |
224 | long status, platform_base_drift, itc_drift; | |
225 | ||
226 | /* | |
227 | * According to SAL v2.6, we need to use a SAL call to determine the platform base | |
228 | * frequency and then a PAL call to determine the frequency ratio between the ITC | |
229 | * and the base frequency. | |
230 | */ | |
231 | status = ia64_sal_freq_base(SAL_FREQ_BASE_PLATFORM, | |
232 | &platform_base_freq, &platform_base_drift); | |
233 | if (status != 0) { | |
234 | printk(KERN_ERR "SAL_FREQ_BASE_PLATFORM failed: %s\n", ia64_sal_strerror(status)); | |
235 | } else { | |
236 | status = ia64_pal_freq_ratios(&proc_ratio, NULL, &itc_ratio); | |
237 | if (status != 0) | |
238 | printk(KERN_ERR "PAL_FREQ_RATIOS failed with status=%ld\n", status); | |
239 | } | |
240 | if (status != 0) { | |
241 | /* invent "random" values */ | |
242 | printk(KERN_ERR | |
243 | "SAL/PAL failed to obtain frequency info---inventing reasonable values\n"); | |
244 | platform_base_freq = 100000000; | |
245 | platform_base_drift = -1; /* no drift info */ | |
246 | itc_ratio.num = 3; | |
247 | itc_ratio.den = 1; | |
248 | } | |
249 | if (platform_base_freq < 40000000) { | |
250 | printk(KERN_ERR "Platform base frequency %lu bogus---resetting to 75MHz!\n", | |
251 | platform_base_freq); | |
252 | platform_base_freq = 75000000; | |
253 | platform_base_drift = -1; | |
254 | } | |
255 | if (!proc_ratio.den) | |
256 | proc_ratio.den = 1; /* avoid division by zero */ | |
257 | if (!itc_ratio.den) | |
258 | itc_ratio.den = 1; /* avoid division by zero */ | |
259 | ||
260 | itc_freq = (platform_base_freq*itc_ratio.num)/itc_ratio.den; | |
261 | ||
262 | local_cpu_data->itm_delta = (itc_freq + HZ/2) / HZ; | |
2ab9391d | 263 | printk(KERN_DEBUG "CPU %d: base freq=%lu.%03luMHz, ITC ratio=%u/%u, " |
1da177e4 LT |
264 | "ITC freq=%lu.%03luMHz", smp_processor_id(), |
265 | platform_base_freq / 1000000, (platform_base_freq / 1000) % 1000, | |
266 | itc_ratio.num, itc_ratio.den, itc_freq / 1000000, (itc_freq / 1000) % 1000); | |
267 | ||
268 | if (platform_base_drift != -1) { | |
269 | itc_drift = platform_base_drift*itc_ratio.num/itc_ratio.den; | |
270 | printk("+/-%ldppm\n", itc_drift); | |
271 | } else { | |
272 | itc_drift = -1; | |
273 | printk("\n"); | |
274 | } | |
275 | ||
276 | local_cpu_data->proc_freq = (platform_base_freq*proc_ratio.num)/proc_ratio.den; | |
277 | local_cpu_data->itc_freq = itc_freq; | |
278 | local_cpu_data->cyc_per_usec = (itc_freq + USEC_PER_SEC/2) / USEC_PER_SEC; | |
279 | local_cpu_data->nsec_per_cyc = ((NSEC_PER_SEC<<IA64_NSEC_PER_CYC_SHIFT) | |
280 | + itc_freq/2)/itc_freq; | |
281 | ||
282 | if (!(sal_platform_features & IA64_SAL_PLATFORM_FEATURE_ITC_DRIFT)) { | |
1da177e4 LT |
283 | #ifdef CONFIG_SMP |
284 | /* On IA64 in an SMP configuration ITCs are never accurately synchronized. | |
285 | * Jitter compensation requires a cmpxchg which may limit | |
286 | * the scalability of the syscalls for retrieving time. | |
287 | * The ITC synchronization is usually successful to within a few | |
288 | * ITC ticks but this is not a sure thing. If you need to improve | |
289 | * timer performance in SMP situations then boot the kernel with the | |
290 | * "nojitter" option. However, doing so may result in time fluctuating (maybe | |
291 | * even going backward) if the ITC offsets between the individual CPUs | |
292 | * are too large. | |
293 | */ | |
0aa366f3 TL |
294 | if (!nojitter) |
295 | itc_jitter_data.itc_jitter = 1; | |
1da177e4 | 296 | #endif |
b718f91c CL |
297 | } else |
298 | /* | |
299 | * ITC is drifty and we have not synchronized the ITCs in smpboot.c. | |
300 | * ITC values may fluctuate significantly between processors. | |
301 | * Clock should not be used for hrtimers. Mark itc as only | |
302 | * useful for boot and testing. | |
303 | * | |
304 | * Note that jitter compensation is off! There is no point of | |
305 | * synchronizing ITCs since they may be large differentials | |
306 | * that change over time. | |
307 | * | |
308 | * The only way to fix this would be to repeatedly sync the | |
309 | * ITCs. Until that time we have to avoid ITC. | |
310 | */ | |
311 | clocksource_itc.rating = 50; | |
1da177e4 | 312 | |
00d21d82 IY |
313 | /* avoid softlock up message when cpu is unplug and plugged again. */ |
314 | touch_softlockup_watchdog(); | |
315 | ||
1da177e4 LT |
316 | /* Setup the CPU local timer tick */ |
317 | ia64_cpu_local_tick(); | |
0aa366f3 TL |
318 | |
319 | if (!itc_clocksource) { | |
d60c3041 JS |
320 | clocksource_register_hz(&clocksource_itc, |
321 | local_cpu_data->itc_freq); | |
0aa366f3 TL |
322 | itc_clocksource = &clocksource_itc; |
323 | } | |
1da177e4 LT |
324 | } |
325 | ||
8e19608e | 326 | static cycle_t itc_get_cycles(struct clocksource *cs) |
0aa366f3 | 327 | { |
e088a4ad | 328 | unsigned long lcycle, now, ret; |
0aa366f3 TL |
329 | |
330 | if (!itc_jitter_data.itc_jitter) | |
331 | return get_cycles(); | |
332 | ||
333 | lcycle = itc_jitter_data.itc_lastcycle; | |
334 | now = get_cycles(); | |
335 | if (lcycle && time_after(lcycle, now)) | |
336 | return lcycle; | |
337 | ||
338 | /* | |
339 | * Keep track of the last timer value returned. | |
340 | * In an SMP environment, you could lose out in contention of | |
341 | * cmpxchg. If so, your cmpxchg returns new value which the | |
342 | * winner of contention updated to. Use the new value instead. | |
343 | */ | |
344 | ret = cmpxchg(&itc_jitter_data.itc_lastcycle, lcycle, now); | |
345 | if (unlikely(ret != lcycle)) | |
346 | return ret; | |
347 | ||
348 | return now; | |
349 | } | |
350 | ||
351 | ||
1da177e4 LT |
352 | static struct irqaction timer_irqaction = { |
353 | .handler = timer_interrupt, | |
2958a489 | 354 | .flags = IRQF_IRQPOLL, |
1da177e4 LT |
355 | .name = "timer" |
356 | }; | |
357 | ||
6ffdc577 JS |
358 | void read_persistent_clock(struct timespec *ts) |
359 | { | |
360 | efi_gettimeofday(ts); | |
361 | } | |
362 | ||
1da177e4 LT |
363 | void __init |
364 | time_init (void) | |
365 | { | |
366 | register_percpu_irq(IA64_TIMER_VECTOR, &timer_irqaction); | |
1da177e4 | 367 | ia64_init_itm(); |
1da177e4 | 368 | } |
f5899b5d | 369 | |
defbb2c9 | 370 | /* |
371 | * Generic udelay assumes that if preemption is allowed and the thread | |
372 | * migrates to another CPU, that the ITC values are synchronized across | |
373 | * all CPUs. | |
374 | */ | |
375 | static void | |
376 | ia64_itc_udelay (unsigned long usecs) | |
f5899b5d | 377 | { |
defbb2c9 | 378 | unsigned long start = ia64_get_itc(); |
379 | unsigned long end = start + usecs*local_cpu_data->cyc_per_usec; | |
f5899b5d | 380 | |
defbb2c9 | 381 | while (time_before(ia64_get_itc(), end)) |
382 | cpu_relax(); | |
383 | } | |
f5899b5d | 384 | |
defbb2c9 | 385 | void (*ia64_udelay)(unsigned long usecs) = &ia64_itc_udelay; |
f5899b5d | 386 | |
defbb2c9 | 387 | void |
388 | udelay (unsigned long usecs) | |
389 | { | |
390 | (*ia64_udelay)(usecs); | |
f5899b5d JH |
391 | } |
392 | EXPORT_SYMBOL(udelay); | |
d6e56a2a | 393 | |
2c622148 TB |
394 | /* IA64 doesn't cache the timezone */ |
395 | void update_vsyscall_tz(void) | |
396 | { | |
397 | } | |
398 | ||
70639421 | 399 | void update_vsyscall_old(struct timespec *wall, struct timespec *wtm, |
953dec21 | 400 | struct clocksource *c, u32 mult, cycle_t cycle_last) |
0aa366f3 | 401 | { |
74a622be | 402 | write_seqcount_begin(&fsyscall_gtod_data.seq); |
0aa366f3 TL |
403 | |
404 | /* copy fsyscall clock data */ | |
405 | fsyscall_gtod_data.clk_mask = c->mask; | |
0696b711 | 406 | fsyscall_gtod_data.clk_mult = mult; |
0aa366f3 | 407 | fsyscall_gtod_data.clk_shift = c->shift; |
574c44fa | 408 | fsyscall_gtod_data.clk_fsys_mmio = c->archdata.fsys_mmio; |
4a0e6377 | 409 | fsyscall_gtod_data.clk_cycle_last = cycle_last; |
0aa366f3 TL |
410 | |
411 | /* copy kernel time structures */ | |
412 | fsyscall_gtod_data.wall_time.tv_sec = wall->tv_sec; | |
413 | fsyscall_gtod_data.wall_time.tv_nsec = wall->tv_nsec; | |
7615856e | 414 | fsyscall_gtod_data.monotonic_time.tv_sec = wtm->tv_sec |
0aa366f3 | 415 | + wall->tv_sec; |
7615856e | 416 | fsyscall_gtod_data.monotonic_time.tv_nsec = wtm->tv_nsec |
0aa366f3 TL |
417 | + wall->tv_nsec; |
418 | ||
419 | /* normalize */ | |
420 | while (fsyscall_gtod_data.monotonic_time.tv_nsec >= NSEC_PER_SEC) { | |
421 | fsyscall_gtod_data.monotonic_time.tv_nsec -= NSEC_PER_SEC; | |
422 | fsyscall_gtod_data.monotonic_time.tv_sec++; | |
423 | } | |
424 | ||
74a622be | 425 | write_seqcount_end(&fsyscall_gtod_data.seq); |
0aa366f3 TL |
426 | } |
427 |