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1da177e4 LT |
1 | /* |
2 | * linux/arch/ia64/kernel/time.c | |
3 | * | |
4 | * Copyright (C) 1998-2003 Hewlett-Packard Co | |
5 | * Stephane Eranian <eranian@hpl.hp.com> | |
6 | * David Mosberger <davidm@hpl.hp.com> | |
7 | * Copyright (C) 1999 Don Dugger <don.dugger@intel.com> | |
8 | * Copyright (C) 1999-2000 VA Linux Systems | |
9 | * Copyright (C) 1999-2000 Walt Drummond <drummond@valinux.com> | |
10 | */ | |
1da177e4 LT |
11 | |
12 | #include <linux/cpu.h> | |
13 | #include <linux/init.h> | |
14 | #include <linux/kernel.h> | |
15 | #include <linux/module.h> | |
16 | #include <linux/profile.h> | |
17 | #include <linux/sched.h> | |
18 | #include <linux/time.h> | |
38b8d208 | 19 | #include <linux/nmi.h> |
1da177e4 LT |
20 | #include <linux/interrupt.h> |
21 | #include <linux/efi.h> | |
1da177e4 | 22 | #include <linux/timex.h> |
189374ae | 23 | #include <linux/timekeeper_internal.h> |
5e3fd9e5 | 24 | #include <linux/platform_device.h> |
32ef5517 | 25 | #include <linux/sched/cputime.h> |
1da177e4 LT |
26 | |
27 | #include <asm/machvec.h> | |
28 | #include <asm/delay.h> | |
29 | #include <asm/hw_irq.h> | |
30 | #include <asm/ptrace.h> | |
31 | #include <asm/sal.h> | |
32 | #include <asm/sections.h> | |
1da177e4 | 33 | |
0aa366f3 TL |
34 | #include "fsyscall_gtod_data.h" |
35 | ||
a5a1d1c2 | 36 | static u64 itc_get_cycles(struct clocksource *cs); |
0aa366f3 | 37 | |
74a622be | 38 | struct fsyscall_gtod_data_t fsyscall_gtod_data; |
0aa366f3 TL |
39 | |
40 | struct itc_jitter_data_t itc_jitter_data; | |
41 | ||
ff741906 | 42 | volatile int time_keeper_id = 0; /* smp_processor_id() of time-keeper */ |
1da177e4 LT |
43 | |
44 | #ifdef CONFIG_IA64_DEBUG_IRQ | |
45 | ||
46 | unsigned long last_cli_ip; | |
47 | EXPORT_SYMBOL(last_cli_ip); | |
48 | ||
49 | #endif | |
50 | ||
0aa366f3 | 51 | static struct clocksource clocksource_itc = { |
3eb05676 LZ |
52 | .name = "itc", |
53 | .rating = 350, | |
54 | .read = itc_get_cycles, | |
55 | .mask = CLOCKSOURCE_MASK(64), | |
3eb05676 | 56 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, |
1da177e4 | 57 | }; |
0aa366f3 | 58 | static struct clocksource *itc_clocksource; |
1da177e4 | 59 | |
abf917cd | 60 | #ifdef CONFIG_VIRT_CPU_ACCOUNTING_NATIVE |
b64f34cd HS |
61 | |
62 | #include <linux/kernel_stat.h> | |
63 | ||
e2339a4c | 64 | extern u64 cycle_to_nsec(u64 cyc); |
b64f34cd | 65 | |
c8d7dabf | 66 | void vtime_flush(struct task_struct *tsk) |
5bf412cd | 67 | { |
5bf412cd | 68 | struct thread_info *ti = task_thread_info(tsk); |
fb8b049c | 69 | u64 delta; |
5bf412cd | 70 | |
7dd58230 | 71 | if (ti->utime) |
e2339a4c | 72 | account_user_time(tsk, cycle_to_nsec(ti->utime)); |
7dd58230 FW |
73 | |
74 | if (ti->gtime) | |
e2339a4c | 75 | account_guest_time(tsk, cycle_to_nsec(ti->gtime)); |
7dd58230 FW |
76 | |
77 | if (ti->idle_time) | |
e2339a4c | 78 | account_idle_time(cycle_to_nsec(ti->idle_time)); |
7dd58230 FW |
79 | |
80 | if (ti->stime) { | |
e2339a4c | 81 | delta = cycle_to_nsec(ti->stime); |
7dd58230 FW |
82 | account_system_index_time(tsk, delta, CPUTIME_SYSTEM); |
83 | } | |
84 | ||
85 | if (ti->hardirq_time) { | |
e2339a4c | 86 | delta = cycle_to_nsec(ti->hardirq_time); |
7dd58230 FW |
87 | account_system_index_time(tsk, delta, CPUTIME_IRQ); |
88 | } | |
89 | ||
90 | if (ti->softirq_time) { | |
e2339a4c | 91 | delta = cycle_to_nsec(ti->softirq_time)); |
7dd58230 | 92 | account_system_index_time(tsk, delta, CPUTIME_SOFTIRQ); |
5bf412cd | 93 | } |
7dd58230 FW |
94 | |
95 | ti->utime = 0; | |
96 | ti->gtime = 0; | |
97 | ti->idle_time = 0; | |
98 | ti->stime = 0; | |
99 | ti->hardirq_time = 0; | |
100 | ti->softirq_time = 0; | |
5bf412cd FW |
101 | } |
102 | ||
b64f34cd HS |
103 | /* |
104 | * Called from the context switch with interrupts disabled, to charge all | |
105 | * accumulated times to the current process, and to prepare accounting on | |
106 | * the next process. | |
107 | */ | |
e3942ba0 | 108 | void arch_vtime_task_switch(struct task_struct *prev) |
b64f34cd HS |
109 | { |
110 | struct thread_info *pi = task_thread_info(prev); | |
baa36046 | 111 | struct thread_info *ni = task_thread_info(current); |
b64f34cd | 112 | |
8388d214 | 113 | ni->ac_stamp = pi->ac_stamp; |
b64f34cd HS |
114 | ni->ac_stime = ni->ac_utime = 0; |
115 | } | |
116 | ||
117 | /* | |
118 | * Account time for a transition between system, hard irq or soft irq state. | |
119 | * Note that this function is called with interrupts enabled. | |
120 | */ | |
7dd58230 | 121 | static __u64 vtime_delta(struct task_struct *tsk) |
b64f34cd HS |
122 | { |
123 | struct thread_info *ti = task_thread_info(tsk); | |
7dd58230 | 124 | __u64 now, delta_stime; |
b64f34cd | 125 | |
1b2852b1 FW |
126 | WARN_ON_ONCE(!irqs_disabled()); |
127 | ||
b64f34cd | 128 | now = ia64_get_itc(); |
7dd58230 | 129 | delta_stime = now - ti->ac_stamp; |
b64f34cd HS |
130 | ti->ac_stamp = now; |
131 | ||
a7e1a9e3 FW |
132 | return delta_stime; |
133 | } | |
134 | ||
fd25b4c2 | 135 | void vtime_account_system(struct task_struct *tsk) |
a7e1a9e3 | 136 | { |
7dd58230 FW |
137 | struct thread_info *ti = task_thread_info(tsk); |
138 | __u64 stime = vtime_delta(tsk); | |
139 | ||
140 | if ((tsk->flags & PF_VCPU) && !irq_count()) | |
141 | ti->gtime += stime; | |
142 | else if (hardirq_count()) | |
143 | ti->hardirq_time += stime; | |
144 | else if (in_serving_softirq()) | |
145 | ti->softirq_time += stime; | |
146 | else | |
147 | ti->stime += stime; | |
a7e1a9e3 | 148 | } |
c11f11fc | 149 | EXPORT_SYMBOL_GPL(vtime_account_system); |
a7e1a9e3 | 150 | |
fd25b4c2 | 151 | void vtime_account_idle(struct task_struct *tsk) |
a7e1a9e3 | 152 | { |
7dd58230 FW |
153 | struct thread_info *ti = task_thread_info(tsk); |
154 | ||
155 | ti->idle_time += vtime_delta(tsk); | |
b64f34cd HS |
156 | } |
157 | ||
abf917cd | 158 | #endif /* CONFIG_VIRT_CPU_ACCOUNTING_NATIVE */ |
b64f34cd | 159 | |
1da177e4 | 160 | static irqreturn_t |
7d12e780 | 161 | timer_interrupt (int irq, void *dev_id) |
1da177e4 LT |
162 | { |
163 | unsigned long new_itm; | |
164 | ||
e7d28253 | 165 | if (cpu_is_offline(smp_processor_id())) { |
1da177e4 LT |
166 | return IRQ_HANDLED; |
167 | } | |
168 | ||
7d12e780 | 169 | platform_timer_interrupt(irq, dev_id); |
1da177e4 LT |
170 | |
171 | new_itm = local_cpu_data->itm_next; | |
172 | ||
173 | if (!time_after(ia64_get_itc(), new_itm)) | |
174 | printk(KERN_ERR "Oops: timer tick before it's due (itc=%lx,itm=%lx)\n", | |
175 | ia64_get_itc(), new_itm); | |
176 | ||
7d12e780 | 177 | profile_tick(CPU_PROFILING); |
1da177e4 LT |
178 | |
179 | while (1) { | |
7d12e780 | 180 | update_process_times(user_mode(get_irq_regs())); |
1da177e4 LT |
181 | |
182 | new_itm += local_cpu_data->itm_delta; | |
183 | ||
1aabd67d TH |
184 | if (smp_processor_id() == time_keeper_id) |
185 | xtime_update(1); | |
186 | ||
187 | local_cpu_data->itm_next = new_itm; | |
1da177e4 LT |
188 | |
189 | if (time_after(new_itm, ia64_get_itc())) | |
190 | break; | |
accaddb2 JS |
191 | |
192 | /* | |
193 | * Allow IPIs to interrupt the timer loop. | |
194 | */ | |
195 | local_irq_enable(); | |
196 | local_irq_disable(); | |
1da177e4 LT |
197 | } |
198 | ||
199 | do { | |
200 | /* | |
201 | * If we're too close to the next clock tick for | |
202 | * comfort, we increase the safety margin by | |
203 | * intentionally dropping the next tick(s). We do NOT | |
204 | * update itm.next because that would force us to call | |
1aabd67d | 205 | * xtime_update() which in turn would let our clock run |
1da177e4 LT |
206 | * too fast (with the potentially devastating effect |
207 | * of losing monotony of time). | |
208 | */ | |
209 | while (!time_after(new_itm, ia64_get_itc() + local_cpu_data->itm_delta/2)) | |
210 | new_itm += local_cpu_data->itm_delta; | |
211 | ia64_set_itm(new_itm); | |
212 | /* double check, in case we got hit by a (slow) PMI: */ | |
213 | } while (time_after_eq(ia64_get_itc(), new_itm)); | |
214 | return IRQ_HANDLED; | |
215 | } | |
216 | ||
217 | /* | |
218 | * Encapsulate access to the itm structure for SMP. | |
219 | */ | |
220 | void | |
221 | ia64_cpu_local_tick (void) | |
222 | { | |
223 | int cpu = smp_processor_id(); | |
224 | unsigned long shift = 0, delta; | |
225 | ||
226 | /* arrange for the cycle counter to generate a timer interrupt: */ | |
227 | ia64_set_itv(IA64_TIMER_VECTOR); | |
228 | ||
229 | delta = local_cpu_data->itm_delta; | |
230 | /* | |
231 | * Stagger the timer tick for each CPU so they don't occur all at (almost) the | |
232 | * same time: | |
233 | */ | |
234 | if (cpu) { | |
235 | unsigned long hi = 1UL << ia64_fls(cpu); | |
236 | shift = (2*(cpu - hi) + 1) * delta/hi/2; | |
237 | } | |
238 | local_cpu_data->itm_next = ia64_get_itc() + delta + shift; | |
239 | ia64_set_itm(local_cpu_data->itm_next); | |
240 | } | |
241 | ||
242 | static int nojitter; | |
243 | ||
244 | static int __init nojitter_setup(char *str) | |
245 | { | |
246 | nojitter = 1; | |
247 | printk("Jitter checking for ITC timers disabled\n"); | |
248 | return 1; | |
249 | } | |
250 | ||
251 | __setup("nojitter", nojitter_setup); | |
252 | ||
253 | ||
5b5e76e9 | 254 | void ia64_init_itm(void) |
1da177e4 LT |
255 | { |
256 | unsigned long platform_base_freq, itc_freq; | |
257 | struct pal_freq_ratio itc_ratio, proc_ratio; | |
258 | long status, platform_base_drift, itc_drift; | |
259 | ||
260 | /* | |
261 | * According to SAL v2.6, we need to use a SAL call to determine the platform base | |
262 | * frequency and then a PAL call to determine the frequency ratio between the ITC | |
263 | * and the base frequency. | |
264 | */ | |
265 | status = ia64_sal_freq_base(SAL_FREQ_BASE_PLATFORM, | |
266 | &platform_base_freq, &platform_base_drift); | |
267 | if (status != 0) { | |
268 | printk(KERN_ERR "SAL_FREQ_BASE_PLATFORM failed: %s\n", ia64_sal_strerror(status)); | |
269 | } else { | |
270 | status = ia64_pal_freq_ratios(&proc_ratio, NULL, &itc_ratio); | |
271 | if (status != 0) | |
272 | printk(KERN_ERR "PAL_FREQ_RATIOS failed with status=%ld\n", status); | |
273 | } | |
274 | if (status != 0) { | |
275 | /* invent "random" values */ | |
276 | printk(KERN_ERR | |
277 | "SAL/PAL failed to obtain frequency info---inventing reasonable values\n"); | |
278 | platform_base_freq = 100000000; | |
279 | platform_base_drift = -1; /* no drift info */ | |
280 | itc_ratio.num = 3; | |
281 | itc_ratio.den = 1; | |
282 | } | |
283 | if (platform_base_freq < 40000000) { | |
284 | printk(KERN_ERR "Platform base frequency %lu bogus---resetting to 75MHz!\n", | |
285 | platform_base_freq); | |
286 | platform_base_freq = 75000000; | |
287 | platform_base_drift = -1; | |
288 | } | |
289 | if (!proc_ratio.den) | |
290 | proc_ratio.den = 1; /* avoid division by zero */ | |
291 | if (!itc_ratio.den) | |
292 | itc_ratio.den = 1; /* avoid division by zero */ | |
293 | ||
294 | itc_freq = (platform_base_freq*itc_ratio.num)/itc_ratio.den; | |
295 | ||
296 | local_cpu_data->itm_delta = (itc_freq + HZ/2) / HZ; | |
2ab9391d | 297 | printk(KERN_DEBUG "CPU %d: base freq=%lu.%03luMHz, ITC ratio=%u/%u, " |
1da177e4 LT |
298 | "ITC freq=%lu.%03luMHz", smp_processor_id(), |
299 | platform_base_freq / 1000000, (platform_base_freq / 1000) % 1000, | |
300 | itc_ratio.num, itc_ratio.den, itc_freq / 1000000, (itc_freq / 1000) % 1000); | |
301 | ||
302 | if (platform_base_drift != -1) { | |
303 | itc_drift = platform_base_drift*itc_ratio.num/itc_ratio.den; | |
304 | printk("+/-%ldppm\n", itc_drift); | |
305 | } else { | |
306 | itc_drift = -1; | |
307 | printk("\n"); | |
308 | } | |
309 | ||
310 | local_cpu_data->proc_freq = (platform_base_freq*proc_ratio.num)/proc_ratio.den; | |
311 | local_cpu_data->itc_freq = itc_freq; | |
312 | local_cpu_data->cyc_per_usec = (itc_freq + USEC_PER_SEC/2) / USEC_PER_SEC; | |
313 | local_cpu_data->nsec_per_cyc = ((NSEC_PER_SEC<<IA64_NSEC_PER_CYC_SHIFT) | |
314 | + itc_freq/2)/itc_freq; | |
315 | ||
316 | if (!(sal_platform_features & IA64_SAL_PLATFORM_FEATURE_ITC_DRIFT)) { | |
1da177e4 LT |
317 | #ifdef CONFIG_SMP |
318 | /* On IA64 in an SMP configuration ITCs are never accurately synchronized. | |
319 | * Jitter compensation requires a cmpxchg which may limit | |
320 | * the scalability of the syscalls for retrieving time. | |
321 | * The ITC synchronization is usually successful to within a few | |
322 | * ITC ticks but this is not a sure thing. If you need to improve | |
323 | * timer performance in SMP situations then boot the kernel with the | |
324 | * "nojitter" option. However, doing so may result in time fluctuating (maybe | |
325 | * even going backward) if the ITC offsets between the individual CPUs | |
326 | * are too large. | |
327 | */ | |
0aa366f3 TL |
328 | if (!nojitter) |
329 | itc_jitter_data.itc_jitter = 1; | |
1da177e4 | 330 | #endif |
b718f91c CL |
331 | } else |
332 | /* | |
333 | * ITC is drifty and we have not synchronized the ITCs in smpboot.c. | |
334 | * ITC values may fluctuate significantly between processors. | |
335 | * Clock should not be used for hrtimers. Mark itc as only | |
336 | * useful for boot and testing. | |
337 | * | |
338 | * Note that jitter compensation is off! There is no point of | |
339 | * synchronizing ITCs since they may be large differentials | |
340 | * that change over time. | |
341 | * | |
342 | * The only way to fix this would be to repeatedly sync the | |
343 | * ITCs. Until that time we have to avoid ITC. | |
344 | */ | |
345 | clocksource_itc.rating = 50; | |
1da177e4 | 346 | |
00d21d82 IY |
347 | /* avoid softlock up message when cpu is unplug and plugged again. */ |
348 | touch_softlockup_watchdog(); | |
349 | ||
1da177e4 LT |
350 | /* Setup the CPU local timer tick */ |
351 | ia64_cpu_local_tick(); | |
0aa366f3 TL |
352 | |
353 | if (!itc_clocksource) { | |
d60c3041 JS |
354 | clocksource_register_hz(&clocksource_itc, |
355 | local_cpu_data->itc_freq); | |
0aa366f3 TL |
356 | itc_clocksource = &clocksource_itc; |
357 | } | |
1da177e4 LT |
358 | } |
359 | ||
a5a1d1c2 | 360 | static u64 itc_get_cycles(struct clocksource *cs) |
0aa366f3 | 361 | { |
e088a4ad | 362 | unsigned long lcycle, now, ret; |
0aa366f3 TL |
363 | |
364 | if (!itc_jitter_data.itc_jitter) | |
365 | return get_cycles(); | |
366 | ||
367 | lcycle = itc_jitter_data.itc_lastcycle; | |
368 | now = get_cycles(); | |
369 | if (lcycle && time_after(lcycle, now)) | |
370 | return lcycle; | |
371 | ||
372 | /* | |
373 | * Keep track of the last timer value returned. | |
374 | * In an SMP environment, you could lose out in contention of | |
375 | * cmpxchg. If so, your cmpxchg returns new value which the | |
376 | * winner of contention updated to. Use the new value instead. | |
377 | */ | |
378 | ret = cmpxchg(&itc_jitter_data.itc_lastcycle, lcycle, now); | |
379 | if (unlikely(ret != lcycle)) | |
380 | return ret; | |
381 | ||
382 | return now; | |
383 | } | |
384 | ||
385 | ||
1da177e4 LT |
386 | static struct irqaction timer_irqaction = { |
387 | .handler = timer_interrupt, | |
2958a489 | 388 | .flags = IRQF_IRQPOLL, |
1da177e4 LT |
389 | .name = "timer" |
390 | }; | |
391 | ||
70f4f935 | 392 | void read_persistent_clock64(struct timespec64 *ts) |
6ffdc577 JS |
393 | { |
394 | efi_gettimeofday(ts); | |
395 | } | |
396 | ||
1da177e4 LT |
397 | void __init |
398 | time_init (void) | |
399 | { | |
400 | register_percpu_irq(IA64_TIMER_VECTOR, &timer_irqaction); | |
1da177e4 | 401 | ia64_init_itm(); |
1da177e4 | 402 | } |
f5899b5d | 403 | |
defbb2c9 | 404 | /* |
405 | * Generic udelay assumes that if preemption is allowed and the thread | |
406 | * migrates to another CPU, that the ITC values are synchronized across | |
407 | * all CPUs. | |
408 | */ | |
409 | static void | |
410 | ia64_itc_udelay (unsigned long usecs) | |
f5899b5d | 411 | { |
defbb2c9 | 412 | unsigned long start = ia64_get_itc(); |
413 | unsigned long end = start + usecs*local_cpu_data->cyc_per_usec; | |
f5899b5d | 414 | |
defbb2c9 | 415 | while (time_before(ia64_get_itc(), end)) |
416 | cpu_relax(); | |
417 | } | |
f5899b5d | 418 | |
defbb2c9 | 419 | void (*ia64_udelay)(unsigned long usecs) = &ia64_itc_udelay; |
f5899b5d | 420 | |
defbb2c9 | 421 | void |
422 | udelay (unsigned long usecs) | |
423 | { | |
424 | (*ia64_udelay)(usecs); | |
f5899b5d JH |
425 | } |
426 | EXPORT_SYMBOL(udelay); | |
d6e56a2a | 427 | |
2c622148 TB |
428 | /* IA64 doesn't cache the timezone */ |
429 | void update_vsyscall_tz(void) | |
430 | { | |
431 | } | |
432 | ||
70639421 | 433 | void update_vsyscall_old(struct timespec *wall, struct timespec *wtm, |
a5a1d1c2 | 434 | struct clocksource *c, u32 mult, u64 cycle_last) |
0aa366f3 | 435 | { |
74a622be | 436 | write_seqcount_begin(&fsyscall_gtod_data.seq); |
0aa366f3 TL |
437 | |
438 | /* copy fsyscall clock data */ | |
439 | fsyscall_gtod_data.clk_mask = c->mask; | |
0696b711 | 440 | fsyscall_gtod_data.clk_mult = mult; |
0aa366f3 | 441 | fsyscall_gtod_data.clk_shift = c->shift; |
574c44fa | 442 | fsyscall_gtod_data.clk_fsys_mmio = c->archdata.fsys_mmio; |
4a0e6377 | 443 | fsyscall_gtod_data.clk_cycle_last = cycle_last; |
0aa366f3 TL |
444 | |
445 | /* copy kernel time structures */ | |
446 | fsyscall_gtod_data.wall_time.tv_sec = wall->tv_sec; | |
447 | fsyscall_gtod_data.wall_time.tv_nsec = wall->tv_nsec; | |
7615856e | 448 | fsyscall_gtod_data.monotonic_time.tv_sec = wtm->tv_sec |
0aa366f3 | 449 | + wall->tv_sec; |
7615856e | 450 | fsyscall_gtod_data.monotonic_time.tv_nsec = wtm->tv_nsec |
0aa366f3 TL |
451 | + wall->tv_nsec; |
452 | ||
453 | /* normalize */ | |
454 | while (fsyscall_gtod_data.monotonic_time.tv_nsec >= NSEC_PER_SEC) { | |
455 | fsyscall_gtod_data.monotonic_time.tv_nsec -= NSEC_PER_SEC; | |
456 | fsyscall_gtod_data.monotonic_time.tv_sec++; | |
457 | } | |
458 | ||
74a622be | 459 | write_seqcount_end(&fsyscall_gtod_data.seq); |
0aa366f3 TL |
460 | } |
461 |