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a4f50038 XZ |
1 | /* |
2 | * vcpu.h: vcpu routines | |
3 | * Copyright (c) 2005, Intel Corporation. | |
4 | * Xuefei Xu (Anthony Xu) (Anthony.xu@intel.com) | |
5 | * Yaozu Dong (Eddie Dong) (Eddie.dong@intel.com) | |
6 | * | |
7 | * Copyright (c) 2007, Intel Corporation. | |
8 | * Xuefei Xu (Anthony Xu) (Anthony.xu@intel.com) | |
9 | * Xiantao Zhang (xiantao.zhang@intel.com) | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify it | |
12 | * under the terms and conditions of the GNU General Public License, | |
13 | * version 2, as published by the Free Software Foundation. | |
14 | * | |
15 | * This program is distributed in the hope it will be useful, but WITHOUT | |
16 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
17 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
18 | * more details. | |
19 | * | |
20 | * You should have received a copy of the GNU General Public License along with | |
21 | * this program; if not, write to the Free Software Foundation, Inc., 59 Temple | |
22 | * Place - Suite 330, Boston, MA 02111-1307 USA. | |
23 | * | |
24 | */ | |
25 | ||
26 | ||
27 | #ifndef __KVM_VCPU_H__ | |
28 | #define __KVM_VCPU_H__ | |
29 | ||
30 | #include <asm/types.h> | |
31 | #include <asm/fpu.h> | |
32 | #include <asm/processor.h> | |
33 | ||
34 | #ifndef __ASSEMBLY__ | |
35 | #include "vti.h" | |
36 | ||
37 | #include <linux/kvm_host.h> | |
38 | #include <linux/spinlock.h> | |
39 | ||
40 | typedef unsigned long IA64_INST; | |
41 | ||
42 | typedef union U_IA64_BUNDLE { | |
43 | unsigned long i64[2]; | |
44 | struct { unsigned long template:5, slot0:41, slot1a:18, | |
45 | slot1b:23, slot2:41; }; | |
46 | /* NOTE: following doesn't work because bitfields can't cross natural | |
47 | size boundaries | |
48 | struct { unsigned long template:5, slot0:41, slot1:41, slot2:41; }; */ | |
49 | } IA64_BUNDLE; | |
50 | ||
51 | typedef union U_INST64_A5 { | |
52 | IA64_INST inst; | |
53 | struct { unsigned long qp:6, r1:7, imm7b:7, r3:2, imm5c:5, | |
54 | imm9d:9, s:1, major:4; }; | |
55 | } INST64_A5; | |
56 | ||
57 | typedef union U_INST64_B4 { | |
58 | IA64_INST inst; | |
59 | struct { unsigned long qp:6, btype:3, un3:3, p:1, b2:3, un11:11, x6:6, | |
60 | wh:2, d:1, un1:1, major:4; }; | |
61 | } INST64_B4; | |
62 | ||
63 | typedef union U_INST64_B8 { | |
64 | IA64_INST inst; | |
65 | struct { unsigned long qp:6, un21:21, x6:6, un4:4, major:4; }; | |
66 | } INST64_B8; | |
67 | ||
68 | typedef union U_INST64_B9 { | |
69 | IA64_INST inst; | |
70 | struct { unsigned long qp:6, imm20:20, :1, x6:6, :3, i:1, major:4; }; | |
71 | } INST64_B9; | |
72 | ||
73 | typedef union U_INST64_I19 { | |
74 | IA64_INST inst; | |
75 | struct { unsigned long qp:6, imm20:20, :1, x6:6, x3:3, i:1, major:4; }; | |
76 | } INST64_I19; | |
77 | ||
78 | typedef union U_INST64_I26 { | |
79 | IA64_INST inst; | |
80 | struct { unsigned long qp:6, :7, r2:7, ar3:7, x6:6, x3:3, :1, major:4; }; | |
81 | } INST64_I26; | |
82 | ||
83 | typedef union U_INST64_I27 { | |
84 | IA64_INST inst; | |
85 | struct { unsigned long qp:6, :7, imm:7, ar3:7, x6:6, x3:3, s:1, major:4; }; | |
86 | } INST64_I27; | |
87 | ||
88 | typedef union U_INST64_I28 { /* not privileged (mov from AR) */ | |
89 | IA64_INST inst; | |
90 | struct { unsigned long qp:6, r1:7, :7, ar3:7, x6:6, x3:3, :1, major:4; }; | |
91 | } INST64_I28; | |
92 | ||
93 | typedef union U_INST64_M28 { | |
94 | IA64_INST inst; | |
95 | struct { unsigned long qp:6, :14, r3:7, x6:6, x3:3, :1, major:4; }; | |
96 | } INST64_M28; | |
97 | ||
98 | typedef union U_INST64_M29 { | |
99 | IA64_INST inst; | |
100 | struct { unsigned long qp:6, :7, r2:7, ar3:7, x6:6, x3:3, :1, major:4; }; | |
101 | } INST64_M29; | |
102 | ||
103 | typedef union U_INST64_M30 { | |
104 | IA64_INST inst; | |
105 | struct { unsigned long qp:6, :7, imm:7, ar3:7, x4:4, x2:2, | |
106 | x3:3, s:1, major:4; }; | |
107 | } INST64_M30; | |
108 | ||
109 | typedef union U_INST64_M31 { | |
110 | IA64_INST inst; | |
111 | struct { unsigned long qp:6, r1:7, :7, ar3:7, x6:6, x3:3, :1, major:4; }; | |
112 | } INST64_M31; | |
113 | ||
114 | typedef union U_INST64_M32 { | |
115 | IA64_INST inst; | |
116 | struct { unsigned long qp:6, :7, r2:7, cr3:7, x6:6, x3:3, :1, major:4; }; | |
117 | } INST64_M32; | |
118 | ||
119 | typedef union U_INST64_M33 { | |
120 | IA64_INST inst; | |
121 | struct { unsigned long qp:6, r1:7, :7, cr3:7, x6:6, x3:3, :1, major:4; }; | |
122 | } INST64_M33; | |
123 | ||
124 | typedef union U_INST64_M35 { | |
125 | IA64_INST inst; | |
126 | struct { unsigned long qp:6, :7, r2:7, :7, x6:6, x3:3, :1, major:4; }; | |
127 | ||
128 | } INST64_M35; | |
129 | ||
130 | typedef union U_INST64_M36 { | |
131 | IA64_INST inst; | |
132 | struct { unsigned long qp:6, r1:7, :14, x6:6, x3:3, :1, major:4; }; | |
133 | } INST64_M36; | |
134 | ||
135 | typedef union U_INST64_M37 { | |
136 | IA64_INST inst; | |
137 | struct { unsigned long qp:6, imm20a:20, :1, x4:4, x2:2, x3:3, | |
138 | i:1, major:4; }; | |
139 | } INST64_M37; | |
140 | ||
141 | typedef union U_INST64_M41 { | |
142 | IA64_INST inst; | |
143 | struct { unsigned long qp:6, :7, r2:7, :7, x6:6, x3:3, :1, major:4; }; | |
144 | } INST64_M41; | |
145 | ||
146 | typedef union U_INST64_M42 { | |
147 | IA64_INST inst; | |
148 | struct { unsigned long qp:6, :7, r2:7, r3:7, x6:6, x3:3, :1, major:4; }; | |
149 | } INST64_M42; | |
150 | ||
151 | typedef union U_INST64_M43 { | |
152 | IA64_INST inst; | |
153 | struct { unsigned long qp:6, r1:7, :7, r3:7, x6:6, x3:3, :1, major:4; }; | |
154 | } INST64_M43; | |
155 | ||
156 | typedef union U_INST64_M44 { | |
157 | IA64_INST inst; | |
158 | struct { unsigned long qp:6, imm:21, x4:4, i2:2, x3:3, i:1, major:4; }; | |
159 | } INST64_M44; | |
160 | ||
161 | typedef union U_INST64_M45 { | |
162 | IA64_INST inst; | |
163 | struct { unsigned long qp:6, :7, r2:7, r3:7, x6:6, x3:3, :1, major:4; }; | |
164 | } INST64_M45; | |
165 | ||
166 | typedef union U_INST64_M46 { | |
167 | IA64_INST inst; | |
168 | struct { unsigned long qp:6, r1:7, un7:7, r3:7, x6:6, | |
169 | x3:3, un1:1, major:4; }; | |
170 | } INST64_M46; | |
171 | ||
172 | typedef union U_INST64_M47 { | |
173 | IA64_INST inst; | |
174 | struct { unsigned long qp:6, un14:14, r3:7, x6:6, x3:3, un1:1, major:4; }; | |
175 | } INST64_M47; | |
176 | ||
177 | typedef union U_INST64_M1{ | |
178 | IA64_INST inst; | |
179 | struct { unsigned long qp:6, r1:7, un7:7, r3:7, x:1, hint:2, | |
180 | x6:6, m:1, major:4; }; | |
181 | } INST64_M1; | |
182 | ||
183 | typedef union U_INST64_M2{ | |
184 | IA64_INST inst; | |
185 | struct { unsigned long qp:6, r1:7, r2:7, r3:7, x:1, hint:2, | |
186 | x6:6, m:1, major:4; }; | |
187 | } INST64_M2; | |
188 | ||
189 | typedef union U_INST64_M3{ | |
190 | IA64_INST inst; | |
191 | struct { unsigned long qp:6, r1:7, imm7:7, r3:7, i:1, hint:2, | |
192 | x6:6, s:1, major:4; }; | |
193 | } INST64_M3; | |
194 | ||
195 | typedef union U_INST64_M4 { | |
196 | IA64_INST inst; | |
197 | struct { unsigned long qp:6, un7:7, r2:7, r3:7, x:1, hint:2, | |
198 | x6:6, m:1, major:4; }; | |
199 | } INST64_M4; | |
200 | ||
201 | typedef union U_INST64_M5 { | |
202 | IA64_INST inst; | |
203 | struct { unsigned long qp:6, imm7:7, r2:7, r3:7, i:1, hint:2, | |
204 | x6:6, s:1, major:4; }; | |
205 | } INST64_M5; | |
206 | ||
207 | typedef union U_INST64_M6 { | |
208 | IA64_INST inst; | |
209 | struct { unsigned long qp:6, f1:7, un7:7, r3:7, x:1, hint:2, | |
210 | x6:6, m:1, major:4; }; | |
211 | } INST64_M6; | |
212 | ||
213 | typedef union U_INST64_M9 { | |
214 | IA64_INST inst; | |
215 | struct { unsigned long qp:6, :7, f2:7, r3:7, x:1, hint:2, | |
216 | x6:6, m:1, major:4; }; | |
217 | } INST64_M9; | |
218 | ||
219 | typedef union U_INST64_M10 { | |
220 | IA64_INST inst; | |
221 | struct { unsigned long qp:6, imm7:7, f2:7, r3:7, i:1, hint:2, | |
222 | x6:6, s:1, major:4; }; | |
223 | } INST64_M10; | |
224 | ||
225 | typedef union U_INST64_M12 { | |
226 | IA64_INST inst; | |
227 | struct { unsigned long qp:6, f1:7, f2:7, r3:7, x:1, hint:2, | |
228 | x6:6, m:1, major:4; }; | |
229 | } INST64_M12; | |
230 | ||
231 | typedef union U_INST64_M15 { | |
232 | IA64_INST inst; | |
233 | struct { unsigned long qp:6, :7, imm7:7, r3:7, i:1, hint:2, | |
234 | x6:6, s:1, major:4; }; | |
235 | } INST64_M15; | |
236 | ||
237 | typedef union U_INST64 { | |
238 | IA64_INST inst; | |
239 | struct { unsigned long :37, major:4; } generic; | |
240 | INST64_A5 A5; /* used in build_hypercall_bundle only */ | |
241 | INST64_B4 B4; /* used in build_hypercall_bundle only */ | |
242 | INST64_B8 B8; /* rfi, bsw.[01] */ | |
243 | INST64_B9 B9; /* break.b */ | |
244 | INST64_I19 I19; /* used in build_hypercall_bundle only */ | |
245 | INST64_I26 I26; /* mov register to ar (I unit) */ | |
246 | INST64_I27 I27; /* mov immediate to ar (I unit) */ | |
247 | INST64_I28 I28; /* mov from ar (I unit) */ | |
248 | INST64_M1 M1; /* ld integer */ | |
249 | INST64_M2 M2; | |
250 | INST64_M3 M3; | |
251 | INST64_M4 M4; /* st integer */ | |
252 | INST64_M5 M5; | |
253 | INST64_M6 M6; /* ldfd floating pointer */ | |
254 | INST64_M9 M9; /* stfd floating pointer */ | |
255 | INST64_M10 M10; /* stfd floating pointer */ | |
256 | INST64_M12 M12; /* ldfd pair floating pointer */ | |
257 | INST64_M15 M15; /* lfetch + imm update */ | |
258 | INST64_M28 M28; /* purge translation cache entry */ | |
259 | INST64_M29 M29; /* mov register to ar (M unit) */ | |
260 | INST64_M30 M30; /* mov immediate to ar (M unit) */ | |
261 | INST64_M31 M31; /* mov from ar (M unit) */ | |
262 | INST64_M32 M32; /* mov reg to cr */ | |
263 | INST64_M33 M33; /* mov from cr */ | |
264 | INST64_M35 M35; /* mov to psr */ | |
265 | INST64_M36 M36; /* mov from psr */ | |
266 | INST64_M37 M37; /* break.m */ | |
267 | INST64_M41 M41; /* translation cache insert */ | |
268 | INST64_M42 M42; /* mov to indirect reg/translation reg insert*/ | |
269 | INST64_M43 M43; /* mov from indirect reg */ | |
270 | INST64_M44 M44; /* set/reset system mask */ | |
271 | INST64_M45 M45; /* translation purge */ | |
272 | INST64_M46 M46; /* translation access (tpa,tak) */ | |
273 | INST64_M47 M47; /* purge translation entry */ | |
274 | } INST64; | |
275 | ||
276 | #define MASK_41 ((unsigned long)0x1ffffffffff) | |
277 | ||
278 | /* Virtual address memory attributes encoding */ | |
279 | #define VA_MATTR_WB 0x0 | |
280 | #define VA_MATTR_UC 0x4 | |
281 | #define VA_MATTR_UCE 0x5 | |
282 | #define VA_MATTR_WC 0x6 | |
283 | #define VA_MATTR_NATPAGE 0x7 | |
284 | ||
285 | #define PMASK(size) (~((size) - 1)) | |
286 | #define PSIZE(size) (1UL<<(size)) | |
287 | #define CLEARLSB(ppn, nbits) (((ppn) >> (nbits)) << (nbits)) | |
288 | #define PAGEALIGN(va, ps) CLEARLSB(va, ps) | |
289 | #define PAGE_FLAGS_RV_MASK (0x2|(0x3UL<<50)|(((1UL<<11)-1)<<53)) | |
290 | #define _PAGE_MA_ST (0x1 << 2) /* is reserved for software use */ | |
291 | ||
292 | #define ARCH_PAGE_SHIFT 12 | |
293 | ||
294 | #define INVALID_TI_TAG (1UL << 63) | |
295 | ||
296 | #define VTLB_PTE_P_BIT 0 | |
297 | #define VTLB_PTE_IO_BIT 60 | |
298 | #define VTLB_PTE_IO (1UL<<VTLB_PTE_IO_BIT) | |
299 | #define VTLB_PTE_P (1UL<<VTLB_PTE_P_BIT) | |
300 | ||
301 | #define vcpu_quick_region_check(_tr_regions,_ifa) \ | |
302 | (_tr_regions & (1 << ((unsigned long)_ifa >> 61))) | |
303 | ||
304 | #define vcpu_quick_region_set(_tr_regions,_ifa) \ | |
305 | do {_tr_regions |= (1 << ((unsigned long)_ifa >> 61)); } while (0) | |
306 | ||
307 | static inline void vcpu_set_tr(struct thash_data *trp, u64 pte, u64 itir, | |
308 | u64 va, u64 rid) | |
309 | { | |
310 | trp->page_flags = pte; | |
311 | trp->itir = itir; | |
312 | trp->vadr = va; | |
313 | trp->rid = rid; | |
314 | } | |
315 | ||
b010eb51 | 316 | extern u64 kvm_get_mpt_entry(u64 gpfn); |
a4f50038 | 317 | |
b010eb51 XZ |
318 | /* Return I/ */ |
319 | static inline u64 __gpfn_is_io(u64 gpfn) | |
320 | { | |
321 | u64 pte; | |
322 | pte = kvm_get_mpt_entry(gpfn); | |
323 | if (!(pte & GPFN_INV_MASK)) { | |
324 | pte = pte & GPFN_IO_MASK; | |
325 | if (pte != GPFN_PHYS_MMIO) | |
326 | return pte; | |
327 | } | |
328 | return 0; | |
329 | } | |
a4f50038 | 330 | #endif |
a4f50038 XZ |
331 | #define IA64_NO_FAULT 0 |
332 | #define IA64_FAULT 1 | |
333 | ||
334 | #define VMM_RBS_OFFSET ((VMM_TASK_SIZE + 15) & ~15) | |
335 | ||
336 | #define SW_BAD 0 /* Bad mode transitition */ | |
337 | #define SW_V2P 1 /* Physical emulatino is activated */ | |
338 | #define SW_P2V 2 /* Exit physical mode emulation */ | |
339 | #define SW_SELF 3 /* No mode transition */ | |
340 | #define SW_NOP 4 /* Mode transition, but without action required */ | |
341 | ||
342 | #define GUEST_IN_PHY 0x1 | |
343 | #define GUEST_PHY_EMUL 0x2 | |
344 | ||
345 | #define current_vcpu ((struct kvm_vcpu *) ia64_getreg(_IA64_REG_TP)) | |
346 | ||
347 | #define VRN_SHIFT 61 | |
348 | #define VRN_MASK 0xe000000000000000 | |
349 | #define VRN0 0x0UL | |
350 | #define VRN1 0x1UL | |
351 | #define VRN2 0x2UL | |
352 | #define VRN3 0x3UL | |
353 | #define VRN4 0x4UL | |
354 | #define VRN5 0x5UL | |
355 | #define VRN6 0x6UL | |
356 | #define VRN7 0x7UL | |
357 | ||
358 | #define IRQ_NO_MASKED 0 | |
359 | #define IRQ_MASKED_BY_VTPR 1 | |
360 | #define IRQ_MASKED_BY_INSVC 2 /* masked by inservice IRQ */ | |
361 | ||
362 | #define PTA_BASE_SHIFT 15 | |
363 | ||
364 | #define IA64_PSR_VM_BIT 46 | |
365 | #define IA64_PSR_VM (__IA64_UL(1) << IA64_PSR_VM_BIT) | |
366 | ||
367 | /* Interruption Function State */ | |
368 | #define IA64_IFS_V_BIT 63 | |
369 | #define IA64_IFS_V (__IA64_UL(1) << IA64_IFS_V_BIT) | |
370 | ||
371 | #define PHY_PAGE_UC (_PAGE_A|_PAGE_D|_PAGE_P|_PAGE_MA_UC|_PAGE_AR_RWX) | |
372 | #define PHY_PAGE_WB (_PAGE_A|_PAGE_D|_PAGE_P|_PAGE_MA_WB|_PAGE_AR_RWX) | |
373 | ||
374 | #ifndef __ASSEMBLY__ | |
375 | ||
376 | #include <asm/gcc_intrin.h> | |
377 | ||
378 | #define is_physical_mode(v) \ | |
379 | ((v->arch.mode_flags) & GUEST_IN_PHY) | |
380 | ||
381 | #define is_virtual_mode(v) \ | |
382 | (!is_physical_mode(v)) | |
383 | ||
384 | #define MODE_IND(psr) \ | |
385 | (((psr).it << 2) + ((psr).dt << 1) + (psr).rt) | |
386 | ||
c60ff51e XZ |
387 | #ifndef CONFIG_SMP |
388 | #define _vmm_raw_spin_lock(x) do {}while(0) | |
389 | #define _vmm_raw_spin_unlock(x) do {}while(0) | |
390 | #else | |
a4f50038 XZ |
391 | #define _vmm_raw_spin_lock(x) \ |
392 | do { \ | |
393 | __u32 *ia64_spinlock_ptr = (__u32 *) (x); \ | |
394 | __u64 ia64_spinlock_val; \ | |
395 | ia64_spinlock_val = ia64_cmpxchg4_acq(ia64_spinlock_ptr, 1, 0);\ | |
396 | if (unlikely(ia64_spinlock_val)) { \ | |
397 | do { \ | |
398 | while (*ia64_spinlock_ptr) \ | |
399 | ia64_barrier(); \ | |
400 | ia64_spinlock_val = \ | |
401 | ia64_cmpxchg4_acq(ia64_spinlock_ptr, 1, 0);\ | |
402 | } while (ia64_spinlock_val); \ | |
403 | } \ | |
404 | } while (0) | |
405 | ||
406 | #define _vmm_raw_spin_unlock(x) \ | |
407 | do { barrier(); \ | |
408 | ((spinlock_t *)x)->raw_lock.lock = 0; } \ | |
409 | while (0) | |
c60ff51e | 410 | #endif |
a4f50038 XZ |
411 | |
412 | void vmm_spin_lock(spinlock_t *lock); | |
413 | void vmm_spin_unlock(spinlock_t *lock); | |
414 | enum { | |
415 | I_TLB = 1, | |
416 | D_TLB = 2 | |
417 | }; | |
418 | ||
419 | union kvm_va { | |
420 | struct { | |
421 | unsigned long off : 60; /* intra-region offset */ | |
422 | unsigned long reg : 4; /* region number */ | |
423 | } f; | |
424 | unsigned long l; | |
425 | void *p; | |
426 | }; | |
427 | ||
428 | #define __kvm_pa(x) ({union kvm_va _v; _v.l = (long) (x); \ | |
429 | _v.f.reg = 0; _v.l; }) | |
430 | #define __kvm_va(x) ({union kvm_va _v; _v.l = (long) (x); \ | |
431 | _v.f.reg = -1; _v.p; }) | |
432 | ||
433 | #define _REGION_ID(x) ({union ia64_rr _v; _v.val = (long)(x); \ | |
434 | _v.rid; }) | |
435 | #define _REGION_PAGE_SIZE(x) ({union ia64_rr _v; _v.val = (long)(x); \ | |
436 | _v.ps; }) | |
437 | #define _REGION_HW_WALKER(x) ({union ia64_rr _v; _v.val = (long)(x); \ | |
438 | _v.ve; }) | |
439 | ||
440 | enum vhpt_ref{ DATA_REF, NA_REF, INST_REF, RSE_REF }; | |
441 | enum tlb_miss_type { INSTRUCTION, DATA, REGISTER }; | |
442 | ||
443 | #define VCPU(_v, _x) ((_v)->arch.vpd->_x) | |
444 | #define VMX(_v, _x) ((_v)->arch._x) | |
445 | ||
446 | #define VLSAPIC_INSVC(vcpu, i) ((vcpu)->arch.insvc[i]) | |
447 | #define VLSAPIC_XTP(_v) VMX(_v, xtp) | |
448 | ||
449 | static inline unsigned long itir_ps(unsigned long itir) | |
450 | { | |
451 | return ((itir >> 2) & 0x3f); | |
452 | } | |
453 | ||
454 | ||
455 | /************************************************************************** | |
456 | VCPU control register access routines | |
457 | **************************************************************************/ | |
458 | ||
459 | static inline u64 vcpu_get_itir(struct kvm_vcpu *vcpu) | |
460 | { | |
461 | return ((u64)VCPU(vcpu, itir)); | |
462 | } | |
463 | ||
464 | static inline void vcpu_set_itir(struct kvm_vcpu *vcpu, u64 val) | |
465 | { | |
466 | VCPU(vcpu, itir) = val; | |
467 | } | |
468 | ||
469 | static inline u64 vcpu_get_ifa(struct kvm_vcpu *vcpu) | |
470 | { | |
471 | return ((u64)VCPU(vcpu, ifa)); | |
472 | } | |
473 | ||
474 | static inline void vcpu_set_ifa(struct kvm_vcpu *vcpu, u64 val) | |
475 | { | |
476 | VCPU(vcpu, ifa) = val; | |
477 | } | |
478 | ||
479 | static inline u64 vcpu_get_iva(struct kvm_vcpu *vcpu) | |
480 | { | |
481 | return ((u64)VCPU(vcpu, iva)); | |
482 | } | |
483 | ||
484 | static inline u64 vcpu_get_pta(struct kvm_vcpu *vcpu) | |
485 | { | |
486 | return ((u64)VCPU(vcpu, pta)); | |
487 | } | |
488 | ||
489 | static inline u64 vcpu_get_lid(struct kvm_vcpu *vcpu) | |
490 | { | |
491 | return ((u64)VCPU(vcpu, lid)); | |
492 | } | |
493 | ||
494 | static inline u64 vcpu_get_tpr(struct kvm_vcpu *vcpu) | |
495 | { | |
496 | return ((u64)VCPU(vcpu, tpr)); | |
497 | } | |
498 | ||
499 | static inline u64 vcpu_get_eoi(struct kvm_vcpu *vcpu) | |
500 | { | |
501 | return (0UL); /*reads of eoi always return 0 */ | |
502 | } | |
503 | ||
504 | static inline u64 vcpu_get_irr0(struct kvm_vcpu *vcpu) | |
505 | { | |
506 | return ((u64)VCPU(vcpu, irr[0])); | |
507 | } | |
508 | ||
509 | static inline u64 vcpu_get_irr1(struct kvm_vcpu *vcpu) | |
510 | { | |
511 | return ((u64)VCPU(vcpu, irr[1])); | |
512 | } | |
513 | ||
514 | static inline u64 vcpu_get_irr2(struct kvm_vcpu *vcpu) | |
515 | { | |
516 | return ((u64)VCPU(vcpu, irr[2])); | |
517 | } | |
518 | ||
519 | static inline u64 vcpu_get_irr3(struct kvm_vcpu *vcpu) | |
520 | { | |
521 | return ((u64)VCPU(vcpu, irr[3])); | |
522 | } | |
523 | ||
524 | static inline void vcpu_set_dcr(struct kvm_vcpu *vcpu, u64 val) | |
525 | { | |
526 | ia64_setreg(_IA64_REG_CR_DCR, val); | |
527 | } | |
528 | ||
529 | static inline void vcpu_set_isr(struct kvm_vcpu *vcpu, u64 val) | |
530 | { | |
531 | VCPU(vcpu, isr) = val; | |
532 | } | |
533 | ||
534 | static inline void vcpu_set_lid(struct kvm_vcpu *vcpu, u64 val) | |
535 | { | |
536 | VCPU(vcpu, lid) = val; | |
537 | } | |
538 | ||
539 | static inline void vcpu_set_ipsr(struct kvm_vcpu *vcpu, u64 val) | |
540 | { | |
541 | VCPU(vcpu, ipsr) = val; | |
542 | } | |
543 | ||
544 | static inline void vcpu_set_iip(struct kvm_vcpu *vcpu, u64 val) | |
545 | { | |
546 | VCPU(vcpu, iip) = val; | |
547 | } | |
548 | ||
549 | static inline void vcpu_set_ifs(struct kvm_vcpu *vcpu, u64 val) | |
550 | { | |
551 | VCPU(vcpu, ifs) = val; | |
552 | } | |
553 | ||
554 | static inline void vcpu_set_iipa(struct kvm_vcpu *vcpu, u64 val) | |
555 | { | |
556 | VCPU(vcpu, iipa) = val; | |
557 | } | |
558 | ||
559 | static inline void vcpu_set_iha(struct kvm_vcpu *vcpu, u64 val) | |
560 | { | |
561 | VCPU(vcpu, iha) = val; | |
562 | } | |
563 | ||
564 | ||
565 | static inline u64 vcpu_get_rr(struct kvm_vcpu *vcpu, u64 reg) | |
566 | { | |
567 | return vcpu->arch.vrr[reg>>61]; | |
568 | } | |
569 | ||
570 | /************************************************************************** | |
571 | VCPU debug breakpoint register access routines | |
572 | **************************************************************************/ | |
573 | ||
574 | static inline void vcpu_set_dbr(struct kvm_vcpu *vcpu, u64 reg, u64 val) | |
575 | { | |
576 | __ia64_set_dbr(reg, val); | |
577 | } | |
578 | ||
579 | static inline void vcpu_set_ibr(struct kvm_vcpu *vcpu, u64 reg, u64 val) | |
580 | { | |
581 | ia64_set_ibr(reg, val); | |
582 | } | |
583 | ||
584 | static inline u64 vcpu_get_dbr(struct kvm_vcpu *vcpu, u64 reg) | |
585 | { | |
586 | return ((u64)__ia64_get_dbr(reg)); | |
587 | } | |
588 | ||
589 | static inline u64 vcpu_get_ibr(struct kvm_vcpu *vcpu, u64 reg) | |
590 | { | |
591 | return ((u64)ia64_get_ibr(reg)); | |
592 | } | |
593 | ||
594 | /************************************************************************** | |
595 | VCPU performance monitor register access routines | |
596 | **************************************************************************/ | |
597 | static inline void vcpu_set_pmc(struct kvm_vcpu *vcpu, u64 reg, u64 val) | |
598 | { | |
599 | /* NOTE: Writes to unimplemented PMC registers are discarded */ | |
600 | ia64_set_pmc(reg, val); | |
601 | } | |
602 | ||
603 | static inline void vcpu_set_pmd(struct kvm_vcpu *vcpu, u64 reg, u64 val) | |
604 | { | |
605 | /* NOTE: Writes to unimplemented PMD registers are discarded */ | |
606 | ia64_set_pmd(reg, val); | |
607 | } | |
608 | ||
609 | static inline u64 vcpu_get_pmc(struct kvm_vcpu *vcpu, u64 reg) | |
610 | { | |
611 | /* NOTE: Reads from unimplemented PMC registers return zero */ | |
612 | return ((u64)ia64_get_pmc(reg)); | |
613 | } | |
614 | ||
615 | static inline u64 vcpu_get_pmd(struct kvm_vcpu *vcpu, u64 reg) | |
616 | { | |
617 | /* NOTE: Reads from unimplemented PMD registers return zero */ | |
618 | return ((u64)ia64_get_pmd(reg)); | |
619 | } | |
620 | ||
621 | static inline unsigned long vrrtomrr(unsigned long val) | |
622 | { | |
623 | union ia64_rr rr; | |
624 | rr.val = val; | |
625 | rr.rid = (rr.rid << 4) | 0xe; | |
626 | if (rr.ps > PAGE_SHIFT) | |
627 | rr.ps = PAGE_SHIFT; | |
628 | rr.ve = 1; | |
629 | return rr.val; | |
630 | } | |
631 | ||
632 | ||
633 | static inline int highest_bits(int *dat) | |
634 | { | |
635 | u32 bits, bitnum; | |
636 | int i; | |
637 | ||
638 | /* loop for all 256 bits */ | |
639 | for (i = 7; i >= 0 ; i--) { | |
640 | bits = dat[i]; | |
641 | if (bits) { | |
642 | bitnum = fls(bits); | |
643 | return i * 32 + bitnum - 1; | |
644 | } | |
645 | } | |
646 | return NULL_VECTOR; | |
647 | } | |
648 | ||
649 | /* | |
650 | * The pending irq is higher than the inservice one. | |
651 | * | |
652 | */ | |
653 | static inline int is_higher_irq(int pending, int inservice) | |
654 | { | |
655 | return ((pending > inservice) | |
656 | || ((pending != NULL_VECTOR) | |
657 | && (inservice == NULL_VECTOR))); | |
658 | } | |
659 | ||
660 | static inline int is_higher_class(int pending, int mic) | |
661 | { | |
662 | return ((pending >> 4) > mic); | |
663 | } | |
664 | ||
665 | /* | |
666 | * Return 0-255 for pending irq. | |
667 | * NULL_VECTOR: when no pending. | |
668 | */ | |
669 | static inline int highest_pending_irq(struct kvm_vcpu *vcpu) | |
670 | { | |
671 | if (VCPU(vcpu, irr[0]) & (1UL<<NMI_VECTOR)) | |
672 | return NMI_VECTOR; | |
673 | if (VCPU(vcpu, irr[0]) & (1UL<<ExtINT_VECTOR)) | |
674 | return ExtINT_VECTOR; | |
675 | ||
676 | return highest_bits((int *)&VCPU(vcpu, irr[0])); | |
677 | } | |
678 | ||
679 | static inline int highest_inservice_irq(struct kvm_vcpu *vcpu) | |
680 | { | |
681 | if (VMX(vcpu, insvc[0]) & (1UL<<NMI_VECTOR)) | |
682 | return NMI_VECTOR; | |
683 | if (VMX(vcpu, insvc[0]) & (1UL<<ExtINT_VECTOR)) | |
684 | return ExtINT_VECTOR; | |
685 | ||
686 | return highest_bits((int *)&(VMX(vcpu, insvc[0]))); | |
687 | } | |
688 | ||
e9cbde8c | 689 | extern void vcpu_get_fpreg(struct kvm_vcpu *vcpu, unsigned long reg, |
a4f50038 | 690 | struct ia64_fpreg *val); |
e9cbde8c | 691 | extern void vcpu_set_fpreg(struct kvm_vcpu *vcpu, unsigned long reg, |
a4f50038 | 692 | struct ia64_fpreg *val); |
e9cbde8c AK |
693 | extern u64 vcpu_get_gr(struct kvm_vcpu *vcpu, unsigned long reg); |
694 | extern void vcpu_set_gr(struct kvm_vcpu *vcpu, unsigned long reg, | |
695 | u64 val, int nat); | |
696 | extern unsigned long vcpu_get_psr(struct kvm_vcpu *vcpu); | |
697 | extern void vcpu_set_psr(struct kvm_vcpu *vcpu, unsigned long val); | |
a4f50038 XZ |
698 | extern u64 vcpu_thash(struct kvm_vcpu *vcpu, u64 vadr); |
699 | extern void vcpu_bsw0(struct kvm_vcpu *vcpu); | |
700 | extern void thash_vhpt_insert(struct kvm_vcpu *v, u64 pte, | |
701 | u64 itir, u64 va, int type); | |
702 | extern struct thash_data *vhpt_lookup(u64 va); | |
703 | extern u64 guest_vhpt_lookup(u64 iha, u64 *pte); | |
704 | extern void thash_purge_entries(struct kvm_vcpu *v, u64 va, u64 ps); | |
705 | extern void thash_purge_entries_remote(struct kvm_vcpu *v, u64 va, u64 ps); | |
706 | extern u64 translate_phy_pte(u64 *pte, u64 itir, u64 va); | |
27d14644 | 707 | extern void thash_purge_and_insert(struct kvm_vcpu *v, u64 pte, |
a4f50038 XZ |
708 | u64 itir, u64 ifa, int type); |
709 | extern void thash_purge_all(struct kvm_vcpu *v); | |
710 | extern struct thash_data *vtlb_lookup(struct kvm_vcpu *v, | |
711 | u64 va, int is_data); | |
712 | extern int vtr_find_overlap(struct kvm_vcpu *vcpu, u64 va, | |
713 | u64 ps, int is_data); | |
714 | ||
715 | extern void vcpu_increment_iip(struct kvm_vcpu *v); | |
716 | extern void vcpu_decrement_iip(struct kvm_vcpu *vcpu); | |
717 | extern void vcpu_pend_interrupt(struct kvm_vcpu *vcpu, u8 vec); | |
718 | extern void vcpu_unpend_interrupt(struct kvm_vcpu *vcpu, u8 vec); | |
719 | extern void data_page_not_present(struct kvm_vcpu *vcpu, u64 vadr); | |
720 | extern void dnat_page_consumption(struct kvm_vcpu *vcpu, u64 vadr); | |
721 | extern void alt_dtlb(struct kvm_vcpu *vcpu, u64 vadr); | |
722 | extern void nested_dtlb(struct kvm_vcpu *vcpu); | |
723 | extern void dvhpt_fault(struct kvm_vcpu *vcpu, u64 vadr); | |
724 | extern int vhpt_enabled(struct kvm_vcpu *vcpu, u64 vadr, enum vhpt_ref ref); | |
725 | ||
726 | extern void update_vhpi(struct kvm_vcpu *vcpu, int vec); | |
727 | extern int irq_masked(struct kvm_vcpu *vcpu, int h_pending, int h_inservice); | |
728 | ||
729 | extern int fetch_code(struct kvm_vcpu *vcpu, u64 gip, IA64_BUNDLE *pbundle); | |
730 | extern void emulate_io_inst(struct kvm_vcpu *vcpu, u64 padr, u64 ma); | |
731 | extern void vmm_transition(struct kvm_vcpu *vcpu); | |
732 | extern void vmm_trampoline(union context *from, union context *to); | |
733 | extern int vmm_entry(void); | |
734 | extern u64 vcpu_get_itc(struct kvm_vcpu *vcpu); | |
735 | ||
736 | extern void vmm_reset_entry(void); | |
737 | void kvm_init_vtlb(struct kvm_vcpu *v); | |
738 | void kvm_init_vhpt(struct kvm_vcpu *v); | |
739 | void thash_init(struct thash_cb *hcb, u64 sz); | |
740 | ||
5e2be198 | 741 | void panic_vm(struct kvm_vcpu *v, const char *fmt, ...); |
27d14644 | 742 | u64 kvm_gpa_to_mpa(u64 gpa); |
a4f50038 XZ |
743 | extern u64 ia64_call_vsa(u64 proc, u64 arg1, u64 arg2, u64 arg3, |
744 | u64 arg4, u64 arg5, u64 arg6, u64 arg7); | |
9f7d5bb5 XZ |
745 | |
746 | extern long vmm_sanity; | |
747 | ||
a4f50038 XZ |
748 | #endif |
749 | #endif /* __VCPU_H__ */ |