[mirror_ubuntu-bionic-kernel.git] / arch / ia64 / sn / pci / pcibr / pcibr_provider.c

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 2001-2004, 2006 Silicon Graphics, Inc. All rights reserved.
 */

#include <linux/interrupt.h>
#include <linux/types.h>
#include <linux/slab.h>
#include <linux/pci.h>
#include <asm/sn/addrs.h>
#include <asm/sn/geo.h>
#include <asm/sn/pcibr_provider.h>
#include <asm/sn/pcibus_provider_defs.h>
#include <asm/sn/pcidev.h>
#include <asm/sn/sn_sal.h>
#include <asm/sn/pic.h>
#include <asm/sn/sn2/sn_hwperf.h>
#include "xtalk/xwidgetdev.h"
#include "xtalk/hubdev.h"

int
sal_pcibr_slot_enable(struct pcibus_info *soft, int device, void *resp,
                      char **ssdt)
{
	struct ia64_sal_retval ret_stuff;
	u64 busnum;
	u64 segment;

	ret_stuff.status = 0;
	ret_stuff.v0 = 0;

	segment = soft->pbi_buscommon.bs_persist_segment;
	busnum = soft->pbi_buscommon.bs_persist_busnum;
	SAL_CALL_NOLOCK(ret_stuff, (u64) SN_SAL_IOIF_SLOT_ENABLE, segment,
			busnum, (u64) device, (u64) resp, (u64)ia64_tpa(ssdt),
			0, 0);

	return (int)ret_stuff.v0;
}

int
sal_pcibr_slot_disable(struct pcibus_info *soft, int device, int action,
		       void *resp)
{
	struct ia64_sal_retval ret_stuff;
	u64 busnum;
	u64 segment;

	ret_stuff.status = 0;
	ret_stuff.v0 = 0;

	segment = soft->pbi_buscommon.bs_persist_segment;
	busnum = soft->pbi_buscommon.bs_persist_busnum;
	SAL_CALL_NOLOCK(ret_stuff, (u64) SN_SAL_IOIF_SLOT_DISABLE,
			segment, busnum, (u64) device, (u64) action,
			(u64) resp, 0, 0);

	return (int)ret_stuff.v0;
}

static int sal_pcibr_error_interrupt(struct pcibus_info *soft)
{
	struct ia64_sal_retval ret_stuff;
	u64 busnum;
	int segment;
	ret_stuff.status = 0;
	ret_stuff.v0 = 0;

	segment = soft->pbi_buscommon.bs_persist_segment;
	busnum = soft->pbi_buscommon.bs_persist_busnum;
	SAL_CALL_NOLOCK(ret_stuff,
			(u64) SN_SAL_IOIF_ERROR_INTERRUPT,
			(u64) segment, (u64) busnum, 0, 0, 0, 0, 0);

	return (int)ret_stuff.v0;
}

u16 sn_ioboard_to_pci_bus(struct pci_bus *pci_bus)
{
	long rc;
	u16 uninitialized_var(ioboard);		/* GCC be quiet */
	nasid_t nasid = NASID_GET(SN_PCIBUS_BUSSOFT(pci_bus)->bs_base);

	rc = ia64_sn_sysctl_ioboard_get(nasid, &ioboard);
	if (rc) {
		printk(KERN_WARNING "ia64_sn_sysctl_ioboard_get failed: %ld\n",
		       rc);
		return 0;
	}

	return ioboard;
}

/* 
 * PCI Bridge Error interrupt handler.  Gets invoked whenever a PCI 
 * bridge sends an error interrupt.
 */
static irqreturn_t
pcibr_error_intr_handler(int irq, void *arg)
{
	struct pcibus_info *soft = arg;

	if (sal_pcibr_error_interrupt(soft) < 0)
		panic("pcibr_error_intr_handler(): Fatal Bridge Error");

	return IRQ_HANDLED;
}

void *
pcibr_bus_fixup(struct pcibus_bussoft *prom_bussoft, struct pci_controller *controller)
{
	int nasid, cnode, j;
	struct hubdev_info *hubdev_info;
	struct pcibus_info *soft;
	struct sn_flush_device_kernel *sn_flush_device_kernel;
	struct sn_flush_device_common *common;

	if (! IS_PCI_BRIDGE_ASIC(prom_bussoft->bs_asic_type)) {
		return NULL;
	}

	/*
	 * Allocate kernel bus soft and copy from prom.
	 */

	soft = kmalloc(sizeof(struct pcibus_info), GFP_KERNEL);
	if (!soft) {
		return NULL;
	}

	memcpy(soft, prom_bussoft, sizeof(struct pcibus_info));
	soft->pbi_buscommon.bs_base = (unsigned long)
		ioremap(REGION_OFFSET(soft->pbi_buscommon.bs_base),
			sizeof(struct pic));

	spin_lock_init(&soft->pbi_lock);

	/*
	 * register the bridge's error interrupt handler
	 */
	if (request_irq(SGI_PCIASIC_ERROR, pcibr_error_intr_handler,
			IRQF_SHARED, "PCIBR error", (void *)(soft))) {
		printk(KERN_WARNING
		       "pcibr cannot allocate interrupt for error handler\n");
	}
	sn_set_err_irq_affinity(SGI_PCIASIC_ERROR);

	/* 
	 * Update the Bridge with the "kernel" pagesize 
	 */
	if (PAGE_SIZE < 16384) {
		pcireg_control_bit_clr(soft, PCIBR_CTRL_PAGE_SIZE);
	} else {
		pcireg_control_bit_set(soft, PCIBR_CTRL_PAGE_SIZE);
	}

	nasid = NASID_GET(soft->pbi_buscommon.bs_base);
	cnode = nasid_to_cnodeid(nasid);
	hubdev_info = (struct hubdev_info *)(NODEPDA(cnode)->pdinfo);

	if (hubdev_info->hdi_flush_nasid_list.widget_p) {
		sn_flush_device_kernel = hubdev_info->hdi_flush_nasid_list.
		    widget_p[(int)soft->pbi_buscommon.bs_xid];
		if (sn_flush_device_kernel) {
			for (j = 0; j < DEV_PER_WIDGET;
			     j++, sn_flush_device_kernel++) {
				common = sn_flush_device_kernel->common;
				if (common->sfdl_slot == -1)
					continue;
				if ((common->sfdl_persistent_segment ==
				     soft->pbi_buscommon.bs_persist_segment) &&
				     (common->sfdl_persistent_busnum ==
				     soft->pbi_buscommon.bs_persist_busnum))
					common->sfdl_pcibus_info =
					    soft;
			}
		}
	}

	/* Setup the PMU ATE map */
	soft->pbi_int_ate_resource.lowest_free_index = 0;
	soft->pbi_int_ate_resource.ate =
	    kzalloc(soft->pbi_int_ate_size * sizeof(u64), GFP_KERNEL);

	if (!soft->pbi_int_ate_resource.ate) {
		kfree(soft);
		return NULL;
	}

	return soft;
}

void pcibr_force_interrupt(struct sn_irq_info *sn_irq_info)
{
	struct pcidev_info *pcidev_info;
	struct pcibus_info *pcibus_info;
	int bit = sn_irq_info->irq_int_bit;

	if (! sn_irq_info->irq_bridge)
		return;

	pcidev_info = (struct pcidev_info *)sn_irq_info->irq_pciioinfo;
	if (pcidev_info) {
		pcibus_info =
		    (struct pcibus_info *)pcidev_info->pdi_host_pcidev_info->
		    pdi_pcibus_info;
		pcireg_force_intr_set(pcibus_info, bit);
	}
}

void pcibr_target_interrupt(struct sn_irq_info *sn_irq_info)
{
	struct pcidev_info *pcidev_info;
	struct pcibus_info *pcibus_info;
	int bit = sn_irq_info->irq_int_bit;
	u64 xtalk_addr = sn_irq_info->irq_xtalkaddr;

	pcidev_info = (struct pcidev_info *)sn_irq_info->irq_pciioinfo;
	if (pcidev_info) {
		pcibus_info =
		    (struct pcibus_info *)pcidev_info->pdi_host_pcidev_info->
		    pdi_pcibus_info;

		/* Disable the device's IRQ   */
		pcireg_intr_enable_bit_clr(pcibus_info, (1 << bit));

		/* Change the device's IRQ    */
		pcireg_intr_addr_addr_set(pcibus_info, bit, xtalk_addr);

		/* Re-enable the device's IRQ */
		pcireg_intr_enable_bit_set(pcibus_info, (1 << bit));

		pcibr_force_interrupt(sn_irq_info);
	}
}

/*
 * Provider entries for PIC/CP
 */

struct sn_pcibus_provider pcibr_provider = {
	.dma_map = pcibr_dma_map,
	.dma_map_consistent = pcibr_dma_map_consistent,
	.dma_unmap = pcibr_dma_unmap,
	.bus_fixup = pcibr_bus_fixup,
	.force_interrupt = pcibr_force_interrupt,
	.target_interrupt = pcibr_target_interrupt
};

int
pcibr_init_provider(void)
{
	sn_pci_provider[PCIIO_ASIC_TYPE_PIC] = &pcibr_provider;
	sn_pci_provider[PCIIO_ASIC_TYPE_TIOCP] = &pcibr_provider;

	return 0;
}

EXPORT_SYMBOL_GPL(sal_pcibr_slot_enable);
EXPORT_SYMBOL_GPL(sal_pcibr_slot_disable);
EXPORT_SYMBOL_GPL(sn_ioboard_to_pci_bus);
Commit	Line	Data
1da177e4 LT	1	/*
	2	* This file is subject to the terms and conditions of the GNU General Public
	3	* License. See the file "COPYING" in the main directory of this archive
	4	* for more details.
	5	*
8ea6091f	6	* Copyright (C) 2001-2004, 2006 Silicon Graphics, Inc. All rights reserved.
1da177e4 LT	7	*/
1da177e4 LT	8
1da177e4	9	#include <linux/interrupt.h>
c13cf371	10	#include <linux/types.h>
5a0e3ad6	11	#include <linux/slab.h>
1da177e4	12	#include <linux/pci.h>
c13cf371	13	#include <asm/sn/addrs.h>
1da177e4	14	#include <asm/sn/geo.h>
c13cf371	15	#include <asm/sn/pcibr_provider.h>
9b08ebd1 MM	16	#include <asm/sn/pcibus_provider_defs.h>
9b08ebd1 MM	17	#include <asm/sn/pcidev.h>
c13cf371	18	#include <asm/sn/sn_sal.h>
1ee27a4e	19	#include <asm/sn/pic.h>
5390970d	20	#include <asm/sn/sn2/sn_hwperf.h>
c13cf371 PB	21	#include "xtalk/xwidgetdev.h"
c13cf371 PB	22	#include "xtalk/hubdev.h"
1da177e4	23
6f354b01	24	int
6f09a925 JK	25	sal_pcibr_slot_enable(struct pcibus_info soft, int device, void resp,
6f09a925 JK	26	char **ssdt)
6f354b01 PB	27	{
6f354b01 PB	28	struct ia64_sal_retval ret_stuff;
53493dcf	29	u64 busnum;
ac354a89	30	u64 segment;
6f354b01 PB	31
	32	ret_stuff.status = 0;
	33	ret_stuff.v0 = 0;
	34
ac354a89	35	segment = soft->pbi_buscommon.bs_persist_segment;
6f354b01	36	busnum = soft->pbi_buscommon.bs_persist_busnum;
ac354a89	37	SAL_CALL_NOLOCK(ret_stuff, (u64) SN_SAL_IOIF_SLOT_ENABLE, segment,
6f09a925 JK	38	busnum, (u64) device, (u64) resp, (u64)ia64_tpa(ssdt),
6f09a925 JK	39	0, 0);
6f354b01 PB	40
	41	return (int)ret_stuff.v0;
	42	}
	43
	44	int
	45	sal_pcibr_slot_disable(struct pcibus_info *soft, int device, int action,
	46	void *resp)
	47	{
	48	struct ia64_sal_retval ret_stuff;
53493dcf	49	u64 busnum;
ac354a89	50	u64 segment;
6f354b01 PB	51
	52	ret_stuff.status = 0;
	53	ret_stuff.v0 = 0;
	54
ac354a89	55	segment = soft->pbi_buscommon.bs_persist_segment;
6f354b01 PB	56	busnum = soft->pbi_buscommon.bs_persist_busnum;
6f354b01 PB	57	SAL_CALL_NOLOCK(ret_stuff, (u64) SN_SAL_IOIF_SLOT_DISABLE,
ac354a89 MH	58	segment, busnum, (u64) device, (u64) action,
ac354a89 MH	59	(u64) resp, 0, 0);
6f354b01 PB	60
	61	return (int)ret_stuff.v0;
	62	}
	63
1da177e4 LT	64	static int sal_pcibr_error_interrupt(struct pcibus_info *soft)
	65	{
	66	struct ia64_sal_retval ret_stuff;
53493dcf	67	u64 busnum;
1da177e4 LT	68	int segment;
	69	ret_stuff.status = 0;
	70	ret_stuff.v0 = 0;
	71
674c6479	72	segment = soft->pbi_buscommon.bs_persist_segment;
1da177e4 LT	73	busnum = soft->pbi_buscommon.bs_persist_busnum;
	74	SAL_CALL_NOLOCK(ret_stuff,
	75	(u64) SN_SAL_IOIF_ERROR_INTERRUPT,
	76	(u64) segment, (u64) busnum, 0, 0, 0, 0, 0);
	77
	78	return (int)ret_stuff.v0;
	79	}
	80
f90aa8c4 PB	81	u16 sn_ioboard_to_pci_bus(struct pci_bus *pci_bus)
f90aa8c4 PB	82	{
e088a4ad	83	long rc;
256a7e09	84	u16 uninitialized_var(ioboard); /* GCC be quiet */
f90aa8c4 PB	85	nasid_t nasid = NASID_GET(SN_PCIBUS_BUSSOFT(pci_bus)->bs_base);
	86
	87	rc = ia64_sn_sysctl_ioboard_get(nasid, &ioboard);
	88	if (rc) {
	89	printk(KERN_WARNING "ia64_sn_sysctl_ioboard_get failed: %ld\n",
	90	rc);
	91	return 0;
	92	}
	93
	94	return ioboard;
	95	}
	96
1da177e4 LT	97	/*
	98	* PCI Bridge Error interrupt handler. Gets invoked whenever a PCI
	99	* bridge sends an error interrupt.
	100	*/
	101	static irqreturn_t
a23b7cb9	102	pcibr_error_intr_handler(int irq, void *arg)
1da177e4	103	{
15aafa2f	104	struct pcibus_info *soft = arg;
1da177e4	105
15aafa2f	106	if (sal_pcibr_error_interrupt(soft) < 0)
1da177e4	107	panic("pcibr_error_intr_handler(): Fatal Bridge Error");
15aafa2f	108
1da177e4 LT	109	return IRQ_HANDLED;
	110	}
	111
	112	void *
7c2a6c62	113	pcibr_bus_fixup(struct pcibus_bussoft prom_bussoft, struct pci_controller controller)
1da177e4 LT	114	{
	115	int nasid, cnode, j;
	116	struct hubdev_info *hubdev_info;
	117	struct pcibus_info *soft;
6d6e4200 PB	118	struct sn_flush_device_kernel *sn_flush_device_kernel;
6d6e4200 PB	119	struct sn_flush_device_common *common;
1da177e4 LT	120
	121	if (! IS_PCI_BRIDGE_ASIC(prom_bussoft->bs_asic_type)) {
	122	return NULL;
	123	}
	124
	125	/*
	126	* Allocate kernel bus soft and copy from prom.
	127	*/
	128
	129	soft = kmalloc(sizeof(struct pcibus_info), GFP_KERNEL);
	130	if (!soft) {
	131	return NULL;
	132	}
	133
	134	memcpy(soft, prom_bussoft, sizeof(struct pcibus_info));
1ee27a4e JS	135	soft->pbi_buscommon.bs_base = (unsigned long)
	136	ioremap(REGION_OFFSET(soft->pbi_buscommon.bs_base),
	137	sizeof(struct pic));
1da177e4 LT	138
	139	spin_lock_init(&soft->pbi_lock);
	140
	141	/*
	142	* register the bridge's error interrupt handler
	143	*/
a23b7cb9	144	if (request_irq(SGI_PCIASIC_ERROR, pcibr_error_intr_handler,
121a4226	145	IRQF_SHARED, "PCIBR error", (void *)(soft))) {
1da177e4 LT	146	printk(KERN_WARNING
	147	"pcibr cannot allocate interrupt for error handler\n");
	148	}
6e9de181	149	sn_set_err_irq_affinity(SGI_PCIASIC_ERROR);
1da177e4 LT	150
	151	/*
	152	* Update the Bridge with the "kernel" pagesize
	153	*/
	154	if (PAGE_SIZE < 16384) {
	155	pcireg_control_bit_clr(soft, PCIBR_CTRL_PAGE_SIZE);
	156	} else {
	157	pcireg_control_bit_set(soft, PCIBR_CTRL_PAGE_SIZE);
	158	}
	159
	160	nasid = NASID_GET(soft->pbi_buscommon.bs_base);
	161	cnode = nasid_to_cnodeid(nasid);
	162	hubdev_info = (struct hubdev_info *)(NODEPDA(cnode)->pdinfo);
	163
	164	if (hubdev_info->hdi_flush_nasid_list.widget_p) {
6d6e4200	165	sn_flush_device_kernel = hubdev_info->hdi_flush_nasid_list.
1da177e4	166	widget_p[(int)soft->pbi_buscommon.bs_xid];
6d6e4200	167	if (sn_flush_device_kernel) {
1da177e4	168	for (j = 0; j < DEV_PER_WIDGET;
6d6e4200 PB	169	j++, sn_flush_device_kernel++) {
	170	common = sn_flush_device_kernel->common;
	171	if (common->sfdl_slot == -1)
1da177e4	172	continue;
6d6e4200	173	if ((common->sfdl_persistent_segment ==
674c6479	174	soft->pbi_buscommon.bs_persist_segment) &&
6d6e4200	175	(common->sfdl_persistent_busnum ==
674c6479	176	soft->pbi_buscommon.bs_persist_busnum))
6d6e4200	177	common->sfdl_pcibus_info =
1da177e4 LT	178	soft;
	179	}
	180	}
	181	}
	182
	183	/* Setup the PMU ATE map */
	184	soft->pbi_int_ate_resource.lowest_free_index = 0;
	185	soft->pbi_int_ate_resource.ate =
8ed9b2c7 JS	186	kzalloc(soft->pbi_int_ate_size * sizeof(u64), GFP_KERNEL);
	187
	188	if (!soft->pbi_int_ate_resource.ate) {
	189	kfree(soft);
	190	return NULL;
	191	}
1da177e4 LT	192
	193	return soft;
	194	}
	195
	196	void pcibr_force_interrupt(struct sn_irq_info *sn_irq_info)
	197	{
	198	struct pcidev_info *pcidev_info;
	199	struct pcibus_info *pcibus_info;
	200	int bit = sn_irq_info->irq_int_bit;
	201
735e60f4 MM	202	if (! sn_irq_info->irq_bridge)
	203	return;
	204
1da177e4 LT	205	pcidev_info = (struct pcidev_info *)sn_irq_info->irq_pciioinfo;
	206	if (pcidev_info) {
	207	pcibus_info =
	208	(struct pcibus_info *)pcidev_info->pdi_host_pcidev_info->
	209	pdi_pcibus_info;
	210	pcireg_force_intr_set(pcibus_info, bit);
	211	}
	212	}
	213
8409668b	214	void pcibr_target_interrupt(struct sn_irq_info *sn_irq_info)
1da177e4 LT	215	{
	216	struct pcidev_info *pcidev_info;
	217	struct pcibus_info *pcibus_info;
	218	int bit = sn_irq_info->irq_int_bit;
53493dcf	219	u64 xtalk_addr = sn_irq_info->irq_xtalkaddr;
1da177e4 LT	220
	221	pcidev_info = (struct pcidev_info *)sn_irq_info->irq_pciioinfo;
	222	if (pcidev_info) {
	223	pcibus_info =
	224	(struct pcibus_info *)pcidev_info->pdi_host_pcidev_info->
	225	pdi_pcibus_info;
	226
	227	/* Disable the device's IRQ */
6fb93a92	228	pcireg_intr_enable_bit_clr(pcibus_info, (1 << bit));
1da177e4 LT	229
	230	/* Change the device's IRQ */
	231	pcireg_intr_addr_addr_set(pcibus_info, bit, xtalk_addr);
	232
	233	/* Re-enable the device's IRQ */
6fb93a92	234	pcireg_intr_enable_bit_set(pcibus_info, (1 << bit));
1da177e4 LT	235
	236	pcibr_force_interrupt(sn_irq_info);
	237	}
	238	}
e955d825 MM	239
	240	/*
	241	* Provider entries for PIC/CP
	242	*/
	243
	244	struct sn_pcibus_provider pcibr_provider = {
	245	.dma_map = pcibr_dma_map,
	246	.dma_map_consistent = pcibr_dma_map_consistent,
	247	.dma_unmap = pcibr_dma_unmap,
	248	.bus_fixup = pcibr_bus_fixup,
8409668b MM	249	.force_interrupt = pcibr_force_interrupt,
8409668b MM	250	.target_interrupt = pcibr_target_interrupt
e955d825 MM	251	};
	252
	253	int
	254	pcibr_init_provider(void)
	255	{
	256	sn_pci_provider[PCIIO_ASIC_TYPE_PIC] = &pcibr_provider;
	257	sn_pci_provider[PCIIO_ASIC_TYPE_TIOCP] = &pcibr_provider;
	258
	259	return 0;
	260	}
6f354b01 PB	261
	262	EXPORT_SYMBOL_GPL(sal_pcibr_slot_enable);
	263	EXPORT_SYMBOL_GPL(sal_pcibr_slot_disable);
f90aa8c4	264	EXPORT_SYMBOL_GPL(sn_ioboard_to_pci_bus);