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c9221da9 MM |
1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public | |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
5 | * | |
6 | * Copyright (C) 2003-2005 Silicon Graphics, Inc. All Rights Reserved. | |
7 | */ | |
8 | ||
9 | #include <linux/types.h> | |
10 | #include <linux/interrupt.h> | |
11 | #include <linux/pci.h> | |
12 | #include <asm/sn/sn_sal.h> | |
13 | #include <asm/sn/addrs.h> | |
1fa92957 | 14 | #include <asm/sn/io.h> |
c9221da9 MM |
15 | #include <asm/sn/pcidev.h> |
16 | #include <asm/sn/pcibus_provider_defs.h> | |
17 | #include <asm/sn/tioce_provider.h> | |
18 | ||
19 | /** | |
20 | * Bus address ranges for the 5 flavors of TIOCE DMA | |
21 | */ | |
22 | ||
23 | #define TIOCE_D64_MIN 0x8000000000000000UL | |
24 | #define TIOCE_D64_MAX 0xffffffffffffffffUL | |
25 | #define TIOCE_D64_ADDR(a) ((a) >= TIOCE_D64_MIN) | |
26 | ||
27 | #define TIOCE_D32_MIN 0x0000000080000000UL | |
28 | #define TIOCE_D32_MAX 0x00000000ffffffffUL | |
29 | #define TIOCE_D32_ADDR(a) ((a) >= TIOCE_D32_MIN && (a) <= TIOCE_D32_MAX) | |
30 | ||
31 | #define TIOCE_M32_MIN 0x0000000000000000UL | |
32 | #define TIOCE_M32_MAX 0x000000007fffffffUL | |
33 | #define TIOCE_M32_ADDR(a) ((a) >= TIOCE_M32_MIN && (a) <= TIOCE_M32_MAX) | |
34 | ||
35 | #define TIOCE_M40_MIN 0x0000004000000000UL | |
36 | #define TIOCE_M40_MAX 0x0000007fffffffffUL | |
37 | #define TIOCE_M40_ADDR(a) ((a) >= TIOCE_M40_MIN && (a) <= TIOCE_M40_MAX) | |
38 | ||
39 | #define TIOCE_M40S_MIN 0x0000008000000000UL | |
40 | #define TIOCE_M40S_MAX 0x000000ffffffffffUL | |
41 | #define TIOCE_M40S_ADDR(a) ((a) >= TIOCE_M40S_MIN && (a) <= TIOCE_M40S_MAX) | |
42 | ||
43 | /* | |
44 | * ATE manipulation macros. | |
45 | */ | |
46 | ||
47 | #define ATE_PAGESHIFT(ps) (__ffs(ps)) | |
48 | #define ATE_PAGEMASK(ps) ((ps)-1) | |
49 | ||
50 | #define ATE_PAGE(x, ps) ((x) >> ATE_PAGESHIFT(ps)) | |
51 | #define ATE_NPAGES(start, len, pagesize) \ | |
52 | (ATE_PAGE((start)+(len)-1, pagesize) - ATE_PAGE(start, pagesize) + 1) | |
53 | ||
54 | #define ATE_VALID(ate) ((ate) & (1UL << 63)) | |
55 | #define ATE_MAKE(addr, ps) (((addr) & ~ATE_PAGEMASK(ps)) | (1UL << 63)) | |
56 | ||
57 | /* | |
58 | * Flavors of ate-based mapping supported by tioce_alloc_map() | |
59 | */ | |
60 | ||
61 | #define TIOCE_ATE_M32 1 | |
62 | #define TIOCE_ATE_M40 2 | |
63 | #define TIOCE_ATE_M40S 3 | |
64 | ||
65 | #define KB(x) ((x) << 10) | |
66 | #define MB(x) ((x) << 20) | |
67 | #define GB(x) ((x) << 30) | |
68 | ||
69 | /** | |
70 | * tioce_dma_d64 - create a DMA mapping using 64-bit direct mode | |
71 | * @ct_addr: system coretalk address | |
72 | * | |
73 | * Map @ct_addr into 64-bit CE bus space. No device context is necessary | |
74 | * and no CE mapping are consumed. | |
75 | * | |
76 | * Bits 53:0 come from the coretalk address. The remaining bits are set as | |
77 | * follows: | |
78 | * | |
79 | * 63 - must be 1 to indicate d64 mode to CE hardware | |
80 | * 62 - barrier bit ... controlled with tioce_dma_barrier() | |
81 | * 61 - 0 since this is not an MSI transaction | |
82 | * 60:54 - reserved, MBZ | |
83 | */ | |
53493dcf | 84 | static u64 |
c9221da9 MM |
85 | tioce_dma_d64(unsigned long ct_addr) |
86 | { | |
53493dcf | 87 | u64 bus_addr; |
c9221da9 MM |
88 | |
89 | bus_addr = ct_addr | (1UL << 63); | |
90 | ||
91 | return bus_addr; | |
92 | } | |
93 | ||
94 | /** | |
95 | * pcidev_to_tioce - return misc ce related pointers given a pci_dev | |
96 | * @pci_dev: pci device context | |
97 | * @base: ptr to store struct tioce_mmr * for the CE holding this device | |
98 | * @kernel: ptr to store struct tioce_kernel * for the CE holding this device | |
99 | * @port: ptr to store the CE port number that this device is on | |
100 | * | |
101 | * Return pointers to various CE-related structures for the CE upstream of | |
102 | * @pci_dev. | |
103 | */ | |
104 | static inline void | |
105 | pcidev_to_tioce(struct pci_dev *pdev, struct tioce **base, | |
106 | struct tioce_kernel **kernel, int *port) | |
107 | { | |
108 | struct pcidev_info *pcidev_info; | |
109 | struct tioce_common *ce_common; | |
110 | struct tioce_kernel *ce_kernel; | |
111 | ||
112 | pcidev_info = SN_PCIDEV_INFO(pdev); | |
113 | ce_common = (struct tioce_common *)pcidev_info->pdi_pcibus_info; | |
114 | ce_kernel = (struct tioce_kernel *)ce_common->ce_kernel_private; | |
115 | ||
116 | if (base) | |
117 | *base = (struct tioce *)ce_common->ce_pcibus.bs_base; | |
118 | if (kernel) | |
119 | *kernel = ce_kernel; | |
120 | ||
121 | /* | |
122 | * we use port as a zero-based value internally, even though the | |
123 | * documentation is 1-based. | |
124 | */ | |
125 | if (port) | |
126 | *port = | |
127 | (pdev->bus->number < ce_kernel->ce_port1_secondary) ? 0 : 1; | |
128 | } | |
129 | ||
130 | /** | |
131 | * tioce_alloc_map - Given a coretalk address, map it to pcie bus address | |
132 | * space using one of the various ATE-based address modes. | |
133 | * @ce_kern: tioce context | |
134 | * @type: map mode to use | |
135 | * @port: 0-based port that the requesting device is downstream of | |
136 | * @ct_addr: the coretalk address to map | |
137 | * @len: number of bytes to map | |
138 | * | |
139 | * Given the addressing type, set up various paramaters that define the | |
140 | * ATE pool to use. Search for a contiguous block of entries to cover the | |
141 | * length, and if enough resources exist, fill in the ATE's and construct a | |
142 | * tioce_dmamap struct to track the mapping. | |
143 | */ | |
53493dcf | 144 | static u64 |
c9221da9 | 145 | tioce_alloc_map(struct tioce_kernel *ce_kern, int type, int port, |
53493dcf | 146 | u64 ct_addr, int len) |
c9221da9 MM |
147 | { |
148 | int i; | |
149 | int j; | |
150 | int first; | |
151 | int last; | |
152 | int entries; | |
153 | int nates; | |
154 | int pagesize; | |
53493dcf PB |
155 | u64 *ate_shadow; |
156 | u64 *ate_reg; | |
157 | u64 addr; | |
c9221da9 | 158 | struct tioce *ce_mmr; |
53493dcf | 159 | u64 bus_base; |
c9221da9 MM |
160 | struct tioce_dmamap *map; |
161 | ||
162 | ce_mmr = (struct tioce *)ce_kern->ce_common->ce_pcibus.bs_base; | |
163 | ||
164 | switch (type) { | |
165 | case TIOCE_ATE_M32: | |
166 | /* | |
167 | * The first 64 entries of the ate3240 pool are dedicated to | |
168 | * super-page (TIOCE_ATE_M40S) mode. | |
169 | */ | |
170 | first = 64; | |
171 | entries = TIOCE_NUM_M3240_ATES - 64; | |
172 | ate_shadow = ce_kern->ce_ate3240_shadow; | |
173 | ate_reg = ce_mmr->ce_ure_ate3240; | |
174 | pagesize = ce_kern->ce_ate3240_pagesize; | |
175 | bus_base = TIOCE_M32_MIN; | |
176 | break; | |
177 | case TIOCE_ATE_M40: | |
178 | first = 0; | |
179 | entries = TIOCE_NUM_M40_ATES; | |
180 | ate_shadow = ce_kern->ce_ate40_shadow; | |
181 | ate_reg = ce_mmr->ce_ure_ate40; | |
182 | pagesize = MB(64); | |
183 | bus_base = TIOCE_M40_MIN; | |
184 | break; | |
185 | case TIOCE_ATE_M40S: | |
186 | /* | |
187 | * ate3240 entries 0-31 are dedicated to port1 super-page | |
188 | * mappings. ate3240 entries 32-63 are dedicated to port2. | |
189 | */ | |
190 | first = port * 32; | |
191 | entries = 32; | |
192 | ate_shadow = ce_kern->ce_ate3240_shadow; | |
193 | ate_reg = ce_mmr->ce_ure_ate3240; | |
194 | pagesize = GB(16); | |
195 | bus_base = TIOCE_M40S_MIN; | |
196 | break; | |
197 | default: | |
198 | return 0; | |
199 | } | |
200 | ||
201 | nates = ATE_NPAGES(ct_addr, len, pagesize); | |
202 | if (nates > entries) | |
203 | return 0; | |
204 | ||
205 | last = first + entries - nates; | |
206 | for (i = first; i <= last; i++) { | |
207 | if (ATE_VALID(ate_shadow[i])) | |
208 | continue; | |
209 | ||
210 | for (j = i; j < i + nates; j++) | |
211 | if (ATE_VALID(ate_shadow[j])) | |
212 | break; | |
213 | ||
214 | if (j >= i + nates) | |
215 | break; | |
216 | } | |
217 | ||
218 | if (i > last) | |
219 | return 0; | |
220 | ||
baf47fb6 | 221 | map = kzalloc(sizeof(struct tioce_dmamap), GFP_ATOMIC); |
c9221da9 MM |
222 | if (!map) |
223 | return 0; | |
224 | ||
225 | addr = ct_addr; | |
226 | for (j = 0; j < nates; j++) { | |
53493dcf | 227 | u64 ate; |
c9221da9 MM |
228 | |
229 | ate = ATE_MAKE(addr, pagesize); | |
230 | ate_shadow[i + j] = ate; | |
5fbcf9a5 | 231 | writeq(ate, &ate_reg[i + j]); |
c9221da9 MM |
232 | addr += pagesize; |
233 | } | |
234 | ||
235 | map->refcnt = 1; | |
236 | map->nbytes = nates * pagesize; | |
237 | map->ct_start = ct_addr & ~ATE_PAGEMASK(pagesize); | |
238 | map->pci_start = bus_base + (i * pagesize); | |
239 | map->ate_hw = &ate_reg[i]; | |
240 | map->ate_shadow = &ate_shadow[i]; | |
241 | map->ate_count = nates; | |
242 | ||
243 | list_add(&map->ce_dmamap_list, &ce_kern->ce_dmamap_list); | |
244 | ||
245 | return (map->pci_start + (ct_addr - map->ct_start)); | |
246 | } | |
247 | ||
248 | /** | |
249 | * tioce_dma_d32 - create a DMA mapping using 32-bit direct mode | |
250 | * @pdev: linux pci_dev representing the function | |
251 | * @paddr: system physical address | |
252 | * | |
253 | * Map @paddr into 32-bit bus space of the CE associated with @pcidev_info. | |
254 | */ | |
53493dcf PB |
255 | static u64 |
256 | tioce_dma_d32(struct pci_dev *pdev, u64 ct_addr) | |
c9221da9 MM |
257 | { |
258 | int dma_ok; | |
259 | int port; | |
260 | struct tioce *ce_mmr; | |
261 | struct tioce_kernel *ce_kern; | |
53493dcf PB |
262 | u64 ct_upper; |
263 | u64 ct_lower; | |
c9221da9 MM |
264 | dma_addr_t bus_addr; |
265 | ||
266 | ct_upper = ct_addr & ~0x3fffffffUL; | |
267 | ct_lower = ct_addr & 0x3fffffffUL; | |
268 | ||
269 | pcidev_to_tioce(pdev, &ce_mmr, &ce_kern, &port); | |
270 | ||
271 | if (ce_kern->ce_port[port].dirmap_refcnt == 0) { | |
53493dcf | 272 | u64 tmp; |
c9221da9 MM |
273 | |
274 | ce_kern->ce_port[port].dirmap_shadow = ct_upper; | |
5fbcf9a5 | 275 | writeq(ct_upper, &ce_mmr->ce_ure_dir_map[port]); |
c9221da9 MM |
276 | tmp = ce_mmr->ce_ure_dir_map[port]; |
277 | dma_ok = 1; | |
278 | } else | |
279 | dma_ok = (ce_kern->ce_port[port].dirmap_shadow == ct_upper); | |
280 | ||
281 | if (dma_ok) { | |
282 | ce_kern->ce_port[port].dirmap_refcnt++; | |
283 | bus_addr = TIOCE_D32_MIN + ct_lower; | |
284 | } else | |
285 | bus_addr = 0; | |
286 | ||
287 | return bus_addr; | |
288 | } | |
289 | ||
290 | /** | |
291 | * tioce_dma_barrier - swizzle a TIOCE bus address to include or exclude | |
292 | * the barrier bit. | |
293 | * @bus_addr: bus address to swizzle | |
294 | * | |
295 | * Given a TIOCE bus address, set the appropriate bit to indicate barrier | |
296 | * attributes. | |
297 | */ | |
53493dcf PB |
298 | static u64 |
299 | tioce_dma_barrier(u64 bus_addr, int on) | |
c9221da9 | 300 | { |
53493dcf | 301 | u64 barrier_bit; |
c9221da9 MM |
302 | |
303 | /* barrier not supported in M40/M40S mode */ | |
304 | if (TIOCE_M40_ADDR(bus_addr) || TIOCE_M40S_ADDR(bus_addr)) | |
305 | return bus_addr; | |
306 | ||
307 | if (TIOCE_D64_ADDR(bus_addr)) | |
308 | barrier_bit = (1UL << 62); | |
309 | else /* must be m32 or d32 */ | |
310 | barrier_bit = (1UL << 30); | |
311 | ||
312 | return (on) ? (bus_addr | barrier_bit) : (bus_addr & ~barrier_bit); | |
313 | } | |
314 | ||
315 | /** | |
316 | * tioce_dma_unmap - release CE mapping resources | |
317 | * @pdev: linux pci_dev representing the function | |
318 | * @bus_addr: bus address returned by an earlier tioce_dma_map | |
319 | * @dir: mapping direction (unused) | |
320 | * | |
321 | * Locate mapping resources associated with @bus_addr and release them. | |
322 | * For mappings created using the direct modes there are no resources | |
323 | * to release. | |
324 | */ | |
325 | void | |
326 | tioce_dma_unmap(struct pci_dev *pdev, dma_addr_t bus_addr, int dir) | |
327 | { | |
328 | int i; | |
329 | int port; | |
330 | struct tioce_kernel *ce_kern; | |
331 | struct tioce *ce_mmr; | |
332 | unsigned long flags; | |
333 | ||
334 | bus_addr = tioce_dma_barrier(bus_addr, 0); | |
335 | pcidev_to_tioce(pdev, &ce_mmr, &ce_kern, &port); | |
336 | ||
337 | /* nothing to do for D64 */ | |
338 | ||
339 | if (TIOCE_D64_ADDR(bus_addr)) | |
340 | return; | |
341 | ||
342 | spin_lock_irqsave(&ce_kern->ce_lock, flags); | |
343 | ||
344 | if (TIOCE_D32_ADDR(bus_addr)) { | |
345 | if (--ce_kern->ce_port[port].dirmap_refcnt == 0) { | |
346 | ce_kern->ce_port[port].dirmap_shadow = 0; | |
5fbcf9a5 | 347 | writeq(0, &ce_mmr->ce_ure_dir_map[port]); |
c9221da9 MM |
348 | } |
349 | } else { | |
350 | struct tioce_dmamap *map; | |
351 | ||
352 | list_for_each_entry(map, &ce_kern->ce_dmamap_list, | |
353 | ce_dmamap_list) { | |
53493dcf | 354 | u64 last; |
c9221da9 MM |
355 | |
356 | last = map->pci_start + map->nbytes - 1; | |
357 | if (bus_addr >= map->pci_start && bus_addr <= last) | |
358 | break; | |
359 | } | |
360 | ||
361 | if (&map->ce_dmamap_list == &ce_kern->ce_dmamap_list) { | |
362 | printk(KERN_WARNING | |
363 | "%s: %s - no map found for bus_addr 0x%lx\n", | |
364 | __FUNCTION__, pci_name(pdev), bus_addr); | |
365 | } else if (--map->refcnt == 0) { | |
366 | for (i = 0; i < map->ate_count; i++) { | |
367 | map->ate_shadow[i] = 0; | |
368 | map->ate_hw[i] = 0; | |
369 | } | |
370 | ||
371 | list_del(&map->ce_dmamap_list); | |
372 | kfree(map); | |
373 | } | |
374 | } | |
375 | ||
376 | spin_unlock_irqrestore(&ce_kern->ce_lock, flags); | |
377 | } | |
378 | ||
379 | /** | |
380 | * tioce_do_dma_map - map pages for PCI DMA | |
381 | * @pdev: linux pci_dev representing the function | |
382 | * @paddr: host physical address to map | |
383 | * @byte_count: bytes to map | |
384 | * | |
385 | * This is the main wrapper for mapping host physical pages to CE PCI space. | |
386 | * The mapping mode used is based on the device's dma_mask. | |
387 | */ | |
53493dcf PB |
388 | static u64 |
389 | tioce_do_dma_map(struct pci_dev *pdev, u64 paddr, size_t byte_count, | |
c9221da9 MM |
390 | int barrier) |
391 | { | |
392 | unsigned long flags; | |
53493dcf PB |
393 | u64 ct_addr; |
394 | u64 mapaddr = 0; | |
c9221da9 MM |
395 | struct tioce_kernel *ce_kern; |
396 | struct tioce_dmamap *map; | |
397 | int port; | |
53493dcf | 398 | u64 dma_mask; |
c9221da9 MM |
399 | |
400 | dma_mask = (barrier) ? pdev->dev.coherent_dma_mask : pdev->dma_mask; | |
401 | ||
402 | /* cards must be able to address at least 31 bits */ | |
403 | if (dma_mask < 0x7fffffffUL) | |
404 | return 0; | |
405 | ||
406 | ct_addr = PHYS_TO_TIODMA(paddr); | |
407 | ||
408 | /* | |
409 | * If the device can generate 64 bit addresses, create a D64 map. | |
410 | * Since this should never fail, bypass the rest of the checks. | |
411 | */ | |
412 | if (dma_mask == ~0UL) { | |
413 | mapaddr = tioce_dma_d64(ct_addr); | |
414 | goto dma_map_done; | |
415 | } | |
416 | ||
417 | pcidev_to_tioce(pdev, NULL, &ce_kern, &port); | |
418 | ||
419 | spin_lock_irqsave(&ce_kern->ce_lock, flags); | |
420 | ||
421 | /* | |
422 | * D64 didn't work ... See if we have an existing map that covers | |
423 | * this address range. Must account for devices dma_mask here since | |
424 | * an existing map might have been done in a mode using more pci | |
425 | * address bits than this device can support. | |
426 | */ | |
427 | list_for_each_entry(map, &ce_kern->ce_dmamap_list, ce_dmamap_list) { | |
53493dcf | 428 | u64 last; |
c9221da9 MM |
429 | |
430 | last = map->ct_start + map->nbytes - 1; | |
431 | if (ct_addr >= map->ct_start && | |
432 | ct_addr + byte_count - 1 <= last && | |
433 | map->pci_start <= dma_mask) { | |
434 | map->refcnt++; | |
435 | mapaddr = map->pci_start + (ct_addr - map->ct_start); | |
436 | break; | |
437 | } | |
438 | } | |
439 | ||
440 | /* | |
441 | * If we don't have a map yet, and the card can generate 40 | |
442 | * bit addresses, try the M40/M40S modes. Note these modes do not | |
443 | * support a barrier bit, so if we need a consistent map these | |
444 | * won't work. | |
445 | */ | |
446 | if (!mapaddr && !barrier && dma_mask >= 0xffffffffffUL) { | |
447 | /* | |
448 | * We have two options for 40-bit mappings: 16GB "super" ATE's | |
449 | * and 64MB "regular" ATE's. We'll try both if needed for a | |
450 | * given mapping but which one we try first depends on the | |
451 | * size. For requests >64MB, prefer to use a super page with | |
452 | * regular as the fallback. Otherwise, try in the reverse order. | |
453 | */ | |
454 | ||
455 | if (byte_count > MB(64)) { | |
456 | mapaddr = tioce_alloc_map(ce_kern, TIOCE_ATE_M40S, | |
457 | port, ct_addr, byte_count); | |
458 | if (!mapaddr) | |
459 | mapaddr = | |
460 | tioce_alloc_map(ce_kern, TIOCE_ATE_M40, -1, | |
461 | ct_addr, byte_count); | |
462 | } else { | |
463 | mapaddr = tioce_alloc_map(ce_kern, TIOCE_ATE_M40, -1, | |
464 | ct_addr, byte_count); | |
465 | if (!mapaddr) | |
466 | mapaddr = | |
467 | tioce_alloc_map(ce_kern, TIOCE_ATE_M40S, | |
468 | port, ct_addr, byte_count); | |
469 | } | |
470 | } | |
471 | ||
472 | /* | |
473 | * 32-bit direct is the next mode to try | |
474 | */ | |
475 | if (!mapaddr && dma_mask >= 0xffffffffUL) | |
476 | mapaddr = tioce_dma_d32(pdev, ct_addr); | |
477 | ||
478 | /* | |
479 | * Last resort, try 32-bit ATE-based map. | |
480 | */ | |
481 | if (!mapaddr) | |
482 | mapaddr = | |
483 | tioce_alloc_map(ce_kern, TIOCE_ATE_M32, -1, ct_addr, | |
484 | byte_count); | |
485 | ||
486 | spin_unlock_irqrestore(&ce_kern->ce_lock, flags); | |
487 | ||
488 | dma_map_done: | |
489 | if (mapaddr & barrier) | |
490 | mapaddr = tioce_dma_barrier(mapaddr, 1); | |
491 | ||
492 | return mapaddr; | |
493 | } | |
494 | ||
495 | /** | |
496 | * tioce_dma - standard pci dma map interface | |
497 | * @pdev: pci device requesting the map | |
498 | * @paddr: system physical address to map into pci space | |
499 | * @byte_count: # bytes to map | |
500 | * | |
501 | * Simply call tioce_do_dma_map() to create a map with the barrier bit clear | |
502 | * in the address. | |
503 | */ | |
53493dcf PB |
504 | static u64 |
505 | tioce_dma(struct pci_dev *pdev, u64 paddr, size_t byte_count) | |
c9221da9 MM |
506 | { |
507 | return tioce_do_dma_map(pdev, paddr, byte_count, 0); | |
508 | } | |
509 | ||
510 | /** | |
511 | * tioce_dma_consistent - consistent pci dma map interface | |
512 | * @pdev: pci device requesting the map | |
513 | * @paddr: system physical address to map into pci space | |
514 | * @byte_count: # bytes to map | |
515 | * | |
516 | * Simply call tioce_do_dma_map() to create a map with the barrier bit set | |
517 | * in the address. | |
53493dcf PB |
518 | */ static u64 |
519 | tioce_dma_consistent(struct pci_dev *pdev, u64 paddr, size_t byte_count) | |
c9221da9 MM |
520 | { |
521 | return tioce_do_dma_map(pdev, paddr, byte_count, 1); | |
522 | } | |
523 | ||
524 | /** | |
525 | * tioce_error_intr_handler - SGI TIO CE error interrupt handler | |
526 | * @irq: unused | |
527 | * @arg: pointer to tioce_common struct for the given CE | |
528 | * @pt: unused | |
529 | * | |
530 | * Handle a CE error interrupt. Simply a wrapper around a SAL call which | |
531 | * defers processing to the SGI prom. | |
532 | */ static irqreturn_t | |
533 | tioce_error_intr_handler(int irq, void *arg, struct pt_regs *pt) | |
534 | { | |
535 | struct tioce_common *soft = arg; | |
536 | struct ia64_sal_retval ret_stuff; | |
537 | ret_stuff.status = 0; | |
538 | ret_stuff.v0 = 0; | |
539 | ||
540 | SAL_CALL_NOLOCK(ret_stuff, (u64) SN_SAL_IOIF_ERROR_INTERRUPT, | |
541 | soft->ce_pcibus.bs_persist_segment, | |
542 | soft->ce_pcibus.bs_persist_busnum, 0, 0, 0, 0, 0); | |
543 | ||
544 | return IRQ_HANDLED; | |
545 | } | |
546 | ||
547 | /** | |
548 | * tioce_kern_init - init kernel structures related to a given TIOCE | |
549 | * @tioce_common: ptr to a cached tioce_common struct that originated in prom | |
550 | */ static struct tioce_kernel * | |
551 | tioce_kern_init(struct tioce_common *tioce_common) | |
552 | { | |
553 | int i; | |
53493dcf | 554 | u32 tmp; |
c9221da9 MM |
555 | struct tioce *tioce_mmr; |
556 | struct tioce_kernel *tioce_kern; | |
557 | ||
baf47fb6 | 558 | tioce_kern = kzalloc(sizeof(struct tioce_kernel), GFP_KERNEL); |
c9221da9 MM |
559 | if (!tioce_kern) { |
560 | return NULL; | |
561 | } | |
562 | ||
563 | tioce_kern->ce_common = tioce_common; | |
564 | spin_lock_init(&tioce_kern->ce_lock); | |
565 | INIT_LIST_HEAD(&tioce_kern->ce_dmamap_list); | |
53493dcf | 566 | tioce_common->ce_kernel_private = (u64) tioce_kern; |
c9221da9 MM |
567 | |
568 | /* | |
569 | * Determine the secondary bus number of the port2 logical PPB. | |
570 | * This is used to decide whether a given pci device resides on | |
571 | * port1 or port2. Note: We don't have enough plumbing set up | |
572 | * here to use pci_read_config_xxx() so use the raw_pci_ops vector. | |
573 | */ | |
574 | ||
575 | raw_pci_ops->read(tioce_common->ce_pcibus.bs_persist_segment, | |
576 | tioce_common->ce_pcibus.bs_persist_busnum, | |
577 | PCI_DEVFN(2, 0), PCI_SECONDARY_BUS, 1, &tmp); | |
53493dcf | 578 | tioce_kern->ce_port1_secondary = (u8) tmp; |
c9221da9 MM |
579 | |
580 | /* | |
581 | * Set PMU pagesize to the largest size available, and zero out | |
582 | * the ate's. | |
583 | */ | |
584 | ||
585 | tioce_mmr = (struct tioce *)tioce_common->ce_pcibus.bs_base; | |
5fbcf9a5 MM |
586 | __sn_clrq_relaxed(&tioce_mmr->ce_ure_page_map, CE_URE_PAGESIZE_MASK); |
587 | __sn_setq_relaxed(&tioce_mmr->ce_ure_page_map, CE_URE_256K_PAGESIZE); | |
c9221da9 MM |
588 | tioce_kern->ce_ate3240_pagesize = KB(256); |
589 | ||
590 | for (i = 0; i < TIOCE_NUM_M40_ATES; i++) { | |
591 | tioce_kern->ce_ate40_shadow[i] = 0; | |
5fbcf9a5 | 592 | writeq(0, &tioce_mmr->ce_ure_ate40[i]); |
c9221da9 MM |
593 | } |
594 | ||
595 | for (i = 0; i < TIOCE_NUM_M3240_ATES; i++) { | |
596 | tioce_kern->ce_ate3240_shadow[i] = 0; | |
5fbcf9a5 | 597 | writeq(0, &tioce_mmr->ce_ure_ate3240[i]); |
c9221da9 MM |
598 | } |
599 | ||
600 | return tioce_kern; | |
601 | } | |
602 | ||
603 | /** | |
604 | * tioce_force_interrupt - implement altix force_interrupt() backend for CE | |
605 | * @sn_irq_info: sn asic irq that we need an interrupt generated for | |
606 | * | |
607 | * Given an sn_irq_info struct, set the proper bit in ce_adm_force_int to | |
608 | * force a secondary interrupt to be generated. This is to work around an | |
609 | * asic issue where there is a small window of opportunity for a legacy device | |
610 | * interrupt to be lost. | |
611 | */ | |
612 | static void | |
613 | tioce_force_interrupt(struct sn_irq_info *sn_irq_info) | |
614 | { | |
615 | struct pcidev_info *pcidev_info; | |
616 | struct tioce_common *ce_common; | |
617 | struct tioce *ce_mmr; | |
53493dcf | 618 | u64 force_int_val; |
c9221da9 MM |
619 | |
620 | if (!sn_irq_info->irq_bridge) | |
621 | return; | |
622 | ||
623 | if (sn_irq_info->irq_bridge_type != PCIIO_ASIC_TYPE_TIOCE) | |
624 | return; | |
625 | ||
626 | pcidev_info = (struct pcidev_info *)sn_irq_info->irq_pciioinfo; | |
627 | if (!pcidev_info) | |
628 | return; | |
629 | ||
630 | ce_common = (struct tioce_common *)pcidev_info->pdi_pcibus_info; | |
631 | ce_mmr = (struct tioce *)ce_common->ce_pcibus.bs_base; | |
632 | ||
633 | /* | |
634 | * irq_int_bit is originally set up by prom, and holds the interrupt | |
635 | * bit shift (not mask) as defined by the bit definitions in the | |
636 | * ce_adm_int mmr. These shifts are not the same for the | |
637 | * ce_adm_force_int register, so do an explicit mapping here to make | |
638 | * things clearer. | |
639 | */ | |
640 | ||
641 | switch (sn_irq_info->irq_int_bit) { | |
642 | case CE_ADM_INT_PCIE_PORT1_DEV_A_SHFT: | |
643 | force_int_val = 1UL << CE_ADM_FORCE_INT_PCIE_PORT1_DEV_A_SHFT; | |
644 | break; | |
645 | case CE_ADM_INT_PCIE_PORT1_DEV_B_SHFT: | |
646 | force_int_val = 1UL << CE_ADM_FORCE_INT_PCIE_PORT1_DEV_B_SHFT; | |
647 | break; | |
648 | case CE_ADM_INT_PCIE_PORT1_DEV_C_SHFT: | |
649 | force_int_val = 1UL << CE_ADM_FORCE_INT_PCIE_PORT1_DEV_C_SHFT; | |
650 | break; | |
651 | case CE_ADM_INT_PCIE_PORT1_DEV_D_SHFT: | |
652 | force_int_val = 1UL << CE_ADM_FORCE_INT_PCIE_PORT1_DEV_D_SHFT; | |
653 | break; | |
654 | case CE_ADM_INT_PCIE_PORT2_DEV_A_SHFT: | |
655 | force_int_val = 1UL << CE_ADM_FORCE_INT_PCIE_PORT2_DEV_A_SHFT; | |
656 | break; | |
657 | case CE_ADM_INT_PCIE_PORT2_DEV_B_SHFT: | |
658 | force_int_val = 1UL << CE_ADM_FORCE_INT_PCIE_PORT2_DEV_B_SHFT; | |
659 | break; | |
660 | case CE_ADM_INT_PCIE_PORT2_DEV_C_SHFT: | |
661 | force_int_val = 1UL << CE_ADM_FORCE_INT_PCIE_PORT2_DEV_C_SHFT; | |
662 | break; | |
663 | case CE_ADM_INT_PCIE_PORT2_DEV_D_SHFT: | |
664 | force_int_val = 1UL << CE_ADM_FORCE_INT_PCIE_PORT2_DEV_D_SHFT; | |
665 | break; | |
666 | default: | |
667 | return; | |
668 | } | |
5fbcf9a5 | 669 | writeq(force_int_val, &ce_mmr->ce_adm_force_int); |
c9221da9 MM |
670 | } |
671 | ||
8409668b MM |
672 | /** |
673 | * tioce_target_interrupt - implement set_irq_affinity for tioce resident | |
674 | * functions. Note: only applies to line interrupts, not MSI's. | |
675 | * | |
676 | * @sn_irq_info: SN IRQ context | |
677 | * | |
678 | * Given an sn_irq_info, set the associated CE device's interrupt destination | |
679 | * register. Since the interrupt destination registers are on a per-ce-slot | |
680 | * basis, this will retarget line interrupts for all functions downstream of | |
681 | * the slot. | |
682 | */ | |
683 | static void | |
684 | tioce_target_interrupt(struct sn_irq_info *sn_irq_info) | |
685 | { | |
686 | struct pcidev_info *pcidev_info; | |
687 | struct tioce_common *ce_common; | |
688 | struct tioce *ce_mmr; | |
689 | int bit; | |
53493dcf | 690 | u64 vector; |
8409668b MM |
691 | |
692 | pcidev_info = (struct pcidev_info *)sn_irq_info->irq_pciioinfo; | |
693 | if (!pcidev_info) | |
694 | return; | |
695 | ||
696 | ce_common = (struct tioce_common *)pcidev_info->pdi_pcibus_info; | |
697 | ce_mmr = (struct tioce *)ce_common->ce_pcibus.bs_base; | |
698 | ||
699 | bit = sn_irq_info->irq_int_bit; | |
700 | ||
5fbcf9a5 | 701 | __sn_setq_relaxed(&ce_mmr->ce_adm_int_mask, (1UL << bit)); |
53493dcf | 702 | vector = (u64)sn_irq_info->irq_irq << INTR_VECTOR_SHFT; |
5fbcf9a5 MM |
703 | vector |= sn_irq_info->irq_xtalkaddr; |
704 | writeq(vector, &ce_mmr->ce_adm_int_dest[bit]); | |
705 | __sn_clrq_relaxed(&ce_mmr->ce_adm_int_mask, (1UL << bit)); | |
8409668b MM |
706 | |
707 | tioce_force_interrupt(sn_irq_info); | |
708 | } | |
709 | ||
c9221da9 MM |
710 | /** |
711 | * tioce_bus_fixup - perform final PCI fixup for a TIO CE bus | |
712 | * @prom_bussoft: Common prom/kernel struct representing the bus | |
713 | * | |
714 | * Replicates the tioce_common pointed to by @prom_bussoft in kernel | |
715 | * space. Allocates and initializes a kernel-only area for a given CE, | |
716 | * and sets up an irq for handling CE error interrupts. | |
717 | * | |
718 | * On successful setup, returns the kernel version of tioce_common back to | |
719 | * the caller. | |
720 | */ | |
721 | static void * | |
722 | tioce_bus_fixup(struct pcibus_bussoft *prom_bussoft, struct pci_controller *controller) | |
723 | { | |
724 | struct tioce_common *tioce_common; | |
725 | ||
726 | /* | |
727 | * Allocate kernel bus soft and copy from prom. | |
728 | */ | |
729 | ||
baf47fb6 | 730 | tioce_common = kzalloc(sizeof(struct tioce_common), GFP_KERNEL); |
c9221da9 MM |
731 | if (!tioce_common) |
732 | return NULL; | |
733 | ||
734 | memcpy(tioce_common, prom_bussoft, sizeof(struct tioce_common)); | |
735 | tioce_common->ce_pcibus.bs_base |= __IA64_UNCACHED_OFFSET; | |
736 | ||
737 | if (tioce_kern_init(tioce_common) == NULL) { | |
738 | kfree(tioce_common); | |
739 | return NULL; | |
740 | } | |
741 | ||
742 | if (request_irq(SGI_PCIASIC_ERROR, | |
743 | tioce_error_intr_handler, | |
744 | SA_SHIRQ, "TIOCE error", (void *)tioce_common)) | |
745 | printk(KERN_WARNING | |
746 | "%s: Unable to get irq %d. " | |
747 | "Error interrupts won't be routed for " | |
748 | "TIOCE bus %04x:%02x\n", | |
749 | __FUNCTION__, SGI_PCIASIC_ERROR, | |
750 | tioce_common->ce_pcibus.bs_persist_segment, | |
751 | tioce_common->ce_pcibus.bs_persist_busnum); | |
752 | ||
753 | return tioce_common; | |
754 | } | |
755 | ||
756 | static struct sn_pcibus_provider tioce_pci_interfaces = { | |
757 | .dma_map = tioce_dma, | |
758 | .dma_map_consistent = tioce_dma_consistent, | |
759 | .dma_unmap = tioce_dma_unmap, | |
760 | .bus_fixup = tioce_bus_fixup, | |
8409668b MM |
761 | .force_interrupt = tioce_force_interrupt, |
762 | .target_interrupt = tioce_target_interrupt | |
c9221da9 MM |
763 | }; |
764 | ||
765 | /** | |
766 | * tioce_init_provider - init SN PCI provider ops for TIO CE | |
767 | */ | |
768 | int | |
769 | tioce_init_provider(void) | |
770 | { | |
771 | sn_pci_provider[PCIIO_ASIC_TYPE_TIOCE] = &tioce_pci_interfaces; | |
772 | return 0; | |
773 | } |