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b2441318 1// SPDX-License-Identifier: GPL-2.0
1da177e4
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2/*
3 * arch/m32r/boot/compressed/m32r_sio.c
4 *
5 * 2003-02-12: Takeo Takahashi
d93f7de8 6 * 2006-11-30: OPSPUT support by Kazuhiro Inaoka
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7 *
8 */
9
23680863 10#include <asm/processor.h>
1da177e4 11
9babed6a 12static void m32r_putc(char c);
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13
14static int puts(const char *s)
15{
16 char c;
9babed6a
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17 while ((c = *s++))
18 m32r_putc(c);
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19 return 0;
20}
21
7852375b 22#if defined(CONFIG_PLAT_M32700UT) || defined(CONFIG_PLAT_OPSPUT)
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23#include <asm/m32r.h>
24#include <asm/io.h>
25
26#define USE_FPGA_MAP 0
27
28#if USE_FPGA_MAP
29/*
30 * fpga configuration program uses MMU, and define map as same as
31 * M32104 uT-Engine board.
32 */
33#define BOOT_SIO0STS (volatile unsigned short *)(0x02c00000 + 0x20006)
34#define BOOT_SIO0TXB (volatile unsigned short *)(0x02c00000 + 0x2000c)
35#else
36#undef PLD_BASE
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37#if defined(CONFIG_PLAT_OPSPUT)
38#define PLD_BASE 0x1cc00000
39#else
1da177e4 40#define PLD_BASE 0xa4c00000
d93f7de8 41#endif
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42#define BOOT_SIO0STS PLD_ESIO0STS
43#define BOOT_SIO0TXB PLD_ESIO0TXB
44#endif
45
9babed6a 46static void m32r_putc(char c)
1da177e4 47{
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48 while ((*BOOT_SIO0STS & 0x3) != 0x3)
49 cpu_relax();
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50 if (c == '\n') {
51 *BOOT_SIO0TXB = '\r';
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52 while ((*BOOT_SIO0STS & 0x3) != 0x3)
53 cpu_relax();
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54 }
55 *BOOT_SIO0TXB = c;
56}
7852375b 57#else /* !(CONFIG_PLAT_M32700UT) */
23680863 58#if defined(CONFIG_PLAT_MAPPI2)
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59#define SIO0STS (volatile unsigned short *)(0xa0efd000 + 14)
60#define SIO0TXB (volatile unsigned short *)(0xa0efd000 + 30)
61#else
62#define SIO0STS (volatile unsigned short *)(0x00efd000 + 14)
63#define SIO0TXB (volatile unsigned short *)(0x00efd000 + 30)
64#endif
65
9babed6a 66static void m32r_putc(char c)
1da177e4 67{
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68 while ((*SIO0STS & 0x1) == 0)
69 cpu_relax();
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70 if (c == '\n') {
71 *SIO0TXB = '\r';
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72 while ((*SIO0STS & 0x1) == 0)
73 cpu_relax();
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74 }
75 *SIO0TXB = c;
76}
77#endif