[mirror_ubuntu-artful-kernel.git] / arch / m32r / kernel / setup_m32700ut.c

/*
 *  linux/arch/m32r/kernel/setup_m32700ut.c
 *
 *  Setup routines for Renesas M32700UT Board
 *
 *  Copyright (c) 2002 	Hiroyuki Kondo, Hirokazu Takata,
 *                      Hitoshi Yamamoto, Takeo Takahashi
 *
 *  This file is subject to the terms and conditions of the GNU General
 *  Public License.  See the file "COPYING" in the main directory of this
 *  archive for more details.
 */

#include <linux/config.h>
#include <linux/irq.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/device.h>

#include <asm/system.h>
#include <asm/m32r.h>
#include <asm/io.h>

/*
 * M32700 Interrupt Control Unit (Level 1)
 */
#define irq2port(x) (M32R_ICU_CR1_PORTL + ((x - 1) * sizeof(unsigned long)))

#ifndef CONFIG_SMP
typedef struct {
	unsigned long icucr;  /* ICU Control Register */
} icu_data_t;
#endif /* CONFIG_SMP */

static icu_data_t icu_data[M32700UT_NUM_CPU_IRQ];

static void disable_m32700ut_irq(unsigned int irq)
{
	unsigned long port, data;

	port = irq2port(irq);
	data = icu_data[irq].icucr|M32R_ICUCR_ILEVEL7;
	outl(data, port);
}

static void enable_m32700ut_irq(unsigned int irq)
{
	unsigned long port, data;

	port = irq2port(irq);
	data = icu_data[irq].icucr|M32R_ICUCR_IEN|M32R_ICUCR_ILEVEL6;
	outl(data, port);
}

static void mask_and_ack_m32700ut(unsigned int irq)
{
	disable_m32700ut_irq(irq);
}

static void end_m32700ut_irq(unsigned int irq)
{
	enable_m32700ut_irq(irq);
}

static unsigned int startup_m32700ut_irq(unsigned int irq)
{
	enable_m32700ut_irq(irq);
	return (0);
}

static void shutdown_m32700ut_irq(unsigned int irq)
{
	unsigned long port;

	port = irq2port(irq);
	outl(M32R_ICUCR_ILEVEL7, port);
}

static struct hw_interrupt_type m32700ut_irq_type =
{
	"M32700UT-IRQ",
	startup_m32700ut_irq,
	shutdown_m32700ut_irq,
	enable_m32700ut_irq,
	disable_m32700ut_irq,
	mask_and_ack_m32700ut,
	end_m32700ut_irq
};

/*
 * Interrupt Control Unit of PLD on M32700UT (Level 2)
 */
#define irq2pldirq(x)		((x) - M32700UT_PLD_IRQ_BASE)
#define pldirq2port(x)		(unsigned long)((int)PLD_ICUCR1 + \
				 (((x) - 1) * sizeof(unsigned short)))

typedef struct {
	unsigned short icucr;  /* ICU Control Register */
} pld_icu_data_t;

static pld_icu_data_t pld_icu_data[M32700UT_NUM_PLD_IRQ];

static void disable_m32700ut_pld_irq(unsigned int irq)
{
	unsigned long port, data;
	unsigned int pldirq;

	pldirq = irq2pldirq(irq);
//	disable_m32700ut_irq(M32R_IRQ_INT1);
	port = pldirq2port(pldirq);
	data = pld_icu_data[pldirq].icucr|PLD_ICUCR_ILEVEL7;
	outw(data, port);
}

static void enable_m32700ut_pld_irq(unsigned int irq)
{
	unsigned long port, data;
	unsigned int pldirq;

	pldirq = irq2pldirq(irq);
//	enable_m32700ut_irq(M32R_IRQ_INT1);
	port = pldirq2port(pldirq);
	data = pld_icu_data[pldirq].icucr|PLD_ICUCR_IEN|PLD_ICUCR_ILEVEL6;
	outw(data, port);
}

static void mask_and_ack_m32700ut_pld(unsigned int irq)
{
	disable_m32700ut_pld_irq(irq);
//	mask_and_ack_m32700ut(M32R_IRQ_INT1);
}

static void end_m32700ut_pld_irq(unsigned int irq)
{
	enable_m32700ut_pld_irq(irq);
	end_m32700ut_irq(M32R_IRQ_INT1);
}

static unsigned int startup_m32700ut_pld_irq(unsigned int irq)
{
	enable_m32700ut_pld_irq(irq);
	return (0);
}

static void shutdown_m32700ut_pld_irq(unsigned int irq)
{
	unsigned long port;
	unsigned int pldirq;

	pldirq = irq2pldirq(irq);
//	shutdown_m32700ut_irq(M32R_IRQ_INT1);
	port = pldirq2port(pldirq);
	outw(PLD_ICUCR_ILEVEL7, port);
}

static struct hw_interrupt_type m32700ut_pld_irq_type =
{
	"M32700UT-PLD-IRQ",
	startup_m32700ut_pld_irq,
	shutdown_m32700ut_pld_irq,
	enable_m32700ut_pld_irq,
	disable_m32700ut_pld_irq,
	mask_and_ack_m32700ut_pld,
	end_m32700ut_pld_irq
};

/*
 * Interrupt Control Unit of PLD on M32700UT-LAN (Level 2)
 */
#define irq2lanpldirq(x)	((x) - M32700UT_LAN_PLD_IRQ_BASE)
#define lanpldirq2port(x)	(unsigned long)((int)M32700UT_LAN_ICUCR1 + \
				 (((x) - 1) * sizeof(unsigned short)))

static pld_icu_data_t lanpld_icu_data[M32700UT_NUM_LAN_PLD_IRQ];

static void disable_m32700ut_lanpld_irq(unsigned int irq)
{
	unsigned long port, data;
	unsigned int pldirq;

	pldirq = irq2lanpldirq(irq);
	port = lanpldirq2port(pldirq);
	data = lanpld_icu_data[pldirq].icucr|PLD_ICUCR_ILEVEL7;
	outw(data, port);
}

static void enable_m32700ut_lanpld_irq(unsigned int irq)
{
	unsigned long port, data;
	unsigned int pldirq;

	pldirq = irq2lanpldirq(irq);
	port = lanpldirq2port(pldirq);
	data = lanpld_icu_data[pldirq].icucr|PLD_ICUCR_IEN|PLD_ICUCR_ILEVEL6;
	outw(data, port);
}

static void mask_and_ack_m32700ut_lanpld(unsigned int irq)
{
	disable_m32700ut_lanpld_irq(irq);
}

static void end_m32700ut_lanpld_irq(unsigned int irq)
{
	enable_m32700ut_lanpld_irq(irq);
	end_m32700ut_irq(M32R_IRQ_INT0);
}

static unsigned int startup_m32700ut_lanpld_irq(unsigned int irq)
{
	enable_m32700ut_lanpld_irq(irq);
	return (0);
}

static void shutdown_m32700ut_lanpld_irq(unsigned int irq)
{
	unsigned long port;
	unsigned int pldirq;

	pldirq = irq2lanpldirq(irq);
	port = lanpldirq2port(pldirq);
	outw(PLD_ICUCR_ILEVEL7, port);
}

static struct hw_interrupt_type m32700ut_lanpld_irq_type =
{
	"M32700UT-PLD-LAN-IRQ",
	startup_m32700ut_lanpld_irq,
	shutdown_m32700ut_lanpld_irq,
	enable_m32700ut_lanpld_irq,
	disable_m32700ut_lanpld_irq,
	mask_and_ack_m32700ut_lanpld,
	end_m32700ut_lanpld_irq
};

/*
 * Interrupt Control Unit of PLD on M32700UT-LCD (Level 2)
 */
#define irq2lcdpldirq(x)	((x) - M32700UT_LCD_PLD_IRQ_BASE)
#define lcdpldirq2port(x)	(unsigned long)((int)M32700UT_LCD_ICUCR1 + \
				 (((x) - 1) * sizeof(unsigned short)))

static pld_icu_data_t lcdpld_icu_data[M32700UT_NUM_LCD_PLD_IRQ];

static void disable_m32700ut_lcdpld_irq(unsigned int irq)
{
	unsigned long port, data;
	unsigned int pldirq;

	pldirq = irq2lcdpldirq(irq);
	port = lcdpldirq2port(pldirq);
	data = lcdpld_icu_data[pldirq].icucr|PLD_ICUCR_ILEVEL7;
	outw(data, port);
}

static void enable_m32700ut_lcdpld_irq(unsigned int irq)
{
	unsigned long port, data;
	unsigned int pldirq;

	pldirq = irq2lcdpldirq(irq);
	port = lcdpldirq2port(pldirq);
	data = lcdpld_icu_data[pldirq].icucr|PLD_ICUCR_IEN|PLD_ICUCR_ILEVEL6;
	outw(data, port);
}

static void mask_and_ack_m32700ut_lcdpld(unsigned int irq)
{
	disable_m32700ut_lcdpld_irq(irq);
}

static void end_m32700ut_lcdpld_irq(unsigned int irq)
{
	enable_m32700ut_lcdpld_irq(irq);
	end_m32700ut_irq(M32R_IRQ_INT2);
}

static unsigned int startup_m32700ut_lcdpld_irq(unsigned int irq)
{
	enable_m32700ut_lcdpld_irq(irq);
	return (0);
}

static void shutdown_m32700ut_lcdpld_irq(unsigned int irq)
{
	unsigned long port;
	unsigned int pldirq;

	pldirq = irq2lcdpldirq(irq);
	port = lcdpldirq2port(pldirq);
	outw(PLD_ICUCR_ILEVEL7, port);
}

static struct hw_interrupt_type m32700ut_lcdpld_irq_type =
{
	"M32700UT-PLD-LCD-IRQ",
	startup_m32700ut_lcdpld_irq,
	shutdown_m32700ut_lcdpld_irq,
	enable_m32700ut_lcdpld_irq,
	disable_m32700ut_lcdpld_irq,
	mask_and_ack_m32700ut_lcdpld,
	end_m32700ut_lcdpld_irq
};

void __init init_IRQ(void)
{
#if defined(CONFIG_SMC91X)
	/* INT#0: LAN controller on M32700UT-LAN (SMC91C111)*/
	irq_desc[M32700UT_LAN_IRQ_LAN].status = IRQ_DISABLED;
	irq_desc[M32700UT_LAN_IRQ_LAN].handler = &m32700ut_lanpld_irq_type;
	irq_desc[M32700UT_LAN_IRQ_LAN].action = 0;
	irq_desc[M32700UT_LAN_IRQ_LAN].depth = 1;	/* disable nested irq */
	lanpld_icu_data[irq2lanpldirq(M32700UT_LAN_IRQ_LAN)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02;	/* "H" edge sense */
	disable_m32700ut_lanpld_irq(M32700UT_LAN_IRQ_LAN);
#endif  /* CONFIG_SMC91X */

	/* MFT2 : system timer */
	irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED;
	irq_desc[M32R_IRQ_MFT2].handler = &m32700ut_irq_type;
	irq_desc[M32R_IRQ_MFT2].action = 0;
	irq_desc[M32R_IRQ_MFT2].depth = 1;
	icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
	disable_m32700ut_irq(M32R_IRQ_MFT2);

	/* SIO0 : receive */
	irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED;
	irq_desc[M32R_IRQ_SIO0_R].handler = &m32700ut_irq_type;
	irq_desc[M32R_IRQ_SIO0_R].action = 0;
	irq_desc[M32R_IRQ_SIO0_R].depth = 1;
	icu_data[M32R_IRQ_SIO0_R].icucr = 0;
	disable_m32700ut_irq(M32R_IRQ_SIO0_R);

	/* SIO0 : send */
	irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED;
	irq_desc[M32R_IRQ_SIO0_S].handler = &m32700ut_irq_type;
	irq_desc[M32R_IRQ_SIO0_S].action = 0;
	irq_desc[M32R_IRQ_SIO0_S].depth = 1;
	icu_data[M32R_IRQ_SIO0_S].icucr = 0;
	disable_m32700ut_irq(M32R_IRQ_SIO0_S);

	/* SIO1 : receive */
	irq_desc[M32R_IRQ_SIO1_R].status = IRQ_DISABLED;
	irq_desc[M32R_IRQ_SIO1_R].handler = &m32700ut_irq_type;
	irq_desc[M32R_IRQ_SIO1_R].action = 0;
	irq_desc[M32R_IRQ_SIO1_R].depth = 1;
	icu_data[M32R_IRQ_SIO1_R].icucr = 0;
	disable_m32700ut_irq(M32R_IRQ_SIO1_R);

	/* SIO1 : send */
	irq_desc[M32R_IRQ_SIO1_S].status = IRQ_DISABLED;
	irq_desc[M32R_IRQ_SIO1_S].handler = &m32700ut_irq_type;
	irq_desc[M32R_IRQ_SIO1_S].action = 0;
	irq_desc[M32R_IRQ_SIO1_S].depth = 1;
	icu_data[M32R_IRQ_SIO1_S].icucr = 0;
	disable_m32700ut_irq(M32R_IRQ_SIO1_S);

	/* DMA1 : */
	irq_desc[M32R_IRQ_DMA1].status = IRQ_DISABLED;
	irq_desc[M32R_IRQ_DMA1].handler = &m32700ut_irq_type;
	irq_desc[M32R_IRQ_DMA1].action = 0;
	irq_desc[M32R_IRQ_DMA1].depth = 1;
	icu_data[M32R_IRQ_DMA1].icucr = 0;
	disable_m32700ut_irq(M32R_IRQ_DMA1);

#ifdef CONFIG_SERIAL_M32R_PLDSIO
	/* INT#1: SIO0 Receive on PLD */
	irq_desc[PLD_IRQ_SIO0_RCV].status = IRQ_DISABLED;
	irq_desc[PLD_IRQ_SIO0_RCV].handler = &m32700ut_pld_irq_type;
	irq_desc[PLD_IRQ_SIO0_RCV].action = 0;
	irq_desc[PLD_IRQ_SIO0_RCV].depth = 1;	/* disable nested irq */
	pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_RCV)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03;
	disable_m32700ut_pld_irq(PLD_IRQ_SIO0_RCV);

	/* INT#1: SIO0 Send on PLD */
	irq_desc[PLD_IRQ_SIO0_SND].status = IRQ_DISABLED;
	irq_desc[PLD_IRQ_SIO0_SND].handler = &m32700ut_pld_irq_type;
	irq_desc[PLD_IRQ_SIO0_SND].action = 0;
	irq_desc[PLD_IRQ_SIO0_SND].depth = 1;	/* disable nested irq */
	pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_SND)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03;
	disable_m32700ut_pld_irq(PLD_IRQ_SIO0_SND);
#endif  /* CONFIG_SERIAL_M32R_PLDSIO */

	/* INT#1: CFC IREQ on PLD */
	irq_desc[PLD_IRQ_CFIREQ].status = IRQ_DISABLED;
	irq_desc[PLD_IRQ_CFIREQ].handler = &m32700ut_pld_irq_type;
	irq_desc[PLD_IRQ_CFIREQ].action = 0;
	irq_desc[PLD_IRQ_CFIREQ].depth = 1;	/* disable nested irq */
	pld_icu_data[irq2pldirq(PLD_IRQ_CFIREQ)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01;	/* 'L' level sense */
	disable_m32700ut_pld_irq(PLD_IRQ_CFIREQ);

	/* INT#1: CFC Insert on PLD */
	irq_desc[PLD_IRQ_CFC_INSERT].status = IRQ_DISABLED;
	irq_desc[PLD_IRQ_CFC_INSERT].handler = &m32700ut_pld_irq_type;
	irq_desc[PLD_IRQ_CFC_INSERT].action = 0;
	irq_desc[PLD_IRQ_CFC_INSERT].depth = 1;	/* disable nested irq */
	pld_icu_data[irq2pldirq(PLD_IRQ_CFC_INSERT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD00;	/* 'L' edge sense */
	disable_m32700ut_pld_irq(PLD_IRQ_CFC_INSERT);

	/* INT#1: CFC Eject on PLD */
	irq_desc[PLD_IRQ_CFC_EJECT].status = IRQ_DISABLED;
	irq_desc[PLD_IRQ_CFC_EJECT].handler = &m32700ut_pld_irq_type;
	irq_desc[PLD_IRQ_CFC_EJECT].action = 0;
	irq_desc[PLD_IRQ_CFC_EJECT].depth = 1;	/* disable nested irq */
	pld_icu_data[irq2pldirq(PLD_IRQ_CFC_EJECT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02;	/* 'H' edge sense */
	disable_m32700ut_pld_irq(PLD_IRQ_CFC_EJECT);

	/*
	 * INT0# is used for LAN, DIO
	 * We enable it here.
	 */
	icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD11;
	enable_m32700ut_irq(M32R_IRQ_INT0);

	/*
	 * INT1# is used for UART, MMC, CF Controller in FPGA.
	 * We enable it here.
	 */
	icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD11;
	enable_m32700ut_irq(M32R_IRQ_INT1);

#if defined(CONFIG_USB)
	outw(USBCR_OTGS, USBCR); 	/* USBCR: non-OTG */

    irq_desc[M32700UT_LCD_IRQ_USB_INT1].status = IRQ_DISABLED;
    irq_desc[M32700UT_LCD_IRQ_USB_INT1].handler = &m32700ut_lcdpld_irq_type;
    irq_desc[M32700UT_LCD_IRQ_USB_INT1].action = 0;
    irq_desc[M32700UT_LCD_IRQ_USB_INT1].depth = 1;
    lcdpld_icu_data[irq2lcdpldirq(M32700UT_LCD_IRQ_USB_INT1)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01;	/* "L" level sense */
    disable_m32700ut_lcdpld_irq(M32700UT_LCD_IRQ_USB_INT1);
#endif
	/*
	 * INT2# is used for BAT, USB, AUDIO
	 * We enable it here.
	 */
	icu_data[M32R_IRQ_INT2].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD01;
	enable_m32700ut_irq(M32R_IRQ_INT2);

//#if defined(CONFIG_VIDEO_M32R_AR)
	/*
	 * INT3# is used for AR
	 */
	irq_desc[M32R_IRQ_INT3].status = IRQ_DISABLED;
	irq_desc[M32R_IRQ_INT3].handler = &m32700ut_irq_type;
	irq_desc[M32R_IRQ_INT3].action = 0;
	irq_desc[M32R_IRQ_INT3].depth = 1;
	icu_data[M32R_IRQ_INT3].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10;
	disable_m32700ut_irq(M32R_IRQ_INT3);
//#endif	/* CONFIG_VIDEO_M32R_AR */
}

#define LAN_IOSTART     0x300
#define LAN_IOEND       0x320
static struct resource smc91x_resources[] = {
	[0] = {
		.start  = (LAN_IOSTART),
		.end    = (LAN_IOEND),
		.flags  = IORESOURCE_MEM,
	},
	[1] = {
		.start  = M32700UT_LAN_IRQ_LAN,
		.end    = M32700UT_LAN_IRQ_LAN,
		.flags  = IORESOURCE_IRQ,
	}
};

static struct platform_device smc91x_device = {
	.name		= "smc91x",
	.id		= 0,
	.num_resources  = ARRAY_SIZE(smc91x_resources),
	.resource       = smc91x_resources,
};

static int __init platform_init(void)
{
	platform_device_register(&smc91x_device);
	return 0;
}
arch_initcall(platform_init);
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/arch/m32r/kernel/setup_m32700ut.c
	3	*
	4	* Setup routines for Renesas M32700UT Board
	5	*
	6	* Copyright (c) 2002 Hiroyuki Kondo, Hirokazu Takata,
	7	* Hitoshi Yamamoto, Takeo Takahashi
	8	*
	9	* This file is subject to the terms and conditions of the GNU General
	10	* Public License. See the file "COPYING" in the main directory of this
	11	* archive for more details.
	12	*/
	13
	14	#include <linux/config.h>
	15	#include <linux/irq.h>
	16	#include <linux/kernel.h>
	17	#include <linux/init.h>
	18	#include <linux/device.h>
	19
	20	#include <asm/system.h>
	21	#include <asm/m32r.h>
	22	#include <asm/io.h>
	23
	24	/*
	25	* M32700 Interrupt Control Unit (Level 1)
	26	*/
	27	#define irq2port(x) (M32R_ICU_CR1_PORTL + ((x - 1) * sizeof(unsigned long)))
	28
	29	#ifndef CONFIG_SMP
	30	typedef struct {
	31	unsigned long icucr; /* ICU Control Register */
	32	} icu_data_t;
	33	#endif /* CONFIG_SMP */
	34
	35	static icu_data_t icu_data[M32700UT_NUM_CPU_IRQ];
	36
	37	static void disable_m32700ut_irq(unsigned int irq)
	38	{
	39	unsigned long port, data;
	40
	41	port = irq2port(irq);
	42	data = icu_data[irq].icucr\|M32R_ICUCR_ILEVEL7;
	43	outl(data, port);
	44	}
	45
	46	static void enable_m32700ut_irq(unsigned int irq)
	47	{
	48	unsigned long port, data;
	49
	50	port = irq2port(irq);
	51	data = icu_data[irq].icucr\|M32R_ICUCR_IEN\|M32R_ICUCR_ILEVEL6;
	52	outl(data, port);
	53	}
	54
	55	static void mask_and_ack_m32700ut(unsigned int irq)
	56	{
	57	disable_m32700ut_irq(irq);
	58	}
	59
	60	static void end_m32700ut_irq(unsigned int irq)
	61	{
	62	enable_m32700ut_irq(irq);
	63	}
	64
65	static unsigned int startup_m32700ut_irq(unsigned int irq)
66	{
67	enable_m32700ut_irq(irq);
68	return (0);
69	}
70
71	static void shutdown_m32700ut_irq(unsigned int irq)
72	{
73	unsigned long port;
74
75	port = irq2port(irq);
76	outl(M32R_ICUCR_ILEVEL7, port);
77	}
78
79	static struct hw_interrupt_type m32700ut_irq_type =
80	{
81	"M32700UT-IRQ",
82	startup_m32700ut_irq,
83	shutdown_m32700ut_irq,
84	enable_m32700ut_irq,
85	disable_m32700ut_irq,
86	mask_and_ack_m32700ut,
87	end_m32700ut_irq
88	};
89
90	/*
91	* Interrupt Control Unit of PLD on M32700UT (Level 2)
92	*/
93	#define irq2pldirq(x) ((x) - M32700UT_PLD_IRQ_BASE)
94	#define pldirq2port(x) (unsigned long)((int)PLD_ICUCR1 + \
95	(((x) - 1) * sizeof(unsigned short)))
96
97	typedef struct {
98	unsigned short icucr; /* ICU Control Register */
99	} pld_icu_data_t;
100
101	static pld_icu_data_t pld_icu_data[M32700UT_NUM_PLD_IRQ];
102
103	static void disable_m32700ut_pld_irq(unsigned int irq)
104	{
105	unsigned long port, data;
106	unsigned int pldirq;
107
108	pldirq = irq2pldirq(irq);
109	// disable_m32700ut_irq(M32R_IRQ_INT1);
110	port = pldirq2port(pldirq);
111	data = pld_icu_data[pldirq].icucr\|PLD_ICUCR_ILEVEL7;
112	outw(data, port);
113	}
114
115	static void enable_m32700ut_pld_irq(unsigned int irq)
116	{
117	unsigned long port, data;
118	unsigned int pldirq;
119
120	pldirq = irq2pldirq(irq);
121	// enable_m32700ut_irq(M32R_IRQ_INT1);
122	port = pldirq2port(pldirq);
123	data = pld_icu_data[pldirq].icucr\|PLD_ICUCR_IEN\|PLD_ICUCR_ILEVEL6;
124	outw(data, port);
125	}
126
127	static void mask_and_ack_m32700ut_pld(unsigned int irq)
128	{
129	disable_m32700ut_pld_irq(irq);
130	// mask_and_ack_m32700ut(M32R_IRQ_INT1);
131	}
132
133	static void end_m32700ut_pld_irq(unsigned int irq)
134	{
135	enable_m32700ut_pld_irq(irq);
136	end_m32700ut_irq(M32R_IRQ_INT1);
137	}
138
139	static unsigned int startup_m32700ut_pld_irq(unsigned int irq)
140	{
141	enable_m32700ut_pld_irq(irq);
142	return (0);
143	}
144
145	static void shutdown_m32700ut_pld_irq(unsigned int irq)
146	{
147	unsigned long port;
148	unsigned int pldirq;
149
150	pldirq = irq2pldirq(irq);
151	// shutdown_m32700ut_irq(M32R_IRQ_INT1);
152	port = pldirq2port(pldirq);
153	outw(PLD_ICUCR_ILEVEL7, port);
154	}
155
156	static struct hw_interrupt_type m32700ut_pld_irq_type =
157	{
158	"M32700UT-PLD-IRQ",
159	startup_m32700ut_pld_irq,
160	shutdown_m32700ut_pld_irq,
161	enable_m32700ut_pld_irq,
162	disable_m32700ut_pld_irq,
163	mask_and_ack_m32700ut_pld,
164	end_m32700ut_pld_irq
165	};
166
167	/*
168	* Interrupt Control Unit of PLD on M32700UT-LAN (Level 2)
169	*/
170	#define irq2lanpldirq(x) ((x) - M32700UT_LAN_PLD_IRQ_BASE)
171	#define lanpldirq2port(x) (unsigned long)((int)M32700UT_LAN_ICUCR1 + \
172	(((x) - 1) * sizeof(unsigned short)))
173
174	static pld_icu_data_t lanpld_icu_data[M32700UT_NUM_LAN_PLD_IRQ];
175
176	static void disable_m32700ut_lanpld_irq(unsigned int irq)
177	{
178	unsigned long port, data;
179	unsigned int pldirq;
180
181	pldirq = irq2lanpldirq(irq);
182	port = lanpldirq2port(pldirq);
183	data = lanpld_icu_data[pldirq].icucr\|PLD_ICUCR_ILEVEL7;
184	outw(data, port);
185	}
186
187	static void enable_m32700ut_lanpld_irq(unsigned int irq)
188	{
189	unsigned long port, data;
190	unsigned int pldirq;
191
192	pldirq = irq2lanpldirq(irq);
193	port = lanpldirq2port(pldirq);
194	data = lanpld_icu_data[pldirq].icucr\|PLD_ICUCR_IEN\|PLD_ICUCR_ILEVEL6;
195	outw(data, port);
196	}
197
198	static void mask_and_ack_m32700ut_lanpld(unsigned int irq)
199	{
200	disable_m32700ut_lanpld_irq(irq);
201	}
202
203	static void end_m32700ut_lanpld_irq(unsigned int irq)
204	{
205	enable_m32700ut_lanpld_irq(irq);
206	end_m32700ut_irq(M32R_IRQ_INT0);
207	}
208
209	static unsigned int startup_m32700ut_lanpld_irq(unsigned int irq)
210	{
211	enable_m32700ut_lanpld_irq(irq);
212	return (0);
213	}
214
215	static void shutdown_m32700ut_lanpld_irq(unsigned int irq)
216	{
217	unsigned long port;
218	unsigned int pldirq;
219
220	pldirq = irq2lanpldirq(irq);
221	port = lanpldirq2port(pldirq);
222	outw(PLD_ICUCR_ILEVEL7, port);
223	}
224
225	static struct hw_interrupt_type m32700ut_lanpld_irq_type =
226	{
227	"M32700UT-PLD-LAN-IRQ",
228	startup_m32700ut_lanpld_irq,
229	shutdown_m32700ut_lanpld_irq,
230	enable_m32700ut_lanpld_irq,
231	disable_m32700ut_lanpld_irq,
232	mask_and_ack_m32700ut_lanpld,
233	end_m32700ut_lanpld_irq
234	};
235
236	/*
237	* Interrupt Control Unit of PLD on M32700UT-LCD (Level 2)
238	*/
239	#define irq2lcdpldirq(x) ((x) - M32700UT_LCD_PLD_IRQ_BASE)
240	#define lcdpldirq2port(x) (unsigned long)((int)M32700UT_LCD_ICUCR1 + \
241	(((x) - 1) * sizeof(unsigned short)))
242
243	static pld_icu_data_t lcdpld_icu_data[M32700UT_NUM_LCD_PLD_IRQ];
244
245	static void disable_m32700ut_lcdpld_irq(unsigned int irq)
246	{
247	unsigned long port, data;
248	unsigned int pldirq;
249
250	pldirq = irq2lcdpldirq(irq);
251	port = lcdpldirq2port(pldirq);
252	data = lcdpld_icu_data[pldirq].icucr\|PLD_ICUCR_ILEVEL7;
253	outw(data, port);
254	}
255
256	static void enable_m32700ut_lcdpld_irq(unsigned int irq)
257	{
258	unsigned long port, data;
259	unsigned int pldirq;
260
261	pldirq = irq2lcdpldirq(irq);
262	port = lcdpldirq2port(pldirq);
263	data = lcdpld_icu_data[pldirq].icucr\|PLD_ICUCR_IEN\|PLD_ICUCR_ILEVEL6;
264	outw(data, port);
265	}
266
267	static void mask_and_ack_m32700ut_lcdpld(unsigned int irq)
268	{
269	disable_m32700ut_lcdpld_irq(irq);
270	}
271
272	static void end_m32700ut_lcdpld_irq(unsigned int irq)
273	{
274	enable_m32700ut_lcdpld_irq(irq);
275	end_m32700ut_irq(M32R_IRQ_INT2);
276	}
277
278	static unsigned int startup_m32700ut_lcdpld_irq(unsigned int irq)
279	{
280	enable_m32700ut_lcdpld_irq(irq);
281	return (0);
282	}
283
284	static void shutdown_m32700ut_lcdpld_irq(unsigned int irq)
285	{
286	unsigned long port;
287	unsigned int pldirq;
288
289	pldirq = irq2lcdpldirq(irq);
290	port = lcdpldirq2port(pldirq);
291	outw(PLD_ICUCR_ILEVEL7, port);
292	}
293
294	static struct hw_interrupt_type m32700ut_lcdpld_irq_type =
295	{
296	"M32700UT-PLD-LCD-IRQ",
297	startup_m32700ut_lcdpld_irq,
298	shutdown_m32700ut_lcdpld_irq,
299	enable_m32700ut_lcdpld_irq,
300	disable_m32700ut_lcdpld_irq,
301	mask_and_ack_m32700ut_lcdpld,
302	end_m32700ut_lcdpld_irq
303	};
304
305	void __init init_IRQ(void)
306	{
307	#if defined(CONFIG_SMC91X)
308	/* INT#0: LAN controller on M32700UT-LAN (SMC91C111)*/
309	irq_desc[M32700UT_LAN_IRQ_LAN].status = IRQ_DISABLED;
310	irq_desc[M32700UT_LAN_IRQ_LAN].handler = &m32700ut_lanpld_irq_type;
311	irq_desc[M32700UT_LAN_IRQ_LAN].action = 0;
312	irq_desc[M32700UT_LAN_IRQ_LAN].depth = 1; /* disable nested irq */
313	lanpld_icu_data[irq2lanpldirq(M32700UT_LAN_IRQ_LAN)].icucr = PLD_ICUCR_IEN\|PLD_ICUCR_ISMOD02; /* "H" edge sense */
314	disable_m32700ut_lanpld_irq(M32700UT_LAN_IRQ_LAN);
315	#endif /* CONFIG_SMC91X */
316
317	/* MFT2 : system timer */
318	irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED;
319	irq_desc[M32R_IRQ_MFT2].handler = &m32700ut_irq_type;
320	irq_desc[M32R_IRQ_MFT2].action = 0;
321	irq_desc[M32R_IRQ_MFT2].depth = 1;
322	icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
323	disable_m32700ut_irq(M32R_IRQ_MFT2);
324
325	/* SIO0 : receive */
326	irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED;
327	irq_desc[M32R_IRQ_SIO0_R].handler = &m32700ut_irq_type;
328	irq_desc[M32R_IRQ_SIO0_R].action = 0;
329	irq_desc[M32R_IRQ_SIO0_R].depth = 1;
330	icu_data[M32R_IRQ_SIO0_R].icucr = 0;
331	disable_m32700ut_irq(M32R_IRQ_SIO0_R);
332
333	/* SIO0 : send */
334	irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED;
335	irq_desc[M32R_IRQ_SIO0_S].handler = &m32700ut_irq_type;
336	irq_desc[M32R_IRQ_SIO0_S].action = 0;
337	irq_desc[M32R_IRQ_SIO0_S].depth = 1;
338	icu_data[M32R_IRQ_SIO0_S].icucr = 0;
339	disable_m32700ut_irq(M32R_IRQ_SIO0_S);
340
341	/* SIO1 : receive */
342	irq_desc[M32R_IRQ_SIO1_R].status = IRQ_DISABLED;
343	irq_desc[M32R_IRQ_SIO1_R].handler = &m32700ut_irq_type;
344	irq_desc[M32R_IRQ_SIO1_R].action = 0;
345	irq_desc[M32R_IRQ_SIO1_R].depth = 1;
346	icu_data[M32R_IRQ_SIO1_R].icucr = 0;
347	disable_m32700ut_irq(M32R_IRQ_SIO1_R);
348
349	/* SIO1 : send */
350	irq_desc[M32R_IRQ_SIO1_S].status = IRQ_DISABLED;
351	irq_desc[M32R_IRQ_SIO1_S].handler = &m32700ut_irq_type;
352	irq_desc[M32R_IRQ_SIO1_S].action = 0;
353	irq_desc[M32R_IRQ_SIO1_S].depth = 1;
354	icu_data[M32R_IRQ_SIO1_S].icucr = 0;
355	disable_m32700ut_irq(M32R_IRQ_SIO1_S);
356
357	/* DMA1 : */
358	irq_desc[M32R_IRQ_DMA1].status = IRQ_DISABLED;
359	irq_desc[M32R_IRQ_DMA1].handler = &m32700ut_irq_type;
360	irq_desc[M32R_IRQ_DMA1].action = 0;
361	irq_desc[M32R_IRQ_DMA1].depth = 1;
362	icu_data[M32R_IRQ_DMA1].icucr = 0;
363	disable_m32700ut_irq(M32R_IRQ_DMA1);
364
365	#ifdef CONFIG_SERIAL_M32R_PLDSIO
366	/* INT#1: SIO0 Receive on PLD */
367	irq_desc[PLD_IRQ_SIO0_RCV].status = IRQ_DISABLED;
368	irq_desc[PLD_IRQ_SIO0_RCV].handler = &m32700ut_pld_irq_type;
369	irq_desc[PLD_IRQ_SIO0_RCV].action = 0;
370	irq_desc[PLD_IRQ_SIO0_RCV].depth = 1; /* disable nested irq */
371	pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_RCV)].icucr = PLD_ICUCR_IEN\|PLD_ICUCR_ISMOD03;
372	disable_m32700ut_pld_irq(PLD_IRQ_SIO0_RCV);
373
374	/* INT#1: SIO0 Send on PLD */
375	irq_desc[PLD_IRQ_SIO0_SND].status = IRQ_DISABLED;
376	irq_desc[PLD_IRQ_SIO0_SND].handler = &m32700ut_pld_irq_type;
377	irq_desc[PLD_IRQ_SIO0_SND].action = 0;
378	irq_desc[PLD_IRQ_SIO0_SND].depth = 1; /* disable nested irq */
379	pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_SND)].icucr = PLD_ICUCR_IEN\|PLD_ICUCR_ISMOD03;
380	disable_m32700ut_pld_irq(PLD_IRQ_SIO0_SND);
381	#endif /* CONFIG_SERIAL_M32R_PLDSIO */
382
383	/* INT#1: CFC IREQ on PLD */
384	irq_desc[PLD_IRQ_CFIREQ].status = IRQ_DISABLED;
385	irq_desc[PLD_IRQ_CFIREQ].handler = &m32700ut_pld_irq_type;
386	irq_desc[PLD_IRQ_CFIREQ].action = 0;
387	irq_desc[PLD_IRQ_CFIREQ].depth = 1; /* disable nested irq */
388	pld_icu_data[irq2pldirq(PLD_IRQ_CFIREQ)].icucr = PLD_ICUCR_IEN\|PLD_ICUCR_ISMOD01; /* 'L' level sense */
389	disable_m32700ut_pld_irq(PLD_IRQ_CFIREQ);
390
391	/* INT#1: CFC Insert on PLD */
392	irq_desc[PLD_IRQ_CFC_INSERT].status = IRQ_DISABLED;
393	irq_desc[PLD_IRQ_CFC_INSERT].handler = &m32700ut_pld_irq_type;
394	irq_desc[PLD_IRQ_CFC_INSERT].action = 0;
395	irq_desc[PLD_IRQ_CFC_INSERT].depth = 1; /* disable nested irq */
396	pld_icu_data[irq2pldirq(PLD_IRQ_CFC_INSERT)].icucr = PLD_ICUCR_IEN\|PLD_ICUCR_ISMOD00; /* 'L' edge sense */
397	disable_m32700ut_pld_irq(PLD_IRQ_CFC_INSERT);
398
399	/* INT#1: CFC Eject on PLD */
400	irq_desc[PLD_IRQ_CFC_EJECT].status = IRQ_DISABLED;
401	irq_desc[PLD_IRQ_CFC_EJECT].handler = &m32700ut_pld_irq_type;
402	irq_desc[PLD_IRQ_CFC_EJECT].action = 0;
403	irq_desc[PLD_IRQ_CFC_EJECT].depth = 1; /* disable nested irq */
404	pld_icu_data[irq2pldirq(PLD_IRQ_CFC_EJECT)].icucr = PLD_ICUCR_IEN\|PLD_ICUCR_ISMOD02; /* 'H' edge sense */
405	disable_m32700ut_pld_irq(PLD_IRQ_CFC_EJECT);
406
407	/*
408	* INT0# is used for LAN, DIO
409	* We enable it here.
410	*/
411	icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN\|M32R_ICUCR_ISMOD11;
412	enable_m32700ut_irq(M32R_IRQ_INT0);
413
414	/*
415	* INT1# is used for UART, MMC, CF Controller in FPGA.
416	* We enable it here.
417	*/
418	icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_IEN\|M32R_ICUCR_ISMOD11;
419	enable_m32700ut_irq(M32R_IRQ_INT1);
420
421	#if defined(CONFIG_USB)
422	outw(USBCR_OTGS, USBCR); /* USBCR: non-OTG */
423
424	irq_desc[M32700UT_LCD_IRQ_USB_INT1].status = IRQ_DISABLED;
425	irq_desc[M32700UT_LCD_IRQ_USB_INT1].handler = &m32700ut_lcdpld_irq_type;
426	irq_desc[M32700UT_LCD_IRQ_USB_INT1].action = 0;
427	irq_desc[M32700UT_LCD_IRQ_USB_INT1].depth = 1;
428	lcdpld_icu_data[irq2lcdpldirq(M32700UT_LCD_IRQ_USB_INT1)].icucr = PLD_ICUCR_IEN\|PLD_ICUCR_ISMOD01; /* "L" level sense */
429	disable_m32700ut_lcdpld_irq(M32700UT_LCD_IRQ_USB_INT1);
430	#endif
431	/*
432	* INT2# is used for BAT, USB, AUDIO
433	* We enable it here.
434	*/
435	icu_data[M32R_IRQ_INT2].icucr = M32R_ICUCR_IEN\|M32R_ICUCR_ISMOD01;
436	enable_m32700ut_irq(M32R_IRQ_INT2);
437
438	//#if defined(CONFIG_VIDEO_M32R_AR)
439	/*
440	* INT3# is used for AR
441	*/
442	irq_desc[M32R_IRQ_INT3].status = IRQ_DISABLED;
443	irq_desc[M32R_IRQ_INT3].handler = &m32700ut_irq_type;
444	irq_desc[M32R_IRQ_INT3].action = 0;
445	irq_desc[M32R_IRQ_INT3].depth = 1;
446	icu_data[M32R_IRQ_INT3].icucr = M32R_ICUCR_IEN\|M32R_ICUCR_ISMOD10;
447	disable_m32700ut_irq(M32R_IRQ_INT3);
448	//#endif /* CONFIG_VIDEO_M32R_AR */
449	}
450
451	#define LAN_IOSTART 0x300
452	#define LAN_IOEND 0x320
453	static struct resource smc91x_resources[] = {
454	[0] = {
455	.start = (LAN_IOSTART),
456	.end = (LAN_IOEND),
457	.flags = IORESOURCE_MEM,
458	},
459	[1] = {
460	.start = M32700UT_LAN_IRQ_LAN,
461	.end = M32700UT_LAN_IRQ_LAN,
462	.flags = IORESOURCE_IRQ,
463	}
464	};
465
466	static struct platform_device smc91x_device = {
467	.name = "smc91x",
468	.id = 0,
469	.num_resources = ARRAY_SIZE(smc91x_resources),
470	.resource = smc91x_resources,
471	};
472
473	static int __init platform_init(void)
474	{
475	platform_device_register(&smc91x_device);
476	return 0;
477	}
478	arch_initcall(platform_init);