[mirror_ubuntu-bionic-kernel.git] / arch / m32r / platforms / mappi2 / setup.c

// SPDX-License-Identifier: GPL-2.0
/*
 *  linux/arch/m32r/platforms/mappi2/setup.c
 *
 *  Setup routines for Renesas MAPPI-II(M3A-ZA36) Board
 *
 *  Copyright (c) 2001-2005  Hiroyuki Kondo, Hirokazu Takata,
 *                           Hitoshi Yamamoto, Mamoru Sakugawa
 */

#include <linux/irq.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>

#include <asm/m32r.h>
#include <asm/io.h>

#define irq2port(x) (M32R_ICU_CR1_PORTL + ((x - 1) * sizeof(unsigned long)))

icu_data_t icu_data[NR_IRQS];

static void disable_mappi2_irq(unsigned int irq)
{
	unsigned long port, data;

	if ((irq == 0) ||(irq >= NR_IRQS))  {
		printk("bad irq 0x%08x\n", irq);
		return;
	}
	port = irq2port(irq);
	data = icu_data[irq].icucr|M32R_ICUCR_ILEVEL7;
	outl(data, port);
}

static void enable_mappi2_irq(unsigned int irq)
{
	unsigned long port, data;

	if ((irq == 0) ||(irq >= NR_IRQS))  {
		printk("bad irq 0x%08x\n", irq);
		return;
	}
	port = irq2port(irq);
	data = icu_data[irq].icucr|M32R_ICUCR_IEN|M32R_ICUCR_ILEVEL6;
	outl(data, port);
}

static void mask_mappi2(struct irq_data *data)
{
	disable_mappi2_irq(data->irq);
}

static void unmask_mappi2(struct irq_data *data)
{
	enable_mappi2_irq(data->irq);
}

static void shutdown_mappi2(struct irq_data *data)
{
	unsigned long port;

	port = irq2port(data->irq);
	outl(M32R_ICUCR_ILEVEL7, port);
}

static struct irq_chip mappi2_irq_type =
{
	.name		= "MAPPI2-IRQ",
	.irq_shutdown	= shutdown_mappi2,
	.irq_mask	= mask_mappi2,
	.irq_unmask	= unmask_mappi2,
};

void __init init_IRQ(void)
{
#if defined(CONFIG_SMC91X)
	/* INT0 : LAN controller (SMC91111) */
	irq_set_chip_and_handler(M32R_IRQ_INT0, &mappi2_irq_type,
				 handle_level_irq);
	icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10;
	disable_mappi2_irq(M32R_IRQ_INT0);
#endif  /* CONFIG_SMC91X */

	/* MFT2 : system timer */
	irq_set_chip_and_handler(M32R_IRQ_MFT2, &mappi2_irq_type,
				 handle_level_irq);
	icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
	disable_mappi2_irq(M32R_IRQ_MFT2);

#ifdef CONFIG_SERIAL_M32R_SIO
	/* SIO0_R : uart receive data */
	irq_set_chip_and_handler(M32R_IRQ_SIO0_R, &mappi2_irq_type,
				 handle_level_irq);
	icu_data[M32R_IRQ_SIO0_R].icucr = 0;
	disable_mappi2_irq(M32R_IRQ_SIO0_R);

	/* SIO0_S : uart send data */
	irq_set_chip_and_handler(M32R_IRQ_SIO0_S, &mappi2_irq_type,
				 handle_level_irq);
	icu_data[M32R_IRQ_SIO0_S].icucr = 0;
	disable_mappi2_irq(M32R_IRQ_SIO0_S);
	/* SIO1_R : uart receive data */
	irq_set_chip_and_handler(M32R_IRQ_SIO1_R, &mappi2_irq_type,
				 handle_level_irq);
	icu_data[M32R_IRQ_SIO1_R].icucr = 0;
	disable_mappi2_irq(M32R_IRQ_SIO1_R);

	/* SIO1_S : uart send data */
	irq_set_chip_and_handler(M32R_IRQ_SIO1_S, &mappi2_irq_type,
				 handle_level_irq);
	icu_data[M32R_IRQ_SIO1_S].icucr = 0;
	disable_mappi2_irq(M32R_IRQ_SIO1_S);
#endif  /* CONFIG_M32R_USE_DBG_CONSOLE */

#if defined(CONFIG_USB)
	/* INT1 : USB Host controller interrupt */
	irq_set_chip_and_handler(M32R_IRQ_INT1, &mappi2_irq_type,
				 handle_level_irq);
	icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_ISMOD01;
	disable_mappi2_irq(M32R_IRQ_INT1);
#endif /* CONFIG_USB */

	/* ICUCR40: CFC IREQ */
	irq_set_chip_and_handler(PLD_IRQ_CFIREQ, &mappi2_irq_type,
				 handle_level_irq);
	icu_data[PLD_IRQ_CFIREQ].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD01;
	disable_mappi2_irq(PLD_IRQ_CFIREQ);

#if defined(CONFIG_M32R_CFC)
	/* ICUCR41: CFC Insert */
	irq_set_chip_and_handler(PLD_IRQ_CFC_INSERT, &mappi2_irq_type,
				 handle_level_irq);
	icu_data[PLD_IRQ_CFC_INSERT].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD00;
	disable_mappi2_irq(PLD_IRQ_CFC_INSERT);

	/* ICUCR42: CFC Eject */
	irq_set_chip_and_handler(PLD_IRQ_CFC_EJECT, &mappi2_irq_type,
				 handle_level_irq);
	icu_data[PLD_IRQ_CFC_EJECT].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10;
	disable_mappi2_irq(PLD_IRQ_CFC_EJECT);
#endif /* CONFIG_MAPPI2_CFC */
}

#define LAN_IOSTART     0x300
#define LAN_IOEND       0x320
static struct resource smc91x_resources[] = {
	[0] = {
		.start  = (LAN_IOSTART),
		.end    = (LAN_IOEND),
		.flags  = IORESOURCE_MEM,
	},
	[1] = {
		.start  = M32R_IRQ_INT0,
		.end    = M32R_IRQ_INT0,
		.flags  = IORESOURCE_IRQ,
	}
};

static struct platform_device smc91x_device = {
	.name		= "smc91x",
	.id		= 0,
	.num_resources  = ARRAY_SIZE(smc91x_resources),
	.resource       = smc91x_resources,
};

static int __init platform_init(void)
{
	platform_device_register(&smc91x_device);
	return 0;
}
arch_initcall(platform_init);
Commit	Line	Data
b2441318	1	// SPDX-License-Identifier: GPL-2.0
1da177e4	2	/*
3264f976	3	* linux/arch/m32r/platforms/mappi2/setup.c
1da177e4 LT	4	*
	5	* Setup routines for Renesas MAPPI-II(M3A-ZA36) Board
	6	*
316240f6 HT	7	* Copyright (c) 2001-2005 Hiroyuki Kondo, Hirokazu Takata,
316240f6 HT	8	* Hitoshi Yamamoto, Mamoru Sakugawa
1da177e4 LT	9	*/
1da177e4 LT	10
1da177e4 LT	11	#include <linux/irq.h>
	12	#include <linux/kernel.h>
	13	#include <linux/init.h>
d052d1be	14	#include <linux/platform_device.h>
1da177e4	15
1da177e4 LT	16	#include <asm/m32r.h>
	17	#include <asm/io.h>
	18
	19	#define irq2port(x) (M32R_ICU_CR1_PORTL + ((x - 1) * sizeof(unsigned long)))
	20
1da177e4 LT	21	icu_data_t icu_data[NR_IRQS];
	22
	23	static void disable_mappi2_irq(unsigned int irq)
	24	{
	25	unsigned long port, data;
	26
	27	if ((irq == 0) \|\|(irq >= NR_IRQS)) {
	28	printk("bad irq 0x%08x\n", irq);
	29	return;
	30	}
	31	port = irq2port(irq);
	32	data = icu_data[irq].icucr\|M32R_ICUCR_ILEVEL7;
	33	outl(data, port);
	34	}
	35
	36	static void enable_mappi2_irq(unsigned int irq)
	37	{
	38	unsigned long port, data;
	39
	40	if ((irq == 0) \|\|(irq >= NR_IRQS)) {
	41	printk("bad irq 0x%08x\n", irq);
	42	return;
	43	}
	44	port = irq2port(irq);
	45	data = icu_data[irq].icucr\|M32R_ICUCR_IEN\|M32R_ICUCR_ILEVEL6;
	46	outl(data, port);
	47	}
	48
efa63c64	49	static void mask_mappi2(struct irq_data *data)
1da177e4	50	{
efa63c64	51	disable_mappi2_irq(data->irq);
1da177e4 LT	52	}
1da177e4 LT	53
efa63c64	54	static void unmask_mappi2(struct irq_data *data)
1da177e4	55	{
efa63c64	56	enable_mappi2_irq(data->irq);
1da177e4 LT	57	}
1da177e4 LT	58
efa63c64	59	static void shutdown_mappi2(struct irq_data *data)
1da177e4 LT	60	{
	61	unsigned long port;
	62
efa63c64	63	port = irq2port(data->irq);
1da177e4 LT	64	outl(M32R_ICUCR_ILEVEL7, port);
	65	}
	66
189e91f5	67	static struct irq_chip mappi2_irq_type =
1da177e4	68	{
efa63c64 TG	69	.name = "MAPPI2-IRQ",
	70	.irq_shutdown = shutdown_mappi2,
	71	.irq_mask = mask_mappi2,
	72	.irq_unmask = unmask_mappi2,
1da177e4 LT	73	};
	74
	75	void __init init_IRQ(void)
	76	{
	77	#if defined(CONFIG_SMC91X)
	78	/* INT0 : LAN controller (SMC91111) */
27e5c5a9	79	irq_set_chip_and_handler(M32R_IRQ_INT0, &mappi2_irq_type,
efa63c64	80	handle_level_irq);
1da177e4 LT	81	icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN\|M32R_ICUCR_ISMOD10;
	82	disable_mappi2_irq(M32R_IRQ_INT0);
	83	#endif /* CONFIG_SMC91X */
	84
	85	/* MFT2 : system timer */
27e5c5a9	86	irq_set_chip_and_handler(M32R_IRQ_MFT2, &mappi2_irq_type,
efa63c64	87	handle_level_irq);
1da177e4 LT	88	icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
	89	disable_mappi2_irq(M32R_IRQ_MFT2);
	90
	91	#ifdef CONFIG_SERIAL_M32R_SIO
	92	/* SIO0_R : uart receive data */
27e5c5a9	93	irq_set_chip_and_handler(M32R_IRQ_SIO0_R, &mappi2_irq_type,
efa63c64	94	handle_level_irq);
1da177e4 LT	95	icu_data[M32R_IRQ_SIO0_R].icucr = 0;
	96	disable_mappi2_irq(M32R_IRQ_SIO0_R);
	97
	98	/* SIO0_S : uart send data */
27e5c5a9	99	irq_set_chip_and_handler(M32R_IRQ_SIO0_S, &mappi2_irq_type,
efa63c64	100	handle_level_irq);
1da177e4 LT	101	icu_data[M32R_IRQ_SIO0_S].icucr = 0;
	102	disable_mappi2_irq(M32R_IRQ_SIO0_S);
	103	/* SIO1_R : uart receive data */
27e5c5a9	104	irq_set_chip_and_handler(M32R_IRQ_SIO1_R, &mappi2_irq_type,
efa63c64	105	handle_level_irq);
1da177e4 LT	106	icu_data[M32R_IRQ_SIO1_R].icucr = 0;
	107	disable_mappi2_irq(M32R_IRQ_SIO1_R);
	108
	109	/* SIO1_S : uart send data */
27e5c5a9	110	irq_set_chip_and_handler(M32R_IRQ_SIO1_S, &mappi2_irq_type,
efa63c64	111	handle_level_irq);
1da177e4 LT	112	icu_data[M32R_IRQ_SIO1_S].icucr = 0;
	113	disable_mappi2_irq(M32R_IRQ_SIO1_S);
	114	#endif /* CONFIG_M32R_USE_DBG_CONSOLE */
	115
	116	#if defined(CONFIG_USB)
	117	/* INT1 : USB Host controller interrupt */
27e5c5a9	118	irq_set_chip_and_handler(M32R_IRQ_INT1, &mappi2_irq_type,
efa63c64	119	handle_level_irq);
1da177e4 LT	120	icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_ISMOD01;
	121	disable_mappi2_irq(M32R_IRQ_INT1);
	122	#endif /* CONFIG_USB */
	123
	124	/* ICUCR40: CFC IREQ */
27e5c5a9	125	irq_set_chip_and_handler(PLD_IRQ_CFIREQ, &mappi2_irq_type,
efa63c64	126	handle_level_irq);
1da177e4 LT	127	icu_data[PLD_IRQ_CFIREQ].icucr = M32R_ICUCR_IEN\|M32R_ICUCR_ISMOD01;
	128	disable_mappi2_irq(PLD_IRQ_CFIREQ);
	129
	130	#if defined(CONFIG_M32R_CFC)
	131	/* ICUCR41: CFC Insert */
27e5c5a9	132	irq_set_chip_and_handler(PLD_IRQ_CFC_INSERT, &mappi2_irq_type,
efa63c64	133	handle_level_irq);
1da177e4	134	icu_data[PLD_IRQ_CFC_INSERT].icucr = M32R_ICUCR_IEN\|M32R_ICUCR_ISMOD00;
1da177e4 LT	135	disable_mappi2_irq(PLD_IRQ_CFC_INSERT);
	136
	137	/* ICUCR42: CFC Eject */
27e5c5a9	138	irq_set_chip_and_handler(PLD_IRQ_CFC_EJECT, &mappi2_irq_type,
efa63c64	139	handle_level_irq);
1da177e4	140	icu_data[PLD_IRQ_CFC_EJECT].icucr = M32R_ICUCR_IEN\|M32R_ICUCR_ISMOD10;
1da177e4	141	disable_mappi2_irq(PLD_IRQ_CFC_EJECT);
1da177e4 LT	142	#endif /* CONFIG_MAPPI2_CFC */
	143	}
	144
	145	#define LAN_IOSTART 0x300
	146	#define LAN_IOEND 0x320
	147	static struct resource smc91x_resources[] = {
	148	[0] = {
	149	.start = (LAN_IOSTART),
	150	.end = (LAN_IOEND),
	151	.flags = IORESOURCE_MEM,
	152	},
	153	[1] = {
	154	.start = M32R_IRQ_INT0,
	155	.end = M32R_IRQ_INT0,
	156	.flags = IORESOURCE_IRQ,
	157	}
	158	};
	159
	160	static struct platform_device smc91x_device = {
	161	.name = "smc91x",
	162	.id = 0,
	163	.num_resources = ARRAY_SIZE(smc91x_resources),
	164	.resource = smc91x_resources,
	165	};
	166
	167	static int __init platform_init(void)
	168	{
	169	platform_device_register(&smc91x_device);
	170	return 0;
	171	}
	172	arch_initcall(platform_init);