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b2441318 | 1 | // SPDX-License-Identifier: GPL-2.0 |
23680863 | 2 | /* |
3264f976 | 3 | * linux/arch/m32r/platforms/mappi3/setup.c |
23680863 HT |
4 | * |
5 | * Setup routines for Renesas MAPPI-III(M3A-2170) Board | |
6 | * | |
316240f6 HT |
7 | * Copyright (c) 2001-2005 Hiroyuki Kondo, Hirokazu Takata, |
8 | * Hitoshi Yamamoto, Mamoru Sakugawa | |
23680863 HT |
9 | */ |
10 | ||
23680863 HT |
11 | #include <linux/irq.h> |
12 | #include <linux/kernel.h> | |
13 | #include <linux/init.h> | |
d052d1be | 14 | #include <linux/platform_device.h> |
23680863 | 15 | |
23680863 HT |
16 | #include <asm/m32r.h> |
17 | #include <asm/io.h> | |
18 | ||
19 | #define irq2port(x) (M32R_ICU_CR1_PORTL + ((x - 1) * sizeof(unsigned long))) | |
20 | ||
23680863 HT |
21 | icu_data_t icu_data[NR_IRQS]; |
22 | ||
23 | static void disable_mappi3_irq(unsigned int irq) | |
24 | { | |
25 | unsigned long port, data; | |
26 | ||
27 | if ((irq == 0) ||(irq >= NR_IRQS)) { | |
28 | printk("bad irq 0x%08x\n", irq); | |
29 | return; | |
30 | } | |
31 | port = irq2port(irq); | |
32 | data = icu_data[irq].icucr|M32R_ICUCR_ILEVEL7; | |
33 | outl(data, port); | |
34 | } | |
35 | ||
36 | static void enable_mappi3_irq(unsigned int irq) | |
37 | { | |
38 | unsigned long port, data; | |
39 | ||
40 | if ((irq == 0) ||(irq >= NR_IRQS)) { | |
41 | printk("bad irq 0x%08x\n", irq); | |
42 | return; | |
43 | } | |
44 | port = irq2port(irq); | |
45 | data = icu_data[irq].icucr|M32R_ICUCR_IEN|M32R_ICUCR_ILEVEL6; | |
46 | outl(data, port); | |
47 | } | |
48 | ||
b82727ec | 49 | static void mask_mappi3(struct irq_data *data) |
23680863 | 50 | { |
b82727ec | 51 | disable_mappi3_irq(data->irq); |
23680863 HT |
52 | } |
53 | ||
b82727ec | 54 | static void unmask_mappi3(struct irq_data *data) |
23680863 | 55 | { |
b82727ec | 56 | enable_mappi3_irq(data->irq); |
23680863 HT |
57 | } |
58 | ||
b82727ec | 59 | static void shutdown_mappi3(struct irq_data *data) |
23680863 HT |
60 | { |
61 | unsigned long port; | |
62 | ||
b82727ec | 63 | port = irq2port(data->irq); |
23680863 HT |
64 | outl(M32R_ICUCR_ILEVEL7, port); |
65 | } | |
66 | ||
b82727ec TG |
67 | static struct irq_chip mappi3_irq_type = { |
68 | .name = "MAPPI3-IRQ", | |
69 | .irq_shutdown = shutdown_mappi3, | |
70 | .irq_mask = mask_mappi3, | |
71 | .irq_unmask = unmask_mappi3, | |
23680863 HT |
72 | }; |
73 | ||
74 | void __init init_IRQ(void) | |
75 | { | |
76 | #if defined(CONFIG_SMC91X) | |
77 | /* INT0 : LAN controller (SMC91111) */ | |
27e5c5a9 | 78 | irq_set_chip_and_handler(M32R_IRQ_INT0, &mappi3_irq_type, |
b82727ec | 79 | handle_level_irq); |
23680863 HT |
80 | icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10; |
81 | disable_mappi3_irq(M32R_IRQ_INT0); | |
82 | #endif /* CONFIG_SMC91X */ | |
83 | ||
84 | /* MFT2 : system timer */ | |
27e5c5a9 | 85 | irq_set_chip_and_handler(M32R_IRQ_MFT2, &mappi3_irq_type, |
b82727ec | 86 | handle_level_irq); |
23680863 HT |
87 | icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; |
88 | disable_mappi3_irq(M32R_IRQ_MFT2); | |
89 | ||
90 | #ifdef CONFIG_SERIAL_M32R_SIO | |
91 | /* SIO0_R : uart receive data */ | |
27e5c5a9 | 92 | irq_set_chip_and_handler(M32R_IRQ_SIO0_R, &mappi3_irq_type, |
b82727ec | 93 | handle_level_irq); |
23680863 HT |
94 | icu_data[M32R_IRQ_SIO0_R].icucr = 0; |
95 | disable_mappi3_irq(M32R_IRQ_SIO0_R); | |
96 | ||
97 | /* SIO0_S : uart send data */ | |
27e5c5a9 | 98 | irq_set_chip_and_handler(M32R_IRQ_SIO0_S, &mappi3_irq_type, |
b82727ec | 99 | handle_level_irq); |
23680863 HT |
100 | icu_data[M32R_IRQ_SIO0_S].icucr = 0; |
101 | disable_mappi3_irq(M32R_IRQ_SIO0_S); | |
102 | /* SIO1_R : uart receive data */ | |
27e5c5a9 | 103 | irq_set_chip_and_handler(M32R_IRQ_SIO1_R, &mappi3_irq_type, |
b82727ec | 104 | handle_level_irq); |
23680863 HT |
105 | icu_data[M32R_IRQ_SIO1_R].icucr = 0; |
106 | disable_mappi3_irq(M32R_IRQ_SIO1_R); | |
107 | ||
108 | /* SIO1_S : uart send data */ | |
27e5c5a9 | 109 | irq_set_chip_and_handler(M32R_IRQ_SIO1_S, &mappi3_irq_type, |
b82727ec | 110 | handle_level_irq); |
23680863 HT |
111 | icu_data[M32R_IRQ_SIO1_S].icucr = 0; |
112 | disable_mappi3_irq(M32R_IRQ_SIO1_S); | |
113 | #endif /* CONFIG_M32R_USE_DBG_CONSOLE */ | |
114 | ||
115 | #if defined(CONFIG_USB) | |
116 | /* INT1 : USB Host controller interrupt */ | |
27e5c5a9 | 117 | irq_set_chip_and_handler(M32R_IRQ_INT1, &mappi3_irq_type, |
b82727ec | 118 | handle_level_irq); |
23680863 HT |
119 | icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_ISMOD01; |
120 | disable_mappi3_irq(M32R_IRQ_INT1); | |
121 | #endif /* CONFIG_USB */ | |
122 | ||
ad09d583 | 123 | /* CFC IREQ */ |
27e5c5a9 | 124 | irq_set_chip_and_handler(PLD_IRQ_CFIREQ, &mappi3_irq_type, |
b82727ec | 125 | handle_level_irq); |
23680863 HT |
126 | icu_data[PLD_IRQ_CFIREQ].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD01; |
127 | disable_mappi3_irq(PLD_IRQ_CFIREQ); | |
128 | ||
129 | #if defined(CONFIG_M32R_CFC) | |
ad09d583 | 130 | /* ICUCR41: CFC Insert & eject */ |
27e5c5a9 | 131 | irq_set_chip_and_handler(PLD_IRQ_CFC_INSERT, &mappi3_irq_type, |
b82727ec | 132 | handle_level_irq); |
23680863 HT |
133 | icu_data[PLD_IRQ_CFC_INSERT].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD00; |
134 | disable_mappi3_irq(PLD_IRQ_CFC_INSERT); | |
135 | ||
23680863 | 136 | #endif /* CONFIG_M32R_CFC */ |
ad09d583 HT |
137 | |
138 | /* IDE IREQ */ | |
27e5c5a9 | 139 | irq_set_chip_and_handler(PLD_IRQ_IDEIREQ, &mappi3_irq_type, |
b82727ec | 140 | handle_level_irq); |
ad09d583 HT |
141 | icu_data[PLD_IRQ_IDEIREQ].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10; |
142 | disable_mappi3_irq(PLD_IRQ_IDEIREQ); | |
143 | ||
23680863 HT |
144 | } |
145 | ||
316240f6 HT |
146 | #if defined(CONFIG_SMC91X) |
147 | ||
23680863 HT |
148 | #define LAN_IOSTART 0x300 |
149 | #define LAN_IOEND 0x320 | |
150 | static struct resource smc91x_resources[] = { | |
151 | [0] = { | |
152 | .start = (LAN_IOSTART), | |
153 | .end = (LAN_IOEND), | |
154 | .flags = IORESOURCE_MEM, | |
155 | }, | |
156 | [1] = { | |
157 | .start = M32R_IRQ_INT0, | |
158 | .end = M32R_IRQ_INT0, | |
159 | .flags = IORESOURCE_IRQ, | |
160 | } | |
161 | }; | |
162 | ||
163 | static struct platform_device smc91x_device = { | |
164 | .name = "smc91x", | |
165 | .id = 0, | |
166 | .num_resources = ARRAY_SIZE(smc91x_resources), | |
167 | .resource = smc91x_resources, | |
168 | }; | |
169 | ||
316240f6 HT |
170 | #endif |
171 | ||
172 | #if defined(CONFIG_FB_S1D13XXX) | |
173 | ||
174 | #include <video/s1d13xxxfb.h> | |
175 | #include <asm/s1d13806.h> | |
176 | ||
177 | static struct s1d13xxxfb_pdata s1d13xxxfb_data = { | |
178 | .initregs = s1d13xxxfb_initregs, | |
179 | .initregssize = ARRAY_SIZE(s1d13xxxfb_initregs), | |
180 | .platform_init_video = NULL, | |
181 | #ifdef CONFIG_PM | |
182 | .platform_suspend_video = NULL, | |
183 | .platform_resume_video = NULL, | |
184 | #endif | |
185 | }; | |
186 | ||
187 | static struct resource s1d13xxxfb_resources[] = { | |
188 | [0] = { | |
189 | .start = 0x1d600000UL, | |
190 | .end = 0x1d73FFFFUL, | |
191 | .flags = IORESOURCE_MEM, | |
192 | }, | |
193 | [1] = { | |
194 | .start = 0x1d400000UL, | |
195 | .end = 0x1d4001FFUL, | |
196 | .flags = IORESOURCE_MEM, | |
197 | } | |
198 | }; | |
199 | ||
200 | static struct platform_device s1d13xxxfb_device = { | |
201 | .name = S1D_DEVICENAME, | |
202 | .id = 0, | |
203 | .dev = { | |
204 | .platform_data = &s1d13xxxfb_data, | |
205 | }, | |
206 | .num_resources = ARRAY_SIZE(s1d13xxxfb_resources), | |
207 | .resource = s1d13xxxfb_resources, | |
208 | }; | |
209 | #endif | |
210 | ||
23680863 HT |
211 | static int __init platform_init(void) |
212 | { | |
316240f6 | 213 | #if defined(CONFIG_SMC91X) |
23680863 | 214 | platform_device_register(&smc91x_device); |
316240f6 HT |
215 | #endif |
216 | #if defined(CONFIG_FB_S1D13XXX) | |
217 | platform_device_register(&s1d13xxxfb_device); | |
218 | #endif | |
23680863 HT |
219 | return 0; |
220 | } | |
221 | arch_initcall(platform_init); |