[mirror_ubuntu-zesty-kernel.git] / arch / m68k / 68360 / head-ram.S

/*
 * head-ram.S - startup code for Motorola 68360
 *
 * Copyright 2001 (C) SED Systems, a Division of Calian Ltd.
 * Based on: arch/m68knommu/platform/68328/pilot/crt0_rom.S
 * Based on: arch/m68knommu/platform/68360/uCquicc/crt0_rom.S, 2.0.38.1.pre7
 *           uClinux Kernel
 * Copyright (C) Michael Leslie <mleslie@lineo.com>
 * Based on: arch/m68knommu/platform/68EZ328/ucsimm/crt0_rom.S
 * Copyright (C) 1998  D. Jeff Dionne <jeff@uclinux.org>,
 *
 */
#define ASSEMBLY

.global _stext
.global _start

.global _rambase
.global _ramvec
.global _ramstart
.global _ramend

.global _quicc_base
.global _periph_base

#define	RAMEND                      (CONFIG_RAMBASE + CONFIG_RAMSIZE)
#define	ROMEND                      (CONFIG_ROMBASE + CONFIG_ROMSIZE)

#define REGB                        0x1000
#define PEPAR                       (_dprbase + REGB + 0x0016)
#define GMR                         (_dprbase + REGB + 0x0040)
#define OR0                         (_dprbase + REGB + 0x0054)
#define BR0                         (_dprbase + REGB + 0x0050)
#define OR1                         (_dprbase + REGB + 0x0064)
#define BR1                         (_dprbase + REGB + 0x0060)
#define OR4                         (_dprbase + REGB + 0x0094)
#define BR4                         (_dprbase + REGB + 0x0090)
#define OR6                         (_dprbase + REGB + 0x00b4)
#define BR6                         (_dprbase + REGB + 0x00b0)
#define OR7                         (_dprbase + REGB + 0x00c4)
#define BR7                         (_dprbase + REGB + 0x00c0)

#define MCR                         (_dprbase + REGB + 0x0000)
#define AVR                         (_dprbase + REGB + 0x0008)

#define SYPCR                       (_dprbase + REGB + 0x0022)

#define PLLCR                       (_dprbase + REGB + 0x0010)
#define CLKOCR                      (_dprbase + REGB + 0x000C)
#define CDVCR                       (_dprbase + REGB + 0x0014)

#define BKAR                        (_dprbase + REGB + 0x0030)
#define BKCR                        (_dprbase + REGB + 0x0034)
#define SWIV                        (_dprbase + REGB + 0x0023)
#define PICR                        (_dprbase + REGB + 0x0026)
#define PITR                        (_dprbase + REGB + 0x002A)

/* Define for all memory configuration */
#define MCU_SIM_GMR                 0x00000000
#define SIM_OR_MASK                 0x0fffffff

/* Defines for chip select zero - the flash */
#define SIM_OR0_MASK                0x20000002
#define SIM_BR0_MASK                0x00000001


/* Defines for chip select one - the RAM */
#define SIM_OR1_MASK                0x10000000
#define SIM_BR1_MASK                0x00000001

#define MCU_SIM_MBAR_ADRS           0x0003ff00
#define MCU_SIM_MBAR_BA_MASK        0xfffff000
#define MCU_SIM_MBAR_AS_MASK        0x00000001

#define MCU_SIM_PEPAR               0x00B4
    
#define MCU_DISABLE_INTRPTS         0x2700
#define MCU_SIM_AVR                 0x00
    
#define MCU_SIM_MCR                 0x00005cff

#define MCU_SIM_CLKOCR              0x00
#define MCU_SIM_PLLCR               0x8000
#define MCU_SIM_CDVCR               0x0000

#define MCU_SIM_SYPCR               0x0000
#define MCU_SIM_SWIV                0x00
#define MCU_SIM_PICR                0x0000
#define MCU_SIM_PITR                0x0000


#include <asm/m68360_regs.h>

	
/*
 * By the time this RAM specific code begins to execute, DPRAM
 * and DRAM should already be mapped and accessible.
 */

	.text
_start:
_stext:
	nop
	ori.w	#MCU_DISABLE_INTRPTS, %sr	/* disable interrupts: */
	/* We should not need to setup the boot stack the reset should do it. */
	movea.l	#RAMEND, %sp			/*set up stack at the end of DRAM:*/

set_mbar_register:
	moveq.l	#0x07, %d1			/* Setup MBAR */
	movec	%d1, %dfc

	lea.l	MCU_SIM_MBAR_ADRS, %a0
	move.l	#_dprbase, %d0
	andi.l	#MCU_SIM_MBAR_BA_MASK, %d0
	ori.l	#MCU_SIM_MBAR_AS_MASK, %d0
	moves.l	%d0, %a0@

	moveq.l	#0x05, %d1
	movec.l	%d1, %dfc

	/* Now we can begin to access registers in DPRAM */

set_sim_mcr:
	/* Set Module Configuration Register */
	move.l	#MCU_SIM_MCR, MCR

	/* to do:	Determine cause of reset */

	/*
	 *       configure system clock MC68360 p. 6-40
	 *       (value +1)*osc/128 = system clock
	 */
set_sim_clock:
	move.w	#MCU_SIM_PLLCR, PLLCR
	move.b	#MCU_SIM_CLKOCR, CLKOCR
	move.w	#MCU_SIM_CDVCR, CDVCR

	/* Wait for the PLL to settle */
	move.w	#16384, %d0
pll_settle_wait:
	subi.w	#1, %d0
	bne	pll_settle_wait

	/* Setup the system protection register, and watchdog timer register */
	move.b	#MCU_SIM_SWIV, SWIV
	move.w	#MCU_SIM_PICR, PICR
	move.w	#MCU_SIM_PITR, PITR
	move.w	#MCU_SIM_SYPCR, SYPCR

	/* Clear DPRAM - system + parameter */
	movea.l	#_dprbase, %a0
	movea.l	#_dprbase+0x2000, %a1

	/* Copy 0 to %a0 until %a0 == %a1 */
clear_dpram:
	movel	#0, %a0@+
	cmpal	%a0, %a1
	bhi	clear_dpram

configure_memory_controller:    
	/* Set up Global Memory Register (GMR) */
	move.l	#MCU_SIM_GMR, %d0
	move.l	%d0, GMR

configure_chip_select_0:
	move.l	#RAMEND, %d0
	subi.l	#__ramstart, %d0
	subq.l	#0x01, %d0
	eori.l	#SIM_OR_MASK, %d0
	ori.l	#SIM_OR0_MASK, %d0
	move.l	%d0, OR0

	move.l	#__ramstart, %d0
	ori.l	#SIM_BR0_MASK, %d0
	move.l	%d0, BR0

configure_chip_select_1:
	move.l	#ROMEND, %d0
	subi.l	#__rom_start, %d0
	subq.l	#0x01, %d0
	eori.l	#SIM_OR_MASK, %d0
	ori.l	#SIM_OR1_MASK, %d0
	move.l	%d0, OR1

	move.l	#__rom_start, %d0
	ori.l	#SIM_BR1_MASK, %d0
	move.l	%d0, BR1

	move.w	#MCU_SIM_PEPAR, PEPAR 

	/* point to vector table: */
	move.l	#_romvec, %a0
	move.l	#_ramvec, %a1
copy_vectors:
	move.l	%a0@, %d0
	move.l	%d0, %a1@
	move.l	%a0@, %a1@
	addq.l	#0x04, %a0
	addq.l	#0x04, %a1
	cmp.l	#_start, %a0
	blt	copy_vectors

	move.l	#_ramvec, %a1
	movec	%a1, %vbr


	/* Copy data segment from ROM to RAM */
	moveal	#_stext, %a0
	moveal	#_sdata, %a1
	moveal	#_edata, %a2

	/* Copy %a0 to %a1 until %a1 == %a2 */
LD1:
	move.l	%a0@, %d0
	addq.l	#0x04, %a0
	move.l	%d0, %a1@
	addq.l	#0x04, %a1
	cmp.l	#_edata, %a1
	blt     LD1

	moveal	#__bss_start, %a0
	moveal	#__bss_stop, %a1

	/* Copy 0 to %a0 until %a0 == %a1 */
L1:
	movel	#0, %a0@+
	cmpal	%a0, %a1
	bhi	L1

load_quicc:
	move.l	#_dprbase, _quicc_base

store_ram_size:
	/* Set ram size information */
	move.l	#_sdata, _rambase
	move.l	#__bss_stop, _ramstart
	move.l	#RAMEND, %d0
	sub.l	#0x1000, %d0			/* Reserve 4K for stack space.*/
	move.l	%d0, _ramend			/* Different from RAMEND.*/

	pea	0
	pea	env
	pea	%sp@(4)
	pea	0

	lea	init_thread_union, %a2
	lea	0x2000(%a2), %sp

lp:
	jsr	start_kernel

_exit:
	jmp	_exit


	.data
	.align 4
env:
	.long	0
_quicc_base:
	.long	0
_periph_base:
	.long	0
_ramvec:
	.long   0
_rambase:
	.long   0
_ramstart:
	.long   0
_ramend:
	.long   0
_dprbase:
	.long	0xffffe000

	.text

    /*
     * These are the exception vectors at boot up, they are copied into RAM
     * and then overwritten as needed.
     */
 
.section ".data..initvect","awx"
    .long   RAMEND	/* Reset: Initial Stack Pointer                 - 0.  */
    .long   _start      /* Reset: Initial Program Counter               - 1.  */
    .long   buserr      /* Bus Error                                    - 2.  */
    .long   trap        /* Address Error                                - 3.  */
    .long   trap        /* Illegal Instruction                          - 4.  */
    .long   trap        /* Divide by zero                               - 5.  */
    .long   trap        /* CHK, CHK2 Instructions                       - 6.  */
    .long   trap        /* TRAPcc, TRAPV Instructions                   - 7.  */
    .long   trap        /* Privilege Violation                          - 8.  */
    .long   trap        /* Trace                                        - 9.  */
    .long   trap        /* Line 1010 Emulator                           - 10. */
    .long   trap        /* Line 1111 Emualtor                           - 11. */
    .long   trap        /* Harware Breakpoint                           - 12. */
    .long   trap        /* (Reserved for Coprocessor Protocol Violation)- 13. */
    .long   trap        /* Format Error                                 - 14. */
    .long   trap        /* Uninitialized Interrupt                      - 15. */
    .long   trap        /* (Unassigned, Reserver)                       - 16. */
    .long   trap        /* (Unassigned, Reserver)                       - 17. */
    .long   trap        /* (Unassigned, Reserver)                       - 18. */
    .long   trap        /* (Unassigned, Reserver)                       - 19. */
    .long   trap        /* (Unassigned, Reserver)                       - 20. */
    .long   trap        /* (Unassigned, Reserver)                       - 21. */
    .long   trap        /* (Unassigned, Reserver)                       - 22. */
    .long   trap        /* (Unassigned, Reserver)                       - 23. */
    .long   trap        /* Spurious Interrupt                           - 24. */
    .long   trap        /* Level 1 Interrupt Autovector                 - 25. */
    .long   trap        /* Level 2 Interrupt Autovector                 - 26. */
    .long   trap        /* Level 3 Interrupt Autovector                 - 27. */
    .long   trap        /* Level 4 Interrupt Autovector                 - 28. */
    .long   trap        /* Level 5 Interrupt Autovector                 - 29. */
    .long   trap        /* Level 6 Interrupt Autovector                 - 30. */
    .long   trap        /* Level 7 Interrupt Autovector                 - 31. */
    .long   system_call /* Trap Instruction Vectors 0                   - 32. */
    .long   trap        /* Trap Instruction Vectors 1                   - 33. */
    .long   trap        /* Trap Instruction Vectors 2                   - 34. */
    .long   trap        /* Trap Instruction Vectors 3                   - 35. */
    .long   trap        /* Trap Instruction Vectors 4                   - 36. */
    .long   trap        /* Trap Instruction Vectors 5                   - 37. */
    .long   trap        /* Trap Instruction Vectors 6                   - 38. */
    .long   trap        /* Trap Instruction Vectors 7                   - 39. */
    .long   trap        /* Trap Instruction Vectors 8                   - 40. */
    .long   trap        /* Trap Instruction Vectors 9                   - 41. */
    .long   trap        /* Trap Instruction Vectors 10                  - 42. */
    .long   trap        /* Trap Instruction Vectors 11                  - 43. */
    .long   trap        /* Trap Instruction Vectors 12                  - 44. */
    .long   trap        /* Trap Instruction Vectors 13                  - 45. */
    .long   trap        /* Trap Instruction Vectors 14                  - 46. */
    .long   trap        /* Trap Instruction Vectors 15                  - 47. */
    .long   0           /* (Reserved for Coprocessor)                   - 48. */
    .long   0           /* (Reserved for Coprocessor)                   - 49. */
    .long   0           /* (Reserved for Coprocessor)                   - 50. */
    .long   0           /* (Reserved for Coprocessor)                   - 51. */
    .long   0           /* (Reserved for Coprocessor)                   - 52. */
    .long   0           /* (Reserved for Coprocessor)                   - 53. */
    .long   0           /* (Reserved for Coprocessor)                   - 54. */
    .long   0           /* (Reserved for Coprocessor)                   - 55. */
    .long   0           /* (Reserved for Coprocessor)                   - 56. */
    .long   0           /* (Reserved for Coprocessor)                   - 57. */
    .long   0           /* (Reserved for Coprocessor)                   - 58. */
    .long   0           /* (Unassigned, Reserved)                       - 59. */
    .long   0           /* (Unassigned, Reserved)                       - 60. */
    .long   0           /* (Unassigned, Reserved)                       - 61. */
    .long   0           /* (Unassigned, Reserved)                       - 62. */
    .long   0           /* (Unassigned, Reserved)                       - 63. */
    /*                  The assignment of these vectors to the CPM is         */
    /*                  dependent on the configuration of the CPM vba         */
    /*                          fields.                                       */
    .long   0           /* (User-Defined Vectors 1) CPM Error           - 64. */
    .long   0           /* (User-Defined Vectors 2) CPM Parallel IO PC11- 65. */
    .long   0           /* (User-Defined Vectors 3) CPM Parallel IO PC10- 66. */
    .long   0           /* (User-Defined Vectors 4) CPM SMC2 / PIP      - 67. */
    .long   0           /* (User-Defined Vectors 5) CPM SMC1            - 68. */
    .long   0           /* (User-Defined Vectors 6) CPM SPI             - 69. */
    .long   0           /* (User-Defined Vectors 7) CPM Parallel IO PC9 - 70. */
    .long   0           /* (User-Defined Vectors 8) CPM Timer 4         - 71. */
    .long   0           /* (User-Defined Vectors 9) CPM Reserved        - 72. */
    .long   0           /* (User-Defined Vectors 10) CPM Parallel IO PC8- 73. */
    .long   0           /* (User-Defined Vectors 11) CPM Parallel IO PC7- 74. */
    .long   0           /* (User-Defined Vectors 12) CPM Parallel IO PC6- 75. */
    .long   0           /* (User-Defined Vectors 13) CPM Timer 3        - 76. */
    .long   0           /* (User-Defined Vectors 14) CPM Reserved       - 77. */
    .long   0           /* (User-Defined Vectors 15) CPM Parallel IO PC5- 78. */
    .long   0           /* (User-Defined Vectors 16) CPM Parallel IO PC4- 79. */
    .long   0           /* (User-Defined Vectors 17) CPM Reserved       - 80. */
    .long   0           /* (User-Defined Vectors 18) CPM RISC Timer Tbl - 81. */
    .long   0           /* (User-Defined Vectors 19) CPM Timer 2        - 82. */
    .long   0           /* (User-Defined Vectors 21) CPM Reserved       - 83. */
    .long   0           /* (User-Defined Vectors 22) CPM IDMA2          - 84. */
    .long   0           /* (User-Defined Vectors 23) CPM IDMA1          - 85. */
    .long   0           /* (User-Defined Vectors 24) CPM SDMA Bus Err   - 86. */
    .long   0           /* (User-Defined Vectors 25) CPM Parallel IO PC3- 87. */
    .long   0           /* (User-Defined Vectors 26) CPM Parallel IO PC2- 88. */
    .long   0           /* (User-Defined Vectors 27) CPM Timer 1        - 89. */
    .long   0           /* (User-Defined Vectors 28) CPM Parallel IO PC1- 90. */
    .long   0           /* (User-Defined Vectors 29) CPM SCC 4          - 91. */
    .long   0           /* (User-Defined Vectors 30) CPM SCC 3          - 92. */
    .long   0           /* (User-Defined Vectors 31) CPM SCC 2          - 93. */
    .long   0           /* (User-Defined Vectors 32) CPM SCC 1          - 94. */
    .long   0           /* (User-Defined Vectors 33) CPM Parallel IO PC0- 95. */
    /*                  I don't think anything uses the vectors after here.   */
    .long   0           /* (User-Defined Vectors 34)                    - 96. */
    .long   0,0,0,0,0               /* (User-Defined Vectors 35  -  39). */
    .long   0,0,0,0,0,0,0,0,0,0     /* (User-Defined Vectors 40  -  49). */
    .long   0,0,0,0,0,0,0,0,0,0     /* (User-Defined Vectors 50  -  59). */
    .long   0,0,0,0,0,0,0,0,0,0     /* (User-Defined Vectors 60  -  69). */
    .long   0,0,0,0,0,0,0,0,0,0     /* (User-Defined Vectors 70  -  79). */
    .long   0,0,0,0,0,0,0,0,0,0     /* (User-Defined Vectors 80  -  89). */
    .long   0,0,0,0,0,0,0,0,0,0     /* (User-Defined Vectors 90  -  99). */
    .long   0,0,0,0,0,0,0,0,0,0     /* (User-Defined Vectors 100 - 109). */
    .long   0,0,0,0,0,0,0,0,0,0     /* (User-Defined Vectors 110 - 119). */
    .long   0,0,0,0,0,0,0,0,0,0     /* (User-Defined Vectors 120 - 129). */
    .long   0,0,0,0,0,0,0,0,0,0     /* (User-Defined Vectors 130 - 139). */
    .long   0,0,0,0,0,0,0,0,0,0     /* (User-Defined Vectors 140 - 149). */
    .long   0,0,0,0,0,0,0,0,0,0     /* (User-Defined Vectors 150 - 159). */
    .long   0,0,0,0,0,0,0,0,0,0     /* (User-Defined Vectors 160 - 169). */
    .long   0,0,0,0,0,0,0,0,0,0     /* (User-Defined Vectors 170 - 179). */
    .long   0,0,0,0,0,0,0,0,0,0     /* (User-Defined Vectors 180 - 189). */
    .long   0,0,0                   /* (User-Defined Vectors 190 - 192). */
.text
ignore: rte
Commit	Line	Data
6f4a8856 GU	1	/*
6f4a8856 GU	2	* head-ram.S - startup code for Motorola 68360
81d4903d GU	3	*
	4	* Copyright 2001 (C) SED Systems, a Division of Calian Ltd.
	5	* Based on: arch/m68knommu/platform/68328/pilot/crt0_rom.S
	6	* Based on: arch/m68knommu/platform/68360/uCquicc/crt0_rom.S, 2.0.38.1.pre7
	7	* uClinux Kernel
	8	* Copyright (C) Michael Leslie <mleslie@lineo.com>
	9	* Based on: arch/m68knommu/platform/68EZ328/ucsimm/crt0_rom.S
	10	* Copyright (C) 1998 D. Jeff Dionne <jeff@uclinux.org>,
	11	*
	12	*/
	13	#define ASSEMBLY
81d4903d GU	14
	15	.global _stext
	16	.global _start
	17
	18	.global _rambase
81d4903d GU	19	.global _ramvec
	20	.global _ramstart
	21	.global _ramend
	22
	23	.global _quicc_base
	24	.global _periph_base
	25
d046f611	26	#define RAMEND (CONFIG_RAMBASE + CONFIG_RAMSIZE)
d773c660	27	#define ROMEND (CONFIG_ROMBASE + CONFIG_ROMSIZE)
d046f611	28
81d4903d GU	29	#define REGB 0x1000
	30	#define PEPAR (_dprbase + REGB + 0x0016)
	31	#define GMR (_dprbase + REGB + 0x0040)
	32	#define OR0 (_dprbase + REGB + 0x0054)
	33	#define BR0 (_dprbase + REGB + 0x0050)
	34	#define OR1 (_dprbase + REGB + 0x0064)
	35	#define BR1 (_dprbase + REGB + 0x0060)
	36	#define OR4 (_dprbase + REGB + 0x0094)
	37	#define BR4 (_dprbase + REGB + 0x0090)
	38	#define OR6 (_dprbase + REGB + 0x00b4)
	39	#define BR6 (_dprbase + REGB + 0x00b0)
	40	#define OR7 (_dprbase + REGB + 0x00c4)
	41	#define BR7 (_dprbase + REGB + 0x00c0)
	42
	43	#define MCR (_dprbase + REGB + 0x0000)
	44	#define AVR (_dprbase + REGB + 0x0008)
	45
	46	#define SYPCR (_dprbase + REGB + 0x0022)
	47
	48	#define PLLCR (_dprbase + REGB + 0x0010)
	49	#define CLKOCR (_dprbase + REGB + 0x000C)
	50	#define CDVCR (_dprbase + REGB + 0x0014)
	51
	52	#define BKAR (_dprbase + REGB + 0x0030)
	53	#define BKCR (_dprbase + REGB + 0x0034)
	54	#define SWIV (_dprbase + REGB + 0x0023)
	55	#define PICR (_dprbase + REGB + 0x0026)
	56	#define PITR (_dprbase + REGB + 0x002A)
	57
	58	/* Define for all memory configuration */
	59	#define MCU_SIM_GMR 0x00000000
	60	#define SIM_OR_MASK 0x0fffffff
	61
	62	/* Defines for chip select zero - the flash */
	63	#define SIM_OR0_MASK 0x20000002
	64	#define SIM_BR0_MASK 0x00000001
	65
	66
	67	/* Defines for chip select one - the RAM */
	68	#define SIM_OR1_MASK 0x10000000
	69	#define SIM_BR1_MASK 0x00000001
	70
	71	#define MCU_SIM_MBAR_ADRS 0x0003ff00
	72	#define MCU_SIM_MBAR_BA_MASK 0xfffff000
	73	#define MCU_SIM_MBAR_AS_MASK 0x00000001
	74
	75	#define MCU_SIM_PEPAR 0x00B4
	76
	77	#define MCU_DISABLE_INTRPTS 0x2700
	78	#define MCU_SIM_AVR 0x00
	79
	80	#define MCU_SIM_MCR 0x00005cff
	81
	82	#define MCU_SIM_CLKOCR 0x00
	83	#define MCU_SIM_PLLCR 0x8000
	84	#define MCU_SIM_CDVCR 0x0000
	85
	86	#define MCU_SIM_SYPCR 0x0000
	87	#define MCU_SIM_SWIV 0x00
	88	#define MCU_SIM_PICR 0x0000
	89	#define MCU_SIM_PITR 0x0000
	90
	91
	92	#include <asm/m68360_regs.h>
93
94
95	/*
96	* By the time this RAM specific code begins to execute, DPRAM
97	* and DRAM should already be mapped and accessible.
98	*/
99
100	.text
101	_start:
102	_stext:
103	nop
104	ori.w #MCU_DISABLE_INTRPTS, %sr /* disable interrupts: */
105	/* We should not need to setup the boot stack the reset should do it. */
d046f611	106	movea.l #RAMEND, %sp /set up stack at the end of DRAM:/
81d4903d GU	107
	108	set_mbar_register:
	109	moveq.l #0x07, %d1 /* Setup MBAR */
	110	movec %d1, %dfc
	111
	112	lea.l MCU_SIM_MBAR_ADRS, %a0
	113	move.l #_dprbase, %d0
	114	andi.l #MCU_SIM_MBAR_BA_MASK, %d0
	115	ori.l #MCU_SIM_MBAR_AS_MASK, %d0
	116	moves.l %d0, %a0@
	117
	118	moveq.l #0x05, %d1
	119	movec.l %d1, %dfc
	120
	121	/* Now we can begin to access registers in DPRAM */
	122
	123	set_sim_mcr:
	124	/* Set Module Configuration Register */
	125	move.l #MCU_SIM_MCR, MCR
	126
	127	/* to do: Determine cause of reset */
	128
	129	/*
	130	* configure system clock MC68360 p. 6-40
	131	* (value +1)*osc/128 = system clock
	132	*/
	133	set_sim_clock:
	134	move.w #MCU_SIM_PLLCR, PLLCR
	135	move.b #MCU_SIM_CLKOCR, CLKOCR
	136	move.w #MCU_SIM_CDVCR, CDVCR
	137
	138	/* Wait for the PLL to settle */
	139	move.w #16384, %d0
	140	pll_settle_wait:
	141	subi.w #1, %d0
	142	bne pll_settle_wait
	143
	144	/* Setup the system protection register, and watchdog timer register */
	145	move.b #MCU_SIM_SWIV, SWIV
	146	move.w #MCU_SIM_PICR, PICR
	147	move.w #MCU_SIM_PITR, PITR
	148	move.w #MCU_SIM_SYPCR, SYPCR
	149
	150	/* Clear DPRAM - system + parameter */
	151	movea.l #_dprbase, %a0
	152	movea.l #_dprbase+0x2000, %a1
	153
	154	/* Copy 0 to %a0 until %a0 == %a1 */
	155	clear_dpram:
	156	movel #0, %a0@+
	157	cmpal %a0, %a1
	158	bhi clear_dpram
	159
	160	configure_memory_controller:
	161	/* Set up Global Memory Register (GMR) */
	162	move.l #MCU_SIM_GMR, %d0
	163	move.l %d0, GMR
	164
	165	configure_chip_select_0:
d046f611	166	move.l #RAMEND, %d0
81d4903d GU	167	subi.l #__ramstart, %d0
	168	subq.l #0x01, %d0
	169	eori.l #SIM_OR_MASK, %d0
	170	ori.l #SIM_OR0_MASK, %d0
	171	move.l %d0, OR0
	172
	173	move.l #__ramstart, %d0
	174	ori.l #SIM_BR0_MASK, %d0
	175	move.l %d0, BR0
	176
	177	configure_chip_select_1:
d773c660	178	move.l #ROMEND, %d0
81d4903d GU	179	subi.l #__rom_start, %d0
	180	subq.l #0x01, %d0
	181	eori.l #SIM_OR_MASK, %d0
	182	ori.l #SIM_OR1_MASK, %d0
	183	move.l %d0, OR1
	184
	185	move.l #__rom_start, %d0
	186	ori.l #SIM_BR1_MASK, %d0
	187	move.l %d0, BR1
	188
	189	move.w #MCU_SIM_PEPAR, PEPAR
	190
	191	/* point to vector table: */
	192	move.l #_romvec, %a0
	193	move.l #_ramvec, %a1
	194	copy_vectors:
	195	move.l %a0@, %d0
	196	move.l %d0, %a1@
	197	move.l %a0@, %a1@
	198	addq.l #0x04, %a0
	199	addq.l #0x04, %a1
	200	cmp.l #_start, %a0
	201	blt copy_vectors
	202
	203	move.l #_ramvec, %a1
	204	movec %a1, %vbr
	205
	206
	207	/* Copy data segment from ROM to RAM */
	208	moveal #_stext, %a0
	209	moveal #_sdata, %a1
	210	moveal #_edata, %a2
	211
	212	/* Copy %a0 to %a1 until %a1 == %a2 */
	213	LD1:
	214	move.l %a0@, %d0
	215	addq.l #0x04, %a0
	216	move.l %d0, %a1@
	217	addq.l #0x04, %a1
	218	cmp.l #_edata, %a1
	219	blt LD1
	220
dc061051 GU	221	moveal #__bss_start, %a0
dc061051 GU	222	moveal #__bss_stop, %a1
81d4903d GU	223
	224	/* Copy 0 to %a0 until %a0 == %a1 */
	225	L1:
	226	movel #0, %a0@+
	227	cmpal %a0, %a1
	228	bhi L1
	229
	230	load_quicc:
	231	move.l #_dprbase, _quicc_base
	232
	233	store_ram_size:
	234	/* Set ram size information */
	235	move.l #_sdata, _rambase
dc061051	236	move.l #__bss_stop, _ramstart
d046f611	237	move.l #RAMEND, %d0
81d4903d	238	sub.l #0x1000, %d0 /* Reserve 4K for stack space.*/
d046f611	239	move.l %d0, _ramend /* Different from RAMEND.*/
81d4903d	240
81d4903d GU	241	pea 0
	242	pea env
	243	pea %sp@(4)
	244	pea 0
	245
	246	lea init_thread_union, %a2
	247	lea 0x2000(%a2), %sp
	248
	249	lp:
	250	jsr start_kernel
	251
	252	_exit:
	253	jmp _exit
	254
	255
	256	.data
	257	.align 4
	258	env:
	259	.long 0
	260	_quicc_base:
	261	.long 0
	262	_periph_base:
	263	.long 0
	264	_ramvec:
	265	.long 0
	266	_rambase:
	267	.long 0
	268	_ramstart:
	269	.long 0
	270	_ramend:
	271	.long 0
	272	_dprbase:
	273	.long 0xffffe000
	274
	275	.text
	276
	277	/*
	278	* These are the exception vectors at boot up, they are copied into RAM
	279	* and then overwritten as needed.
	280	*/
	281
2c31c341	282	.section ".data..initvect","awx"
d046f611	283	.long RAMEND /* Reset: Initial Stack Pointer - 0. */
81d4903d GU	284	.long _start /* Reset: Initial Program Counter - 1. */
	285	.long buserr /* Bus Error - 2. */
	286	.long trap /* Address Error - 3. */
	287	.long trap /* Illegal Instruction - 4. */
	288	.long trap /* Divide by zero - 5. */
	289	.long trap /* CHK, CHK2 Instructions - 6. */
	290	.long trap /* TRAPcc, TRAPV Instructions - 7. */
	291	.long trap /* Privilege Violation - 8. */
	292	.long trap /* Trace - 9. */
	293	.long trap /* Line 1010 Emulator - 10. */
	294	.long trap /* Line 1111 Emualtor - 11. */
	295	.long trap /* Harware Breakpoint - 12. */
	296	.long trap /* (Reserved for Coprocessor Protocol Violation)- 13. */
	297	.long trap /* Format Error - 14. */
	298	.long trap /* Uninitialized Interrupt - 15. */
	299	.long trap /* (Unassigned, Reserver) - 16. */
	300	.long trap /* (Unassigned, Reserver) - 17. */
	301	.long trap /* (Unassigned, Reserver) - 18. */
	302	.long trap /* (Unassigned, Reserver) - 19. */
	303	.long trap /* (Unassigned, Reserver) - 20. */
	304	.long trap /* (Unassigned, Reserver) - 21. */
	305	.long trap /* (Unassigned, Reserver) - 22. */
	306	.long trap /* (Unassigned, Reserver) - 23. */
	307	.long trap /* Spurious Interrupt - 24. */
	308	.long trap /* Level 1 Interrupt Autovector - 25. */
	309	.long trap /* Level 2 Interrupt Autovector - 26. */
	310	.long trap /* Level 3 Interrupt Autovector - 27. */
	311	.long trap /* Level 4 Interrupt Autovector - 28. */
	312	.long trap /* Level 5 Interrupt Autovector - 29. */
	313	.long trap /* Level 6 Interrupt Autovector - 30. */
	314	.long trap /* Level 7 Interrupt Autovector - 31. */
	315	.long system_call /* Trap Instruction Vectors 0 - 32. */
	316	.long trap /* Trap Instruction Vectors 1 - 33. */
	317	.long trap /* Trap Instruction Vectors 2 - 34. */
	318	.long trap /* Trap Instruction Vectors 3 - 35. */
	319	.long trap /* Trap Instruction Vectors 4 - 36. */
	320	.long trap /* Trap Instruction Vectors 5 - 37. */
	321	.long trap /* Trap Instruction Vectors 6 - 38. */
	322	.long trap /* Trap Instruction Vectors 7 - 39. */
	323	.long trap /* Trap Instruction Vectors 8 - 40. */
	324	.long trap /* Trap Instruction Vectors 9 - 41. */
	325	.long trap /* Trap Instruction Vectors 10 - 42. */
	326	.long trap /* Trap Instruction Vectors 11 - 43. */
	327	.long trap /* Trap Instruction Vectors 12 - 44. */
	328	.long trap /* Trap Instruction Vectors 13 - 45. */
	329	.long trap /* Trap Instruction Vectors 14 - 46. */
	330	.long trap /* Trap Instruction Vectors 15 - 47. */
	331	.long 0 /* (Reserved for Coprocessor) - 48. */
	332	.long 0 /* (Reserved for Coprocessor) - 49. */
	333	.long 0 /* (Reserved for Coprocessor) - 50. */
	334	.long 0 /* (Reserved for Coprocessor) - 51. */
	335	.long 0 /* (Reserved for Coprocessor) - 52. */
	336	.long 0 /* (Reserved for Coprocessor) - 53. */
	337	.long 0 /* (Reserved for Coprocessor) - 54. */
	338	.long 0 /* (Reserved for Coprocessor) - 55. */
	339	.long 0 /* (Reserved for Coprocessor) - 56. */
	340	.long 0 /* (Reserved for Coprocessor) - 57. */
	341	.long 0 /* (Reserved for Coprocessor) - 58. */
	342	.long 0 /* (Unassigned, Reserved) - 59. */
	343	.long 0 /* (Unassigned, Reserved) - 60. */
	344	.long 0 /* (Unassigned, Reserved) - 61. */
	345	.long 0 /* (Unassigned, Reserved) - 62. */
	346	.long 0 /* (Unassigned, Reserved) - 63. */
	347	/* The assignment of these vectors to the CPM is */
348	/* dependent on the configuration of the CPM vba */
349	/* fields. */
350	.long 0 /* (User-Defined Vectors 1) CPM Error - 64. */
351	.long 0 /* (User-Defined Vectors 2) CPM Parallel IO PC11- 65. */
352	.long 0 /* (User-Defined Vectors 3) CPM Parallel IO PC10- 66. */
353	.long 0 /* (User-Defined Vectors 4) CPM SMC2 / PIP - 67. */
354	.long 0 /* (User-Defined Vectors 5) CPM SMC1 - 68. */
355	.long 0 /* (User-Defined Vectors 6) CPM SPI - 69. */
356	.long 0 /* (User-Defined Vectors 7) CPM Parallel IO PC9 - 70. */
357	.long 0 /* (User-Defined Vectors 8) CPM Timer 4 - 71. */
358	.long 0 /* (User-Defined Vectors 9) CPM Reserved - 72. */
359	.long 0 /* (User-Defined Vectors 10) CPM Parallel IO PC8- 73. */
360	.long 0 /* (User-Defined Vectors 11) CPM Parallel IO PC7- 74. */
361	.long 0 /* (User-Defined Vectors 12) CPM Parallel IO PC6- 75. */
362	.long 0 /* (User-Defined Vectors 13) CPM Timer 3 - 76. */
363	.long 0 /* (User-Defined Vectors 14) CPM Reserved - 77. */
364	.long 0 /* (User-Defined Vectors 15) CPM Parallel IO PC5- 78. */
365	.long 0 /* (User-Defined Vectors 16) CPM Parallel IO PC4- 79. */
366	.long 0 /* (User-Defined Vectors 17) CPM Reserved - 80. */
367	.long 0 /* (User-Defined Vectors 18) CPM RISC Timer Tbl - 81. */
368	.long 0 /* (User-Defined Vectors 19) CPM Timer 2 - 82. */
369	.long 0 /* (User-Defined Vectors 21) CPM Reserved - 83. */
370	.long 0 /* (User-Defined Vectors 22) CPM IDMA2 - 84. */
371	.long 0 /* (User-Defined Vectors 23) CPM IDMA1 - 85. */
372	.long 0 /* (User-Defined Vectors 24) CPM SDMA Bus Err - 86. */
373	.long 0 /* (User-Defined Vectors 25) CPM Parallel IO PC3- 87. */
374	.long 0 /* (User-Defined Vectors 26) CPM Parallel IO PC2- 88. */
375	.long 0 /* (User-Defined Vectors 27) CPM Timer 1 - 89. */
376	.long 0 /* (User-Defined Vectors 28) CPM Parallel IO PC1- 90. */
377	.long 0 /* (User-Defined Vectors 29) CPM SCC 4 - 91. */
378	.long 0 /* (User-Defined Vectors 30) CPM SCC 3 - 92. */
379	.long 0 /* (User-Defined Vectors 31) CPM SCC 2 - 93. */
380	.long 0 /* (User-Defined Vectors 32) CPM SCC 1 - 94. */
381	.long 0 /* (User-Defined Vectors 33) CPM Parallel IO PC0- 95. */
382	/* I don't think anything uses the vectors after here. */
383	.long 0 /* (User-Defined Vectors 34) - 96. */
384	.long 0,0,0,0,0 /* (User-Defined Vectors 35 - 39). */
385	.long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 40 - 49). */
386	.long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 50 - 59). */
387	.long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 60 - 69). */
388	.long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 70 - 79). */
389	.long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 80 - 89). */
390	.long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 90 - 99). */
391	.long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 100 - 109). */
392	.long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 110 - 119). */
393	.long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 120 - 129). */
394	.long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 130 - 139). */
395	.long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 140 - 149). */
396	.long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 150 - 159). */
397	.long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 160 - 169). */
398	.long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 170 - 179). */
399	.long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 180 - 189). */
400	.long 0,0,0 /* (User-Defined Vectors 190 - 192). */
401	.text
402	ignore: rte