[mirror_ubuntu-jammy-kernel.git] / arch / m68k / coldfire / head.S

/* SPDX-License-Identifier: GPL-2.0 */
/*****************************************************************************/

/*
 *	head.S -- common startup code for ColdFire CPUs.
 *
 *	(C) Copyright 1999-2011, Greg Ungerer <gerg@snapgear.com>.
 */

/*****************************************************************************/

#include <linux/linkage.h>
#include <linux/init.h>
#include <asm/asm-offsets.h>
#include <asm/coldfire.h>
#include <asm/mcfsim.h>
#include <asm/mcfmmu.h>
#include <asm/thread_info.h>

/*****************************************************************************/

/*
 *	If we don't have a fixed memory size, then lets build in code
 *	to auto detect the DRAM size. Obviously this is the preferred
 *	method, and should work for most boards. It won't work for those
 *	that do not have their RAM starting at address 0, and it only
 *	works on SDRAM (not boards fitted with SRAM).
 */
#if CONFIG_RAMSIZE != 0
.macro GET_MEM_SIZE
	movel	#CONFIG_RAMSIZE,%d0	/* hard coded memory size */
.endm

#elif defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \
      defined(CONFIG_M5249) || defined(CONFIG_M525x) || \
      defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
      defined(CONFIG_M5307) || defined(CONFIG_M5407)
/*
 *	Not all these devices have exactly the same DRAM controller,
 *	but the DCMR register is virtually identical - give or take
 *	a couple of bits. The only exception is the 5272 devices, their
 *	DRAM controller is quite different.
 */
.macro GET_MEM_SIZE
	movel	MCFSIM_DMR0,%d0		/* get mask for 1st bank */
	btst	#0,%d0			/* check if region enabled */
	beq	1f
	andl	#0xfffc0000,%d0
	beq	1f
	addl	#0x00040000,%d0		/* convert mask to size */
1:
	movel	MCFSIM_DMR1,%d1		/* get mask for 2nd bank */
	btst	#0,%d1			/* check if region enabled */
	beq	2f
	andl	#0xfffc0000,%d1
	beq	2f
	addl	#0x00040000,%d1
	addl	%d1,%d0			/* total mem size in d0 */
2:
.endm

#elif defined(CONFIG_M5272)
.macro GET_MEM_SIZE
	movel	MCFSIM_CSOR7,%d0	/* get SDRAM address mask */
	andil	#0xfffff000,%d0		/* mask out chip select options */
	negl	%d0			/* negate bits */
.endm

#elif defined(CONFIG_M520x)
.macro GET_MEM_SIZE
	clrl	%d0
	movel	MCFSIM_SDCS0, %d2	/* Get SDRAM chip select 0 config */
	andl	#0x1f, %d2		/* Get only the chip select size */
	beq	3f			/* Check if it is enabled */
	addql	#1, %d2			/* Form exponent */
	moveql	#1, %d0
	lsll	%d2, %d0		/* 2 ^ exponent */
3:
	movel	MCFSIM_SDCS1, %d2	/* Get SDRAM chip select 1 config */
	andl	#0x1f, %d2		/* Get only the chip select size */
	beq	4f			/* Check if it is enabled */
	addql	#1, %d2			/* Form exponent */
	moveql	#1, %d1
	lsll	%d2, %d1		/* 2 ^ exponent */
	addl	%d1, %d0		/* Total size of SDRAM in d0 */
4:
.endm

#else
#error "ERROR: I don't know how to probe your boards memory size?"
#endif

/*****************************************************************************/

/*
 *	Boards and platforms can do specific early hardware setup if
 *	they need to. Most don't need this, define away if not required.
 */
#ifndef PLATFORM_SETUP
#define	PLATFORM_SETUP
#endif

/*****************************************************************************/

.global	_start
.global _rambase
.global _ramvec
.global	_ramstart
.global	_ramend
#if defined(CONFIG_UBOOT)
.global	_init_sp
#endif

/*****************************************************************************/

.data

/*
 *	During startup we store away the RAM setup. These are not in the
 *	bss, since their values are determined and written before the bss
 *	has been cleared.
 */
_rambase:
.long	0
_ramvec:
.long	0
_ramstart:
.long	0
_ramend:
.long	0
#if defined(CONFIG_UBOOT)
_init_sp:
.long	0
#endif

/*****************************************************************************/

__HEAD

#ifdef CONFIG_MMU
_start0:
	jmp	_start
.global kernel_pg_dir
.equ	kernel_pg_dir,_start0
.equ	.,_start0+0x1000
#endif

/*
 *	This is the codes first entry point. This is where it all
 *	begins...
 */

_start:
	nop					/* filler */
	movew	#0x2700, %sr			/* no interrupts */
	movel	#CACHE_INIT,%d0			/* disable cache */
	movec	%d0,%CACR
	nop
#if defined(CONFIG_UBOOT)
	movel	%sp,_init_sp			/* save initial stack pointer */
#endif
#ifdef CONFIG_MBAR
	movel	#CONFIG_MBAR+1,%d0		/* configured MBAR address */
	movec	%d0,%MBAR			/* set it */
#endif

	/*
	 *	Do any platform or board specific setup now. Most boards
	 *	don't need anything. Those exceptions are define this in
	 *	their board specific includes.
	 */
	PLATFORM_SETUP

	/*
	 *	Create basic memory configuration. Set VBR accordingly,
	 *	and size memory.
	 */
	movel	#CONFIG_VECTORBASE,%a7
	movec   %a7,%VBR			/* set vectors addr */
	movel	%a7,_ramvec

	movel	#CONFIG_RAMBASE,%a7		/* mark the base of RAM */
	movel	%a7,_rambase

	GET_MEM_SIZE				/* macro code determines size */
	addl	%a7,%d0
	movel	%d0,_ramend			/* set end ram addr */

	/*
	 *	Now that we know what the memory is, lets enable cache
	 *	and get things moving. This is Coldfire CPU specific. Not
	 *	all version cores have identical cache register setup. But
	 *	it is very similar. Define the exact settings in the headers
	 *	then the code here is the same for all.
	 */
	movel	#ACR0_MODE,%d0			/* set RAM region for caching */
	movec	%d0,%ACR0
	movel	#ACR1_MODE,%d0			/* anything else to cache? */
	movec	%d0,%ACR1
#ifdef ACR2_MODE
	movel	#ACR2_MODE,%d0
	movec	%d0,%ACR2
	movel	#ACR3_MODE,%d0
	movec	%d0,%ACR3
#endif
	movel	#CACHE_MODE,%d0			/* enable cache */
	movec	%d0,%CACR
	nop

#ifdef CONFIG_MMU
	/*
	 *	Identity mapping for the kernel region.
	 */
	movel	#(MMUBASE+1),%d0		/* enable MMUBAR registers */
	movec	%d0,%MMUBAR
	movel	#MMUOR_CA,%d0			/* clear TLB entries */
	movel	%d0,MMUOR
	movel	#0,%d0				/* set ASID to 0 */
	movec	%d0,%asid

	movel	#MMUCR_EN,%d0			/* Enable the identity map */
	movel	%d0,MMUCR
	nop					/* sync i-pipeline */

	movel	#_vstart,%a0			/* jump to "virtual" space */
	jmp	%a0@
_vstart:
#endif /* CONFIG_MMU */

#ifdef CONFIG_ROMFS_FS
	/*
	 *	Move ROM filesystem above bss :-)
	 */
	lea	__bss_start,%a0			/* get start of bss */
	lea	__bss_stop,%a1			/* set up destination  */
	movel	%a0,%a2				/* copy of bss start */

	movel	8(%a0),%d0			/* get size of ROMFS */
	addql	#8,%d0				/* allow for rounding */
	andl	#0xfffffffc, %d0		/* whole words */

	addl	%d0,%a0				/* copy from end */
	addl	%d0,%a1				/* copy from end */
	movel	%a1,_ramstart			/* set start of ram */

_copy_romfs:
	movel	-(%a0),%d0			/* copy dword */
	movel	%d0,-(%a1)
	cmpl	%a0,%a2				/* check if at end */
	bne	_copy_romfs

#else /* CONFIG_ROMFS_FS */
	lea	__bss_stop,%a1
	movel	%a1,_ramstart
#endif /* CONFIG_ROMFS_FS */


	/*
	 *	Zero out the bss region.
	 */
	lea	__bss_start,%a0			/* get start of bss */
	lea	__bss_stop,%a1			/* get end of bss */
	clrl	%d0				/* set value */
_clear_bss:
	movel	%d0,(%a0)+			/* clear each word */
	cmpl	%a0,%a1				/* check if at end */
	bne	_clear_bss

	/*
	 *	Load the current task pointer and stack.
	 */
	lea	init_thread_union,%a0
	lea	THREAD_SIZE(%a0),%sp

#ifdef CONFIG_MMU
.global m68k_cputype
.global m68k_mmutype
.global m68k_fputype
.global m68k_machtype
	movel	#CPU_COLDFIRE,%d0
	movel	%d0,m68k_cputype		/* Mark us as a ColdFire */
	movel	#MMU_COLDFIRE,%d0
	movel	%d0,m68k_mmutype
	movel	#FPUTYPE,%d0
	movel	%d0,m68k_fputype		/* Mark FPU type */
	movel	#MACHINE,%d0
	movel	%d0,m68k_machtype		/* Mark machine type */
	lea	init_task,%a2			/* Set "current" init task */
#endif

	/*
	 *	Assembler start up done, start code proper.
	 */
	jsr	start_kernel			/* start Linux kernel */

_exit:
	jmp	_exit				/* should never get here */

/*****************************************************************************/
Commit	Line	Data
b2441318	1	/* SPDX-License-Identifier: GPL-2.0 */
1da177e4 LT	2	/*****************************************************************************/
	3
	4	/*
	5	* head.S -- common startup code for ColdFire CPUs.
	6	*
0079fe75	7	* (C) Copyright 1999-2011, Greg Ungerer <gerg@snapgear.com>.
1da177e4 LT	8	*/
	9
	10	/*****************************************************************************/
	11
1da177e4	12	#include <linux/linkage.h>
9b0e7410	13	#include <linux/init.h>
1da177e4 LT	14	#include <asm/asm-offsets.h>
1da177e4 LT	15	#include <asm/coldfire.h>
1da177e4	16	#include <asm/mcfsim.h>
0079fe75	17	#include <asm/mcfmmu.h>
df9ee292	18	#include <asm/thread_info.h>
1da177e4 LT	19
	20	/*****************************************************************************/
	21
	22	/*
12ddae33	23	* If we don't have a fixed memory size, then lets build in code
25985edc	24	* to auto detect the DRAM size. Obviously this is the preferred
12ddae33 GU	25	* method, and should work for most boards. It won't work for those
	26	* that do not have their RAM starting at address 0, and it only
	27	* works on SDRAM (not boards fitted with SRAM).
1da177e4	28	*/
12ddae33	29	#if CONFIG_RAMSIZE != 0
1da177e4	30	.macro GET_MEM_SIZE
12ddae33	31	movel #CONFIG_RAMSIZE,%d0 /* hard coded memory size */
1da177e4 LT	32	.endm
	33
	34	#elif defined(CONFIG_M5206) \|\| defined(CONFIG_M5206e) \|\| \
04e037aa SK	35	defined(CONFIG_M5249) \|\| defined(CONFIG_M525x) \|\| \
	36	defined(CONFIG_M527x) \|\| defined(CONFIG_M528x) \|\| \
	37	defined(CONFIG_M5307) \|\| defined(CONFIG_M5407)
1da177e4 LT	38	/*
	39	* Not all these devices have exactly the same DRAM controller,
	40	* but the DCMR register is virtually identical - give or take
	41	* a couple of bits. The only exception is the 5272 devices, their
	42	* DRAM controller is quite different.
	43	*/
	44	.macro GET_MEM_SIZE
6a92e198	45	movel MCFSIM_DMR0,%d0 /* get mask for 1st bank */
1da177e4 LT	46	btst #0,%d0 /* check if region enabled */
	47	beq 1f
	48	andl #0xfffc0000,%d0
	49	beq 1f
	50	addl #0x00040000,%d0 /* convert mask to size */
	51	1:
6a92e198	52	movel MCFSIM_DMR1,%d1 /* get mask for 2nd bank */
1da177e4 LT	53	btst #0,%d1 /* check if region enabled */
1da177e4 LT	54	beq 2f
6a92e198	55	andl #0xfffc0000,%d1
1da177e4 LT	56	beq 2f
	57	addl #0x00040000,%d1
	58	addl %d1,%d0 /* total mem size in d0 */
	59	2:
	60	.endm
	61
	62	#elif defined(CONFIG_M5272)
	63	.macro GET_MEM_SIZE
1419ea3b	64	movel MCFSIM_CSOR7,%d0 /* get SDRAM address mask */
1da177e4 LT	65	andil #0xfffff000,%d0 /* mask out chip select options */
	66	negl %d0 /* negate bits */
	67	.endm
55298405 MB	68
	69	#elif defined(CONFIG_M520x)
	70	.macro GET_MEM_SIZE
	71	clrl %d0
571f0608	72	movel MCFSIM_SDCS0, %d2 /* Get SDRAM chip select 0 config */
55298405 MB	73	andl #0x1f, %d2 /* Get only the chip select size */
	74	beq 3f /* Check if it is enabled */
	75	addql #1, %d2 /* Form exponent */
	76	moveql #1, %d0
	77	lsll %d2, %d0 /* 2 ^ exponent */
	78	3:
571f0608	79	movel MCFSIM_SDCS1, %d2 /* Get SDRAM chip select 1 config */
55298405 MB	80	andl #0x1f, %d2 /* Get only the chip select size */
	81	beq 4f /* Check if it is enabled */
	82	addql #1, %d2 /* Form exponent */
	83	moveql #1, %d1
	84	lsll %d2, %d1 /* 2 ^ exponent */
	85	addl %d1, %d0 /* Total size of SDRAM in d0 */
	86	4:
	87	.endm
1da177e4 LT	88
1da177e4 LT	89	#else
12ddae33	90	#error "ERROR: I don't know how to probe your boards memory size?"
1da177e4 LT	91	#endif
	92
	93	/*****************************************************************************/
	94
	95	/*
	96	* Boards and platforms can do specific early hardware setup if
	97	* they need to. Most don't need this, define away if not required.
	98	*/
	99	#ifndef PLATFORM_SETUP
	100	#define PLATFORM_SETUP
	101	#endif
	102
	103	/*****************************************************************************/
	104
	105	.global _start
	106	.global _rambase
	107	.global _ramvec
	108	.global _ramstart
	109	.global _ramend
588baeac LS	110	#if defined(CONFIG_UBOOT)
	111	.global _init_sp
	112	#endif
1da177e4 LT	113
	114	/*****************************************************************************/
	115
	116	.data
	117
	118	/*
	119	* During startup we store away the RAM setup. These are not in the
	120	* bss, since their values are determined and written before the bss
	121	* has been cleared.
	122	*/
	123	_rambase:
	124	.long 0
	125	_ramvec:
	126	.long 0
	127	_ramstart:
	128	.long 0
	129	_ramend:
	130	.long 0
588baeac LS	131	#if defined(CONFIG_UBOOT)
	132	_init_sp:
	133	.long 0
	134	#endif
1da177e4 LT	135
	136	/*****************************************************************************/
	137
9b0e7410	138	__HEAD
1da177e4	139
0079fe75 GU	140	#ifdef CONFIG_MMU
	141	_start0:
	142	jmp _start
	143	.global kernel_pg_dir
	144	.equ kernel_pg_dir,_start0
	145	.equ .,_start0+0x1000
	146	#endif
	147
1da177e4 LT	148	/*
	149	* This is the codes first entry point. This is where it all
	150	* begins...
	151	*/
	152
	153	_start:
	154	nop /* filler */
	155	movew #0x2700, %sr /* no interrupts */
ec841187 GU	156	movel #CACHE_INIT,%d0 /* disable cache */
	157	movec %d0,%CACR
	158	nop
588baeac LS	159	#if defined(CONFIG_UBOOT)
	160	movel %sp,_init_sp /* save initial stack pointer */
	161	#endif
10cb54de GU	162	#ifdef CONFIG_MBAR
	163	movel #CONFIG_MBAR+1,%d0 /* configured MBAR address */
	164	movec %d0,%MBAR /* set it */
	165	#endif
1da177e4 LT	166
	167	/*
	168	* Do any platform or board specific setup now. Most boards
	169	* don't need anything. Those exceptions are define this in
	170	* their board specific includes.
	171	*/
	172	PLATFORM_SETUP
	173
	174	/*
	175	* Create basic memory configuration. Set VBR accordingly,
	176	* and size memory.
	177	*/
12ddae33	178	movel #CONFIG_VECTORBASE,%a7
1da177e4 LT	179	movec %a7,%VBR /* set vectors addr */
	180	movel %a7,_ramvec
	181
12ddae33	182	movel #CONFIG_RAMBASE,%a7 /* mark the base of RAM */
1da177e4 LT	183	movel %a7,_rambase
	184
	185	GET_MEM_SIZE /* macro code determines size */
029fc137	186	addl %a7,%d0
1da177e4 LT	187	movel %d0,_ramend /* set end ram addr */
	188
	189	/*
	190	* Now that we know what the memory is, lets enable cache
8ce877a8 GU	191	* and get things moving. This is Coldfire CPU specific. Not
	192	* all version cores have identical cache register setup. But
	193	* it is very similar. Define the exact settings in the headers
	194	* then the code here is the same for all.
1da177e4	195	*/
8ce877a8 GU	196	movel #ACR0_MODE,%d0 /* set RAM region for caching */
	197	movec %d0,%ACR0
	198	movel #ACR1_MODE,%d0 /* anything else to cache? */
	199	movec %d0,%ACR1
	200	#ifdef ACR2_MODE
	201	movel #ACR2_MODE,%d0
	202	movec %d0,%ACR2
	203	movel #ACR3_MODE,%d0
	204	movec %d0,%ACR3
	205	#endif
	206	movel #CACHE_MODE,%d0 /* enable cache */
	207	movec %d0,%CACR
	208	nop
1da177e4	209
0079fe75 GU	210	#ifdef CONFIG_MMU
	211	/*
	212	* Identity mapping for the kernel region.
	213	*/
	214	movel #(MMUBASE+1),%d0 /* enable MMUBAR registers */
	215	movec %d0,%MMUBAR
	216	movel #MMUOR_CA,%d0 /* clear TLB entries */
	217	movel %d0,MMUOR
	218	movel #0,%d0 /* set ASID to 0 */
	219	movec %d0,%asid
	220
	221	movel #MMUCR_EN,%d0 /* Enable the identity map */
	222	movel %d0,MMUCR
	223	nop /* sync i-pipeline */
	224
	225	movel #_vstart,%a0 /* jump to "virtual" space */
	226	jmp %a0@
	227	_vstart:
	228	#endif /* CONFIG_MMU */
	229
1da177e4 LT	230	#ifdef CONFIG_ROMFS_FS
	231	/*
	232	* Move ROM filesystem above bss :-)
	233	*/
dc061051 GU	234	lea __bss_start,%a0 /* get start of bss */
dc061051 GU	235	lea __bss_stop,%a1 /* set up destination */
1da177e4 LT	236	movel %a0,%a2 /* copy of bss start */
	237
	238	movel 8(%a0),%d0 /* get size of ROMFS */
	239	addql #8,%d0 /* allow for rounding */
	240	andl #0xfffffffc, %d0 /* whole words */
	241
	242	addl %d0,%a0 /* copy from end */
	243	addl %d0,%a1 /* copy from end */
	244	movel %a1,_ramstart /* set start of ram */
	245
	246	_copy_romfs:
	247	movel -(%a0),%d0 /* copy dword */
	248	movel %d0,-(%a1)
	249	cmpl %a0,%a2 /* check if at end */
	250	bne _copy_romfs
	251
	252	#else /* CONFIG_ROMFS_FS */
dc061051	253	lea __bss_stop,%a1
1da177e4 LT	254	movel %a1,_ramstart
	255	#endif /* CONFIG_ROMFS_FS */
	256
	257
	258	/*
	259	* Zero out the bss region.
	260	*/
dc061051 GU	261	lea __bss_start,%a0 /* get start of bss */
dc061051 GU	262	lea __bss_stop,%a1 /* get end of bss */
1da177e4 LT	263	clrl %d0 /* set value */
	264	_clear_bss:
	265	movel %d0,(%a0)+ /* clear each word */
	266	cmpl %a0,%a1 /* check if at end */
	267	bne _clear_bss
	268
	269	/*
	270	* Load the current task pointer and stack.
	271	*/
	272	lea init_thread_union,%a0
	273	lea THREAD_SIZE(%a0),%sp
	274
0079fe75 GU	275	#ifdef CONFIG_MMU
	276	.global m68k_cputype
	277	.global m68k_mmutype
	278	.global m68k_fputype
	279	.global m68k_machtype
	280	movel #CPU_COLDFIRE,%d0
	281	movel %d0,m68k_cputype /* Mark us as a ColdFire */
	282	movel #MMU_COLDFIRE,%d0
	283	movel %d0,m68k_mmutype
cbd5b982 GU	284	movel #FPUTYPE,%d0
cbd5b982 GU	285	movel %d0,m68k_fputype /* Mark FPU type */
81d33350 GU	286	movel #MACHINE,%d0
81d33350 GU	287	movel %d0,m68k_machtype /* Mark machine type */
0079fe75 GU	288	lea init_task,%a2 /* Set "current" init task */
	289	#endif
	290
1da177e4	291	/*
86a8280a	292	* Assembler start up done, start code proper.
1da177e4 LT	293	*/
	294	jsr start_kernel /* start Linux kernel */
	295
	296	_exit:
	297	jmp _exit /* should never get here */
	298
	299	/*****************************************************************************/