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Commit | Line | Data |
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1da177e4 LT |
1 | /***************************************************************************/ |
2 | ||
3 | /* | |
ece9ae65 | 4 | * m527x.c -- platform support for ColdFire 527x based boards |
1da177e4 | 5 | * |
25985edc | 6 | * Sub-architcture dependent initialization code for the Freescale |
ece9ae65 | 7 | * 5270/5271 and 5274/5275 CPUs. |
1da177e4 LT |
8 | * |
9 | * Copyright (C) 1999-2004, Greg Ungerer (gerg@snapgear.com) | |
10 | * Copyright (C) 2001-2004, SnapGear Inc. (www.snapgear.com) | |
11 | */ | |
12 | ||
13 | /***************************************************************************/ | |
14 | ||
1da177e4 | 15 | #include <linux/kernel.h> |
1da177e4 LT |
16 | #include <linux/param.h> |
17 | #include <linux/init.h> | |
e206da0b | 18 | #include <linux/io.h> |
1da177e4 LT |
19 | #include <asm/machdep.h> |
20 | #include <asm/coldfire.h> | |
21 | #include <asm/mcfsim.h> | |
e206da0b | 22 | #include <asm/mcfuart.h> |
a3d8eb0d GU |
23 | #include <asm/mcfclk.h> |
24 | ||
25 | /***************************************************************************/ | |
26 | ||
27 | DEFINE_CLK(pll, "pll.0", MCF_CLK); | |
28 | DEFINE_CLK(sys, "sys.0", MCF_BUSCLK); | |
29 | DEFINE_CLK(mcfpit0, "mcfpit.0", MCF_CLK); | |
30 | DEFINE_CLK(mcfpit1, "mcfpit.1", MCF_CLK); | |
31 | DEFINE_CLK(mcfpit2, "mcfpit.2", MCF_CLK); | |
32 | DEFINE_CLK(mcfpit3, "mcfpit.3", MCF_CLK); | |
33 | DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK); | |
34 | DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK); | |
35 | DEFINE_CLK(mcfuart2, "mcfuart.2", MCF_BUSCLK); | |
74859523 | 36 | DEFINE_CLK(mcfqspi0, "mcfqspi.0", MCF_BUSCLK); |
a3d8eb0d GU |
37 | DEFINE_CLK(fec0, "fec.0", MCF_BUSCLK); |
38 | DEFINE_CLK(fec1, "fec.1", MCF_BUSCLK); | |
39 | ||
40 | struct clk *mcf_clks[] = { | |
41 | &clk_pll, | |
42 | &clk_sys, | |
43 | &clk_mcfpit0, | |
44 | &clk_mcfpit1, | |
45 | &clk_mcfpit2, | |
46 | &clk_mcfpit3, | |
47 | &clk_mcfuart0, | |
48 | &clk_mcfuart1, | |
49 | &clk_mcfuart2, | |
74859523 | 50 | &clk_mcfqspi0, |
a3d8eb0d GU |
51 | &clk_fec0, |
52 | &clk_fec1, | |
53 | NULL | |
54 | }; | |
1da177e4 LT |
55 | |
56 | /***************************************************************************/ | |
57 | ||
91d60417 SK |
58 | static void __init m527x_qspi_init(void) |
59 | { | |
151d14f4 | 60 | #if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) |
91d60417 SK |
61 | #if defined(CONFIG_M5271) |
62 | u16 par; | |
63 | ||
64 | /* setup QSPS pins for QSPI with gpio CS control */ | |
65 | writeb(0x1f, MCFGPIO_PAR_QSPI); | |
66 | /* and CS2 & CS3 as gpio */ | |
67 | par = readw(MCFGPIO_PAR_TIMER); | |
68 | par &= 0x3f3f; | |
69 | writew(par, MCFGPIO_PAR_TIMER); | |
70 | #elif defined(CONFIG_M5275) | |
71 | /* setup QSPS pins for QSPI with gpio CS control */ | |
72 | writew(0x003e, MCFGPIO_PAR_QSPI); | |
73 | #endif | |
83ca6009 | 74 | #endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */ |
151d14f4 | 75 | } |
e206da0b GU |
76 | |
77 | /***************************************************************************/ | |
78 | ||
1eb13916 | 79 | static void __init m527x_uarts_init(void) |
e206da0b GU |
80 | { |
81 | u16 sepmask; | |
e206da0b | 82 | |
e206da0b GU |
83 | /* |
84 | * External Pin Mask Setting & Enable External Pin for Interface | |
85 | */ | |
f821e349 | 86 | sepmask = readw(MCFGPIO_PAR_UART); |
1eb13916 | 87 | sepmask |= UART0_ENABLE_MASK | UART1_ENABLE_MASK | UART2_ENABLE_MASK; |
f821e349 | 88 | writew(sepmask, MCFGPIO_PAR_UART); |
e206da0b GU |
89 | } |
90 | ||
1da177e4 LT |
91 | /***************************************************************************/ |
92 | ||
ffba3f48 GU |
93 | static void __init m527x_fec_init(void) |
94 | { | |
ffba3f48 GU |
95 | u8 v; |
96 | ||
ffba3f48 | 97 | /* Set multi-function pins to ethernet mode for fec0 */ |
592578a1 | 98 | #if defined(CONFIG_M5271) |
f821e349 GU |
99 | v = readb(MCFGPIO_PAR_FECI2C); |
100 | writeb(v | 0xf0, MCFGPIO_PAR_FECI2C); | |
592578a1 | 101 | #else |
6e420613 GU |
102 | u16 par; |
103 | ||
f821e349 GU |
104 | par = readw(MCFGPIO_PAR_FECI2C); |
105 | writew(par | 0xf00, MCFGPIO_PAR_FECI2C); | |
106 | v = readb(MCFGPIO_PAR_FEC0HL); | |
107 | writeb(v | 0xc0, MCFGPIO_PAR_FEC0HL); | |
ffba3f48 | 108 | |
ffba3f48 | 109 | /* Set multi-function pins to ethernet mode for fec1 */ |
f821e349 GU |
110 | par = readw(MCFGPIO_PAR_FECI2C); |
111 | writew(par | 0xa0, MCFGPIO_PAR_FECI2C); | |
112 | v = readb(MCFGPIO_PAR_FEC1HL); | |
113 | writeb(v | 0xc0, MCFGPIO_PAR_FEC1HL); | |
ffba3f48 GU |
114 | #endif |
115 | } | |
116 | ||
117 | /***************************************************************************/ | |
118 | ||
e206da0b | 119 | void __init config_BSP(char *commandp, int size) |
1da177e4 | 120 | { |
35aefb26 | 121 | mach_sched_init = hw_timer_init; |
ffba3f48 GU |
122 | m527x_uarts_init(); |
123 | m527x_fec_init(); | |
91d60417 | 124 | m527x_qspi_init(); |
1da177e4 LT |
125 | } |
126 | ||
127 | /***************************************************************************/ |