]>
Commit | Line | Data |
---|---|---|
b2441318 | 1 | // SPDX-License-Identifier: GPL-2.0 |
1da177e4 LT |
2 | /***************************************************************************/ |
3 | ||
4 | /* | |
ece9ae65 | 5 | * m528x.c -- platform support for ColdFire 528x based boards |
1da177e4 | 6 | * |
25985edc | 7 | * Sub-architcture dependent initialization code for the Freescale |
980f9235 | 8 | * 5280, 5281 and 5282 CPUs. |
1da177e4 LT |
9 | * |
10 | * Copyright (C) 1999-2003, Greg Ungerer (gerg@snapgear.com) | |
11 | * Copyright (C) 2001-2003, SnapGear Inc. (www.snapgear.com) | |
12 | */ | |
13 | ||
14 | /***************************************************************************/ | |
15 | ||
1da177e4 | 16 | #include <linux/kernel.h> |
1da177e4 LT |
17 | #include <linux/param.h> |
18 | #include <linux/init.h> | |
eb49e907 | 19 | #include <linux/platform_device.h> |
eb49e907 | 20 | #include <linux/io.h> |
1da177e4 LT |
21 | #include <asm/machdep.h> |
22 | #include <asm/coldfire.h> | |
23 | #include <asm/mcfsim.h> | |
eb49e907 | 24 | #include <asm/mcfuart.h> |
87f37769 GU |
25 | #include <asm/mcfclk.h> |
26 | ||
27 | /***************************************************************************/ | |
28 | ||
29 | DEFINE_CLK(pll, "pll.0", MCF_CLK); | |
30 | DEFINE_CLK(sys, "sys.0", MCF_BUSCLK); | |
31 | DEFINE_CLK(mcfpit0, "mcfpit.0", MCF_CLK); | |
32 | DEFINE_CLK(mcfpit1, "mcfpit.1", MCF_CLK); | |
33 | DEFINE_CLK(mcfpit2, "mcfpit.2", MCF_CLK); | |
34 | DEFINE_CLK(mcfpit3, "mcfpit.3", MCF_CLK); | |
35 | DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK); | |
36 | DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK); | |
37 | DEFINE_CLK(mcfuart2, "mcfuart.2", MCF_BUSCLK); | |
74859523 | 38 | DEFINE_CLK(mcfqspi0, "mcfqspi.0", MCF_BUSCLK); |
87f37769 | 39 | DEFINE_CLK(fec0, "fec.0", MCF_BUSCLK); |
2d24b532 | 40 | DEFINE_CLK(mcfi2c0, "imx1-i2c.0", MCF_BUSCLK); |
87f37769 GU |
41 | |
42 | struct clk *mcf_clks[] = { | |
43 | &clk_pll, | |
44 | &clk_sys, | |
45 | &clk_mcfpit0, | |
46 | &clk_mcfpit1, | |
47 | &clk_mcfpit2, | |
48 | &clk_mcfpit3, | |
49 | &clk_mcfuart0, | |
50 | &clk_mcfuart1, | |
51 | &clk_mcfuart2, | |
74859523 | 52 | &clk_mcfqspi0, |
87f37769 | 53 | &clk_fec0, |
2d24b532 | 54 | &clk_mcfi2c0, |
87f37769 GU |
55 | NULL |
56 | }; | |
1da177e4 LT |
57 | |
58 | /***************************************************************************/ | |
59 | ||
91d60417 SK |
60 | static void __init m528x_qspi_init(void) |
61 | { | |
151d14f4 | 62 | #if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) |
91d60417 SK |
63 | /* setup Port QS for QSPI with gpio CS control */ |
64 | __raw_writeb(0x07, MCFGPIO_PQSPAR); | |
83ca6009 | 65 | #endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */ |
151d14f4 | 66 | } |
eb49e907 GU |
67 | |
68 | /***************************************************************************/ | |
69 | ||
2d24b532 SK |
70 | static void __init m528x_i2c_init(void) |
71 | { | |
72 | #if IS_ENABLED(CONFIG_I2C_IMX) | |
73 | u16 paspar; | |
74 | ||
75 | /* setup Port AS Pin Assignment Register for I2C */ | |
76 | /* set PASPA0 to SCL and PASPA1 to SDA */ | |
77 | paspar = readw(MCFGPIO_PASPAR); | |
78 | paspar |= 0xF; | |
79 | writew(paspar, MCFGPIO_PASPAR); | |
80 | #endif /* IS_ENABLED(CONFIG_I2C_IMX) */ | |
81 | } | |
82 | ||
83 | /***************************************************************************/ | |
84 | ||
cae82a83 | 85 | static void __init m528x_uarts_init(void) |
eb49e907 GU |
86 | { |
87 | u8 port; | |
eb49e907 | 88 | |
eb49e907 | 89 | /* make sure PUAPAR is set for UART0 and UART1 */ |
0371a1c5 | 90 | port = readb(MCFGPIO_PUAPAR); |
cae82a83 | 91 | port |= 0x03 | (0x03 << 2); |
eac57949 | 92 | writeb(port, MCFGPIO_PUAPAR); |
eb49e907 | 93 | } |
1da177e4 LT |
94 | |
95 | /***************************************************************************/ | |
96 | ||
ffba3f48 GU |
97 | static void __init m528x_fec_init(void) |
98 | { | |
ffba3f48 GU |
99 | u16 v16; |
100 | ||
ffba3f48 | 101 | /* Set multi-function pins to ethernet mode for fec0 */ |
a91f7415 GU |
102 | v16 = readw(MCFGPIO_PASPAR); |
103 | writew(v16 | 0xf00, MCFGPIO_PASPAR); | |
104 | writeb(0xc0, MCFGPIO_PEHLPAR); | |
ffba3f48 GU |
105 | } |
106 | ||
107 | /***************************************************************************/ | |
108 | ||
188a9a48 SB |
109 | #ifdef CONFIG_WILDFIRE |
110 | void wildfire_halt(void) | |
111 | { | |
112 | writeb(0, 0x30000007); | |
113 | writeb(0x2, 0x30000007); | |
114 | } | |
115 | #endif | |
116 | ||
117 | #ifdef CONFIG_WILDFIREMOD | |
118 | void wildfiremod_halt(void) | |
119 | { | |
120 | printk(KERN_INFO "WildFireMod hibernating...\n"); | |
121 | ||
122 | /* Set portE.5 to Digital IO */ | |
41b39ea1 | 123 | writew(readw(MCFGPIO_PEPAR) & ~(1 << (5 * 2)), MCFGPIO_PEPAR); |
188a9a48 SB |
124 | |
125 | /* Make portE.5 an output */ | |
41b39ea1 | 126 | writeb(readb(MCFGPIO_PDDR_E) | (1 << 5), MCFGPIO_PDDR_E); |
188a9a48 SB |
127 | |
128 | /* Now toggle portE.5 from low to high */ | |
41b39ea1 GU |
129 | writeb(readb(MCFGPIO_PODR_E) & ~(1 << 5), MCFGPIO_PODR_E); |
130 | writeb(readb(MCFGPIO_PODR_E) | (1 << 5), MCFGPIO_PODR_E); | |
188a9a48 SB |
131 | |
132 | printk(KERN_EMERG "Failed to hibernate. Halting!\n"); | |
133 | } | |
134 | #endif | |
135 | ||
eb49e907 | 136 | void __init config_BSP(char *commandp, int size) |
1da177e4 | 137 | { |
188a9a48 SB |
138 | #ifdef CONFIG_WILDFIRE |
139 | mach_halt = wildfire_halt; | |
140 | #endif | |
141 | #ifdef CONFIG_WILDFIREMOD | |
142 | mach_halt = wildfiremod_halt; | |
143 | #endif | |
35aefb26 | 144 | mach_sched_init = hw_timer_init; |
eb49e907 | 145 | m528x_uarts_init(); |
ffba3f48 | 146 | m528x_fec_init(); |
91d60417 | 147 | m528x_qspi_init(); |
2d24b532 | 148 | m528x_i2c_init(); |
eb49e907 GU |
149 | } |
150 | ||
eb49e907 | 151 | /***************************************************************************/ |