[mirror_ubuntu-focal-kernel.git] / arch / m68k / coldfire / pit.c

// SPDX-License-Identifier: GPL-2.0
/***************************************************************************/

/*
 *	pit.c -- Freescale ColdFire PIT timer. Currently this type of
 *	         hardware timer only exists in the Freescale ColdFire
 *		 5270/5271, 5282 and 5208 CPUs. No doubt newer ColdFire
 *		 family members will probably use it too.
 *
 *	Copyright (C) 1999-2008, Greg Ungerer (gerg@snapgear.com)
 *	Copyright (C) 2001-2004, SnapGear Inc. (www.snapgear.com)
 */

/***************************************************************************/

#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/param.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/clockchips.h>
#include <asm/machdep.h>
#include <asm/io.h>
#include <asm/coldfire.h>
#include <asm/mcfpit.h>
#include <asm/mcfsim.h>

/***************************************************************************/

/*
 *	By default use timer1 as the system clock timer.
 */
#define	FREQ	((MCF_CLK / 2) / 64)
#define	TA(a)	(MCFPIT_BASE1 + (a))
#define PIT_CYCLES_PER_JIFFY (FREQ / HZ)

static u32 pit_cnt;

/*
 * Initialize the PIT timer.
 *
 * This is also called after resume to bring the PIT into operation again.
 */

static int cf_pit_set_periodic(struct clock_event_device *evt)
{
	__raw_writew(MCFPIT_PCSR_DISABLE, TA(MCFPIT_PCSR));
	__raw_writew(PIT_CYCLES_PER_JIFFY, TA(MCFPIT_PMR));
	__raw_writew(MCFPIT_PCSR_EN | MCFPIT_PCSR_PIE |
		     MCFPIT_PCSR_OVW | MCFPIT_PCSR_RLD |
		     MCFPIT_PCSR_CLK64, TA(MCFPIT_PCSR));
	return 0;
}

static int cf_pit_set_oneshot(struct clock_event_device *evt)
{
	__raw_writew(MCFPIT_PCSR_DISABLE, TA(MCFPIT_PCSR));
	__raw_writew(MCFPIT_PCSR_EN | MCFPIT_PCSR_PIE |
		     MCFPIT_PCSR_OVW | MCFPIT_PCSR_CLK64, TA(MCFPIT_PCSR));
	return 0;
}

static int cf_pit_shutdown(struct clock_event_device *evt)
{
	__raw_writew(MCFPIT_PCSR_DISABLE, TA(MCFPIT_PCSR));
	return 0;
}

/*
 * Program the next event in oneshot mode
 *
 * Delta is given in PIT ticks
 */
static int cf_pit_next_event(unsigned long delta,
		struct clock_event_device *evt)
{
	__raw_writew(delta, TA(MCFPIT_PMR));
	return 0;
}

struct clock_event_device cf_pit_clockevent = {
	.name			= "pit",
	.features		= CLOCK_EVT_FEAT_PERIODIC |
				  CLOCK_EVT_FEAT_ONESHOT,
	.set_state_shutdown	= cf_pit_shutdown,
	.set_state_periodic	= cf_pit_set_periodic,
	.set_state_oneshot	= cf_pit_set_oneshot,
	.set_next_event		= cf_pit_next_event,
	.shift			= 32,
	.irq			= MCF_IRQ_PIT1,
};


/***************************************************************************/

static irqreturn_t pit_tick(int irq, void *dummy)
{
	struct clock_event_device *evt = &cf_pit_clockevent;
	u16 pcsr;

	/* Reset the ColdFire timer */
	pcsr = __raw_readw(TA(MCFPIT_PCSR));
	__raw_writew(pcsr | MCFPIT_PCSR_PIF, TA(MCFPIT_PCSR));

	pit_cnt += PIT_CYCLES_PER_JIFFY;
	evt->event_handler(evt);
	return IRQ_HANDLED;
}

/***************************************************************************/

static struct irqaction pit_irq = {
	.name	 = "timer",
	.flags	 = IRQF_TIMER,
	.handler = pit_tick,
};

/***************************************************************************/

static u64 pit_read_clk(struct clocksource *cs)
{
	unsigned long flags;
	u32 cycles;
	u16 pcntr;

	local_irq_save(flags);
	pcntr = __raw_readw(TA(MCFPIT_PCNTR));
	cycles = pit_cnt;
	local_irq_restore(flags);

	return cycles + PIT_CYCLES_PER_JIFFY - pcntr;
}

/***************************************************************************/

static struct clocksource pit_clk = {
	.name	= "pit",
	.rating	= 100,
	.read	= pit_read_clk,
	.mask	= CLOCKSOURCE_MASK(32),
};

/***************************************************************************/

void hw_timer_init(irq_handler_t handler)
{
	cf_pit_clockevent.cpumask = cpumask_of(smp_processor_id());
	cf_pit_clockevent.mult = div_sc(FREQ, NSEC_PER_SEC, 32);
	cf_pit_clockevent.max_delta_ns =
		clockevent_delta2ns(0xFFFF, &cf_pit_clockevent);
	cf_pit_clockevent.max_delta_ticks = 0xFFFF;
	cf_pit_clockevent.min_delta_ns =
		clockevent_delta2ns(0x3f, &cf_pit_clockevent);
	cf_pit_clockevent.min_delta_ticks = 0x3f;
	clockevents_register_device(&cf_pit_clockevent);

	setup_irq(MCF_IRQ_PIT1, &pit_irq);

	clocksource_register_hz(&pit_clk, FREQ);
}

/***************************************************************************/
Commit	Line	Data
b2441318	1	// SPDX-License-Identifier: GPL-2.0
1da177e4 LT	2	/***************************************************************************/
	3
	4	/*
b671b653 GU	5	* pit.c -- Freescale ColdFire PIT timer. Currently this type of
b671b653 GU	6	* hardware timer only exists in the Freescale ColdFire
8d80c5ee GU	7	* 5270/5271, 5282 and 5208 CPUs. No doubt newer ColdFire
8d80c5ee GU	8	* family members will probably use it too.
1da177e4	9	*
8d80c5ee	10	* Copyright (C) 1999-2008, Greg Ungerer (gerg@snapgear.com)
1da177e4	11	* Copyright (C) 2001-2004, SnapGear Inc. (www.snapgear.com)
1da177e4 LT	12	*/
	13
	14	/***************************************************************************/
	15
1da177e4 LT	16	#include <linux/kernel.h>
	17	#include <linux/sched.h>
	18	#include <linux/param.h>
	19	#include <linux/init.h>
	20	#include <linux/interrupt.h>
5c4525da	21	#include <linux/irq.h>
2b9a6986	22	#include <linux/clockchips.h>
2f2c2679	23	#include <asm/machdep.h>
b671b653	24	#include <asm/io.h>
1da177e4 LT	25	#include <asm/coldfire.h>
	26	#include <asm/mcfpit.h>
	27	#include <asm/mcfsim.h>
	28
	29	/***************************************************************************/
	30
b671b653 GU	31	/*
	32	* By default use timer1 as the system clock timer.
	33	*/
8d80c5ee	34	#define FREQ ((MCF_CLK / 2) / 64)
f317c71a	35	#define TA(a) (MCFPIT_BASE1 + (a))
2b9a6986	36	#define PIT_CYCLES_PER_JIFFY (FREQ / HZ)
8d80c5ee	37
8d80c5ee	38	static u32 pit_cnt;
b671b653	39
2b9a6986 SS	40	/*
	41	* Initialize the PIT timer.
	42	*
	43	* This is also called after resume to bring the PIT into operation again.
	44	*/
	45
5bbc08fb	46	static int cf_pit_set_periodic(struct clock_event_device *evt)
2b9a6986	47	{
5bbc08fb VK	48	__raw_writew(MCFPIT_PCSR_DISABLE, TA(MCFPIT_PCSR));
	49	__raw_writew(PIT_CYCLES_PER_JIFFY, TA(MCFPIT_PMR));
	50	__raw_writew(MCFPIT_PCSR_EN \| MCFPIT_PCSR_PIE \|
	51	MCFPIT_PCSR_OVW \| MCFPIT_PCSR_RLD \|
	52	MCFPIT_PCSR_CLK64, TA(MCFPIT_PCSR));
	53	return 0;
	54	}
	55
	56	static int cf_pit_set_oneshot(struct clock_event_device *evt)
	57	{
	58	__raw_writew(MCFPIT_PCSR_DISABLE, TA(MCFPIT_PCSR));
	59	__raw_writew(MCFPIT_PCSR_EN \| MCFPIT_PCSR_PIE \|
	60	MCFPIT_PCSR_OVW \| MCFPIT_PCSR_CLK64, TA(MCFPIT_PCSR));
	61	return 0;
	62	}
	63
	64	static int cf_pit_shutdown(struct clock_event_device *evt)
	65	{
	66	__raw_writew(MCFPIT_PCSR_DISABLE, TA(MCFPIT_PCSR));
	67	return 0;
2b9a6986 SS	68	}
	69
	70	/*
	71	* Program the next event in oneshot mode
	72	*
	73	* Delta is given in PIT ticks
	74	*/
	75	static int cf_pit_next_event(unsigned long delta,
	76	struct clock_event_device *evt)
	77	{
	78	__raw_writew(delta, TA(MCFPIT_PMR));
	79	return 0;
	80	}
	81
	82	struct clock_event_device cf_pit_clockevent = {
5bbc08fb VK	83	.name = "pit",
	84	.features = CLOCK_EVT_FEAT_PERIODIC \|
	85	CLOCK_EVT_FEAT_ONESHOT,
	86	.set_state_shutdown = cf_pit_shutdown,
	87	.set_state_periodic = cf_pit_set_periodic,
	88	.set_state_oneshot = cf_pit_set_oneshot,
	89	.set_next_event = cf_pit_next_event,
	90	.shift = 32,
	91	.irq = MCF_IRQ_PIT1,
2b9a6986 SS	92	};
	93
	94
	95
b671b653 GU	96	/***************************************************************************/
b671b653 GU	97
8d80c5ee	98	static irqreturn_t pit_tick(int irq, void *dummy)
1da177e4	99	{
2b9a6986	100	struct clock_event_device *evt = &cf_pit_clockevent;
8d80c5ee	101	u16 pcsr;
1da177e4 LT	102
1da177e4 LT	103	/* Reset the ColdFire timer */
b671b653 GU	104	pcsr = __raw_readw(TA(MCFPIT_PCSR));
b671b653 GU	105	__raw_writew(pcsr \| MCFPIT_PCSR_PIF, TA(MCFPIT_PCSR));
2f2c2679	106
2b9a6986 SS	107	pit_cnt += PIT_CYCLES_PER_JIFFY;
	108	evt->event_handler(evt);
	109	return IRQ_HANDLED;
1da177e4 LT	110	}
	111
	112	/***************************************************************************/
	113
8d80c5ee	114	static struct irqaction pit_irq = {
2f2c2679	115	.name = "timer",
77a42796	116	.flags = IRQF_TIMER,
8d80c5ee	117	.handler = pit_tick,
5c4525da GU	118	};
5c4525da GU	119
8d80c5ee GU	120	/***************************************************************************/
8d80c5ee GU	121
a5a1d1c2	122	static u64 pit_read_clk(struct clocksource *cs)
1da177e4	123	{
8d80c5ee GU	124	unsigned long flags;
	125	u32 cycles;
	126	u16 pcntr;
1da177e4	127
8d80c5ee GU	128	local_irq_save(flags);
	129	pcntr = __raw_readw(TA(MCFPIT_PCNTR));
	130	cycles = pit_cnt;
	131	local_irq_restore(flags);
1da177e4	132
2b9a6986	133	return cycles + PIT_CYCLES_PER_JIFFY - pcntr;
8d80c5ee	134	}
1da177e4	135
8d80c5ee	136	/***************************************************************************/
1da177e4	137
8d80c5ee GU	138	static struct clocksource pit_clk = {
8d80c5ee GU	139	.name = "pit",
2b9a6986	140	.rating = 100,
8d80c5ee	141	.read = pit_read_clk,
8d80c5ee	142	.mask = CLOCKSOURCE_MASK(32),
8d80c5ee	143	};
1da177e4 LT	144
	145	/***************************************************************************/
	146
35aefb26	147	void hw_timer_init(irq_handler_t handler)
1da177e4	148	{
320ab2b0	149	cf_pit_clockevent.cpumask = cpumask_of(smp_processor_id());
2b9a6986 SS	150	cf_pit_clockevent.mult = div_sc(FREQ, NSEC_PER_SEC, 32);
	151	cf_pit_clockevent.max_delta_ns =
	152	clockevent_delta2ns(0xFFFF, &cf_pit_clockevent);
33ae7a9b	153	cf_pit_clockevent.max_delta_ticks = 0xFFFF;
2b9a6986 SS	154	cf_pit_clockevent.min_delta_ns =
2b9a6986 SS	155	clockevent_delta2ns(0x3f, &cf_pit_clockevent);
33ae7a9b	156	cf_pit_clockevent.min_delta_ticks = 0x3f;
2b9a6986 SS	157	clockevents_register_device(&cf_pit_clockevent);
2b9a6986 SS	158
bdee4e26	159	setup_irq(MCF_IRQ_PIT1, &pit_irq);
1da177e4	160
010f3f16	161	clocksource_register_hz(&pit_clk, FREQ);
1da177e4 LT	162	}
	163
	164	/***************************************************************************/