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1da177e4 LT |
1 | |
2 | /* include/asm-m68knommu/MC68EZ328.h: 'EZ328 control registers | |
3 | * | |
4 | * Copyright (C) 1999 Vladimir Gurevich <vgurevic@cisco.com> | |
5 | * Bear & Hare Software, Inc. | |
6 | * | |
7 | * Based on include/asm-m68knommu/MC68332.h | |
8 | * Copyright (C) 1998 Kenneth Albanowski <kjahds@kjahds.com>, | |
9 | * The Silver Hammer Group, Ltd. | |
10 | * | |
11 | */ | |
12 | ||
13 | #ifndef _MC68EZ328_H_ | |
14 | #define _MC68EZ328_H_ | |
15 | ||
16 | #define BYTE_REF(addr) (*((volatile unsigned char*)addr)) | |
17 | #define WORD_REF(addr) (*((volatile unsigned short*)addr)) | |
18 | #define LONG_REF(addr) (*((volatile unsigned long*)addr)) | |
19 | ||
20 | #define PUT_FIELD(field, val) (((val) << field##_SHIFT) & field##_MASK) | |
21 | #define GET_FIELD(reg, field) (((reg) & field##_MASK) >> field##_SHIFT) | |
22 | ||
23 | /********** | |
24 | * | |
25 | * 0xFFFFF0xx -- System Control | |
26 | * | |
27 | **********/ | |
28 | ||
29 | /* | |
30 | * System Control Register (SCR) | |
31 | */ | |
32 | #define SCR_ADDR 0xfffff000 | |
33 | #define SCR BYTE_REF(SCR_ADDR) | |
34 | ||
35 | #define SCR_WDTH8 0x01 /* 8-Bit Width Select */ | |
36 | #define SCR_DMAP 0x04 /* Double Map */ | |
37 | #define SCR_SO 0x08 /* Supervisor Only */ | |
38 | #define SCR_BETEN 0x10 /* Bus-Error Time-Out Enable */ | |
39 | #define SCR_PRV 0x20 /* Privilege Violation */ | |
40 | #define SCR_WPV 0x40 /* Write Protect Violation */ | |
41 | #define SCR_BETO 0x80 /* Bus-Error TimeOut */ | |
42 | ||
43 | /* | |
44 | * Silicon ID Register (Mask Revision Register (MRR) for '328 Compatibility) | |
45 | */ | |
46 | #define MRR_ADDR 0xfffff004 | |
47 | #define MRR LONG_REF(MRR_ADDR) | |
48 | ||
49 | /********** | |
50 | * | |
51 | * 0xFFFFF1xx -- Chip-Select logic | |
52 | * | |
53 | **********/ | |
54 | ||
55 | /* | |
56 | * Chip Select Group Base Registers | |
57 | */ | |
58 | #define CSGBA_ADDR 0xfffff100 | |
59 | #define CSGBB_ADDR 0xfffff102 | |
60 | ||
61 | #define CSGBC_ADDR 0xfffff104 | |
62 | #define CSGBD_ADDR 0xfffff106 | |
63 | ||
64 | #define CSGBA WORD_REF(CSGBA_ADDR) | |
65 | #define CSGBB WORD_REF(CSGBB_ADDR) | |
66 | #define CSGBC WORD_REF(CSGBC_ADDR) | |
67 | #define CSGBD WORD_REF(CSGBD_ADDR) | |
68 | ||
69 | /* | |
70 | * Chip Select Registers | |
71 | */ | |
72 | #define CSA_ADDR 0xfffff110 | |
73 | #define CSB_ADDR 0xfffff112 | |
74 | #define CSC_ADDR 0xfffff114 | |
75 | #define CSD_ADDR 0xfffff116 | |
76 | ||
77 | #define CSA WORD_REF(CSA_ADDR) | |
78 | #define CSB WORD_REF(CSB_ADDR) | |
79 | #define CSC WORD_REF(CSC_ADDR) | |
80 | #define CSD WORD_REF(CSD_ADDR) | |
81 | ||
82 | #define CSA_EN 0x0001 /* Chip-Select Enable */ | |
83 | #define CSA_SIZ_MASK 0x000e /* Chip-Select Size */ | |
84 | #define CSA_SIZ_SHIFT 1 | |
85 | #define CSA_WS_MASK 0x0070 /* Wait State */ | |
86 | #define CSA_WS_SHIFT 4 | |
87 | #define CSA_BSW 0x0080 /* Data Bus Width */ | |
88 | #define CSA_FLASH 0x0100 /* FLASH Memory Support */ | |
89 | #define CSA_RO 0x8000 /* Read-Only */ | |
90 | ||
91 | #define CSB_EN 0x0001 /* Chip-Select Enable */ | |
92 | #define CSB_SIZ_MASK 0x000e /* Chip-Select Size */ | |
93 | #define CSB_SIZ_SHIFT 1 | |
94 | #define CSB_WS_MASK 0x0070 /* Wait State */ | |
95 | #define CSB_WS_SHIFT 4 | |
96 | #define CSB_BSW 0x0080 /* Data Bus Width */ | |
97 | #define CSB_FLASH 0x0100 /* FLASH Memory Support */ | |
98 | #define CSB_UPSIZ_MASK 0x1800 /* Unprotected memory block size */ | |
99 | #define CSB_UPSIZ_SHIFT 11 | |
100 | #define CSB_ROP 0x2000 /* Readonly if protected */ | |
101 | #define CSB_SOP 0x4000 /* Supervisor only if protected */ | |
102 | #define CSB_RO 0x8000 /* Read-Only */ | |
103 | ||
104 | #define CSC_EN 0x0001 /* Chip-Select Enable */ | |
105 | #define CSC_SIZ_MASK 0x000e /* Chip-Select Size */ | |
106 | #define CSC_SIZ_SHIFT 1 | |
107 | #define CSC_WS_MASK 0x0070 /* Wait State */ | |
108 | #define CSC_WS_SHIFT 4 | |
109 | #define CSC_BSW 0x0080 /* Data Bus Width */ | |
110 | #define CSC_FLASH 0x0100 /* FLASH Memory Support */ | |
111 | #define CSC_UPSIZ_MASK 0x1800 /* Unprotected memory block size */ | |
112 | #define CSC_UPSIZ_SHIFT 11 | |
113 | #define CSC_ROP 0x2000 /* Readonly if protected */ | |
114 | #define CSC_SOP 0x4000 /* Supervisor only if protected */ | |
115 | #define CSC_RO 0x8000 /* Read-Only */ | |
116 | ||
117 | #define CSD_EN 0x0001 /* Chip-Select Enable */ | |
118 | #define CSD_SIZ_MASK 0x000e /* Chip-Select Size */ | |
119 | #define CSD_SIZ_SHIFT 1 | |
120 | #define CSD_WS_MASK 0x0070 /* Wait State */ | |
121 | #define CSD_WS_SHIFT 4 | |
122 | #define CSD_BSW 0x0080 /* Data Bus Width */ | |
123 | #define CSD_FLASH 0x0100 /* FLASH Memory Support */ | |
124 | #define CSD_DRAM 0x0200 /* Dram Selection */ | |
125 | #define CSD_COMB 0x0400 /* Combining */ | |
126 | #define CSD_UPSIZ_MASK 0x1800 /* Unprotected memory block size */ | |
127 | #define CSD_UPSIZ_SHIFT 11 | |
128 | #define CSD_ROP 0x2000 /* Readonly if protected */ | |
129 | #define CSD_SOP 0x4000 /* Supervisor only if protected */ | |
130 | #define CSD_RO 0x8000 /* Read-Only */ | |
131 | ||
132 | /* | |
133 | * Emulation Chip-Select Register | |
134 | */ | |
135 | #define EMUCS_ADDR 0xfffff118 | |
136 | #define EMUCS WORD_REF(EMUCS_ADDR) | |
137 | ||
138 | #define EMUCS_WS_MASK 0x0070 | |
139 | #define EMUCS_WS_SHIFT 4 | |
140 | ||
141 | /********** | |
142 | * | |
143 | * 0xFFFFF2xx -- Phase Locked Loop (PLL) & Power Control | |
144 | * | |
145 | **********/ | |
146 | ||
147 | /* | |
148 | * PLL Control Register | |
149 | */ | |
150 | #define PLLCR_ADDR 0xfffff200 | |
151 | #define PLLCR WORD_REF(PLLCR_ADDR) | |
152 | ||
153 | #define PLLCR_DISPLL 0x0008 /* Disable PLL */ | |
154 | #define PLLCR_CLKEN 0x0010 /* Clock (CLKO pin) enable */ | |
155 | #define PLLCR_PRESC 0x0020 /* VCO prescaler */ | |
156 | #define PLLCR_SYSCLK_SEL_MASK 0x0700 /* System Clock Selection */ | |
157 | #define PLLCR_SYSCLK_SEL_SHIFT 8 | |
158 | #define PLLCR_LCDCLK_SEL_MASK 0x3800 /* LCD Clock Selection */ | |
159 | #define PLLCR_LCDCLK_SEL_SHIFT 11 | |
160 | ||
161 | /* '328-compatible definitions */ | |
162 | #define PLLCR_PIXCLK_SEL_MASK PLLCR_LCDCLK_SEL_MASK | |
163 | #define PLLCR_PIXCLK_SEL_SHIFT PLLCR_LCDCLK_SEL_SHIFT | |
164 | ||
165 | /* | |
166 | * PLL Frequency Select Register | |
167 | */ | |
168 | #define PLLFSR_ADDR 0xfffff202 | |
169 | #define PLLFSR WORD_REF(PLLFSR_ADDR) | |
170 | ||
171 | #define PLLFSR_PC_MASK 0x00ff /* P Count */ | |
172 | #define PLLFSR_PC_SHIFT 0 | |
173 | #define PLLFSR_QC_MASK 0x0f00 /* Q Count */ | |
174 | #define PLLFSR_QC_SHIFT 8 | |
175 | #define PLLFSR_PROT 0x4000 /* Protect P & Q */ | |
176 | #define PLLFSR_CLK32 0x8000 /* Clock 32 (kHz) */ | |
177 | ||
178 | /* | |
179 | * Power Control Register | |
180 | */ | |
181 | #define PCTRL_ADDR 0xfffff207 | |
182 | #define PCTRL BYTE_REF(PCTRL_ADDR) | |
183 | ||
184 | #define PCTRL_WIDTH_MASK 0x1f /* CPU Clock bursts width */ | |
185 | #define PCTRL_WIDTH_SHIFT 0 | |
186 | #define PCTRL_PCEN 0x80 /* Power Control Enable */ | |
187 | ||
188 | /********** | |
189 | * | |
190 | * 0xFFFFF3xx -- Interrupt Controller | |
191 | * | |
192 | **********/ | |
193 | ||
194 | /* | |
195 | * Interrupt Vector Register | |
196 | */ | |
197 | #define IVR_ADDR 0xfffff300 | |
198 | #define IVR BYTE_REF(IVR_ADDR) | |
199 | ||
200 | #define IVR_VECTOR_MASK 0xF8 | |
201 | ||
202 | /* | |
203 | * Interrupt control Register | |
204 | */ | |
205 | #define ICR_ADDR 0xfffff302 | |
206 | #define ICR WORD_REF(ICR_ADDR) | |
207 | ||
208 | #define ICR_POL5 0x0080 /* Polarity Control for IRQ5 */ | |
209 | #define ICR_ET6 0x0100 /* Edge Trigger Select for IRQ6 */ | |
210 | #define ICR_ET3 0x0200 /* Edge Trigger Select for IRQ3 */ | |
211 | #define ICR_ET2 0x0400 /* Edge Trigger Select for IRQ2 */ | |
212 | #define ICR_ET1 0x0800 /* Edge Trigger Select for IRQ1 */ | |
213 | #define ICR_POL6 0x1000 /* Polarity Control for IRQ6 */ | |
214 | #define ICR_POL3 0x2000 /* Polarity Control for IRQ3 */ | |
215 | #define ICR_POL2 0x4000 /* Polarity Control for IRQ2 */ | |
216 | #define ICR_POL1 0x8000 /* Polarity Control for IRQ1 */ | |
217 | ||
218 | /* | |
219 | * Interrupt Mask Register | |
220 | */ | |
221 | #define IMR_ADDR 0xfffff304 | |
222 | #define IMR LONG_REF(IMR_ADDR) | |
223 | ||
224 | /* | |
225 | * Define the names for bit positions first. This is useful for | |
226 | * request_irq | |
227 | */ | |
228 | #define SPI_IRQ_NUM 0 /* SPI interrupt */ | |
229 | #define TMR_IRQ_NUM 1 /* Timer interrupt */ | |
230 | #define UART_IRQ_NUM 2 /* UART interrupt */ | |
231 | #define WDT_IRQ_NUM 3 /* Watchdog Timer interrupt */ | |
232 | #define RTC_IRQ_NUM 4 /* RTC interrupt */ | |
233 | #define KB_IRQ_NUM 6 /* Keyboard Interrupt */ | |
234 | #define PWM_IRQ_NUM 7 /* Pulse-Width Modulator int. */ | |
235 | #define INT0_IRQ_NUM 8 /* External INT0 */ | |
236 | #define INT1_IRQ_NUM 9 /* External INT1 */ | |
237 | #define INT2_IRQ_NUM 10 /* External INT2 */ | |
238 | #define INT3_IRQ_NUM 11 /* External INT3 */ | |
239 | #define IRQ1_IRQ_NUM 16 /* IRQ1 */ | |
240 | #define IRQ2_IRQ_NUM 17 /* IRQ2 */ | |
241 | #define IRQ3_IRQ_NUM 18 /* IRQ3 */ | |
242 | #define IRQ6_IRQ_NUM 19 /* IRQ6 */ | |
243 | #define IRQ5_IRQ_NUM 20 /* IRQ5 */ | |
244 | #define SAM_IRQ_NUM 22 /* Sampling Timer for RTC */ | |
245 | #define EMIQ_IRQ_NUM 23 /* Emulator Interrupt */ | |
246 | ||
247 | /* '328-compatible definitions */ | |
248 | #define SPIM_IRQ_NUM SPI_IRQ_NUM | |
249 | #define TMR1_IRQ_NUM TMR_IRQ_NUM | |
250 | ||
251 | /* | |
252 | * Here go the bitmasks themselves | |
253 | */ | |
254 | #define IMR_MSPI (1 << SPI_IRQ_NUM) /* Mask SPI interrupt */ | |
255 | #define IMR_MTMR (1 << TMR_IRQ_NUM) /* Mask Timer interrupt */ | |
256 | #define IMR_MUART (1 << UART_IRQ_NUM) /* Mask UART interrupt */ | |
257 | #define IMR_MWDT (1 << WDT_IRQ_NUM) /* Mask Watchdog Timer interrupt */ | |
258 | #define IMR_MRTC (1 << RTC_IRQ_NUM) /* Mask RTC interrupt */ | |
259 | #define IMR_MKB (1 << KB_IRQ_NUM) /* Mask Keyboard Interrupt */ | |
260 | #define IMR_MPWM (1 << PWM_IRQ_NUM) /* Mask Pulse-Width Modulator int. */ | |
261 | #define IMR_MINT0 (1 << INT0_IRQ_NUM) /* Mask External INT0 */ | |
262 | #define IMR_MINT1 (1 << INT1_IRQ_NUM) /* Mask External INT1 */ | |
263 | #define IMR_MINT2 (1 << INT2_IRQ_NUM) /* Mask External INT2 */ | |
264 | #define IMR_MINT3 (1 << INT3_IRQ_NUM) /* Mask External INT3 */ | |
265 | #define IMR_MIRQ1 (1 << IRQ1_IRQ_NUM) /* Mask IRQ1 */ | |
266 | #define IMR_MIRQ2 (1 << IRQ2_IRQ_NUM) /* Mask IRQ2 */ | |
267 | #define IMR_MIRQ3 (1 << IRQ3_IRQ_NUM) /* Mask IRQ3 */ | |
268 | #define IMR_MIRQ6 (1 << IRQ6_IRQ_NUM) /* Mask IRQ6 */ | |
269 | #define IMR_MIRQ5 (1 << IRQ5_IRQ_NUM) /* Mask IRQ5 */ | |
270 | #define IMR_MSAM (1 << SAM_IRQ_NUM) /* Mask Sampling Timer for RTC */ | |
271 | #define IMR_MEMIQ (1 << EMIQ_IRQ_NUM) /* Mask Emulator Interrupt */ | |
272 | ||
273 | /* '328-compatible definitions */ | |
274 | #define IMR_MSPIM IMR_MSPI | |
275 | #define IMR_MTMR1 IMR_MTMR | |
276 | ||
277 | /* | |
278 | * Interrupt Status Register | |
279 | */ | |
280 | #define ISR_ADDR 0xfffff30c | |
281 | #define ISR LONG_REF(ISR_ADDR) | |
282 | ||
283 | #define ISR_SPI (1 << SPI_IRQ_NUM) /* SPI interrupt */ | |
284 | #define ISR_TMR (1 << TMR_IRQ_NUM) /* Timer interrupt */ | |
285 | #define ISR_UART (1 << UART_IRQ_NUM) /* UART interrupt */ | |
286 | #define ISR_WDT (1 << WDT_IRQ_NUM) /* Watchdog Timer interrupt */ | |
287 | #define ISR_RTC (1 << RTC_IRQ_NUM) /* RTC interrupt */ | |
288 | #define ISR_KB (1 << KB_IRQ_NUM) /* Keyboard Interrupt */ | |
289 | #define ISR_PWM (1 << PWM_IRQ_NUM) /* Pulse-Width Modulator interrupt */ | |
290 | #define ISR_INT0 (1 << INT0_IRQ_NUM) /* External INT0 */ | |
291 | #define ISR_INT1 (1 << INT1_IRQ_NUM) /* External INT1 */ | |
292 | #define ISR_INT2 (1 << INT2_IRQ_NUM) /* External INT2 */ | |
293 | #define ISR_INT3 (1 << INT3_IRQ_NUM) /* External INT3 */ | |
294 | #define ISR_IRQ1 (1 << IRQ1_IRQ_NUM) /* IRQ1 */ | |
295 | #define ISR_IRQ2 (1 << IRQ2_IRQ_NUM) /* IRQ2 */ | |
296 | #define ISR_IRQ3 (1 << IRQ3_IRQ_NUM) /* IRQ3 */ | |
297 | #define ISR_IRQ6 (1 << IRQ6_IRQ_NUM) /* IRQ6 */ | |
298 | #define ISR_IRQ5 (1 << IRQ5_IRQ_NUM) /* IRQ5 */ | |
299 | #define ISR_SAM (1 << SAM_IRQ_NUM) /* Sampling Timer for RTC */ | |
300 | #define ISR_EMIQ (1 << EMIQ_IRQ_NUM) /* Emulator Interrupt */ | |
301 | ||
302 | /* '328-compatible definitions */ | |
303 | #define ISR_SPIM ISR_SPI | |
304 | #define ISR_TMR1 ISR_TMR | |
305 | ||
306 | /* | |
307 | * Interrupt Pending Register | |
308 | */ | |
309 | #define IPR_ADDR 0xfffff30c | |
310 | #define IPR LONG_REF(IPR_ADDR) | |
311 | ||
312 | #define IPR_SPI (1 << SPI_IRQ_NUM) /* SPI interrupt */ | |
313 | #define IPR_TMR (1 << TMR_IRQ_NUM) /* Timer interrupt */ | |
314 | #define IPR_UART (1 << UART_IRQ_NUM) /* UART interrupt */ | |
315 | #define IPR_WDT (1 << WDT_IRQ_NUM) /* Watchdog Timer interrupt */ | |
316 | #define IPR_RTC (1 << RTC_IRQ_NUM) /* RTC interrupt */ | |
317 | #define IPR_KB (1 << KB_IRQ_NUM) /* Keyboard Interrupt */ | |
318 | #define IPR_PWM (1 << PWM_IRQ_NUM) /* Pulse-Width Modulator interrupt */ | |
319 | #define IPR_INT0 (1 << INT0_IRQ_NUM) /* External INT0 */ | |
320 | #define IPR_INT1 (1 << INT1_IRQ_NUM) /* External INT1 */ | |
321 | #define IPR_INT2 (1 << INT2_IRQ_NUM) /* External INT2 */ | |
322 | #define IPR_INT3 (1 << INT3_IRQ_NUM) /* External INT3 */ | |
323 | #define IPR_IRQ1 (1 << IRQ1_IRQ_NUM) /* IRQ1 */ | |
324 | #define IPR_IRQ2 (1 << IRQ2_IRQ_NUM) /* IRQ2 */ | |
325 | #define IPR_IRQ3 (1 << IRQ3_IRQ_NUM) /* IRQ3 */ | |
326 | #define IPR_IRQ6 (1 << IRQ6_IRQ_NUM) /* IRQ6 */ | |
327 | #define IPR_IRQ5 (1 << IRQ5_IRQ_NUM) /* IRQ5 */ | |
328 | #define IPR_SAM (1 << SAM_IRQ_NUM) /* Sampling Timer for RTC */ | |
329 | #define IPR_EMIQ (1 << EMIQ_IRQ_NUM) /* Emulator Interrupt */ | |
330 | ||
331 | /* '328-compatible definitions */ | |
332 | #define IPR_SPIM IPR_SPI | |
333 | #define IPR_TMR1 IPR_TMR | |
334 | ||
335 | /********** | |
336 | * | |
337 | * 0xFFFFF4xx -- Parallel Ports | |
338 | * | |
339 | **********/ | |
340 | ||
341 | /* | |
342 | * Port A | |
343 | */ | |
344 | #define PADIR_ADDR 0xfffff400 /* Port A direction reg */ | |
345 | #define PADATA_ADDR 0xfffff401 /* Port A data register */ | |
346 | #define PAPUEN_ADDR 0xfffff402 /* Port A Pull-Up enable reg */ | |
347 | ||
348 | #define PADIR BYTE_REF(PADIR_ADDR) | |
349 | #define PADATA BYTE_REF(PADATA_ADDR) | |
350 | #define PAPUEN BYTE_REF(PAPUEN_ADDR) | |
351 | ||
352 | #define PA(x) (1 << (x)) | |
353 | ||
354 | /* | |
355 | * Port B | |
356 | */ | |
357 | #define PBDIR_ADDR 0xfffff408 /* Port B direction reg */ | |
358 | #define PBDATA_ADDR 0xfffff409 /* Port B data register */ | |
359 | #define PBPUEN_ADDR 0xfffff40a /* Port B Pull-Up enable reg */ | |
360 | #define PBSEL_ADDR 0xfffff40b /* Port B Select Register */ | |
361 | ||
362 | #define PBDIR BYTE_REF(PBDIR_ADDR) | |
363 | #define PBDATA BYTE_REF(PBDATA_ADDR) | |
364 | #define PBPUEN BYTE_REF(PBPUEN_ADDR) | |
365 | #define PBSEL BYTE_REF(PBSEL_ADDR) | |
366 | ||
367 | #define PB(x) (1 << (x)) | |
368 | ||
369 | #define PB_CSB0 0x01 /* Use CSB0 as PB[0] */ | |
370 | #define PB_CSB1 0x02 /* Use CSB1 as PB[1] */ | |
371 | #define PB_CSC0_RAS0 0x04 /* Use CSC0/RAS0 as PB[2] */ | |
372 | #define PB_CSC1_RAS1 0x08 /* Use CSC1/RAS1 as PB[3] */ | |
373 | #define PB_CSD0_CAS0 0x10 /* Use CSD0/CAS0 as PB[4] */ | |
374 | #define PB_CSD1_CAS1 0x20 /* Use CSD1/CAS1 as PB[5] */ | |
375 | #define PB_TIN_TOUT 0x40 /* Use TIN/TOUT as PB[6] */ | |
376 | #define PB_PWMO 0x80 /* Use PWMO as PB[7] */ | |
377 | ||
378 | /* | |
379 | * Port C | |
380 | */ | |
381 | #define PCDIR_ADDR 0xfffff410 /* Port C direction reg */ | |
382 | #define PCDATA_ADDR 0xfffff411 /* Port C data register */ | |
383 | #define PCPDEN_ADDR 0xfffff412 /* Port C Pull-Down enb. reg */ | |
384 | #define PCSEL_ADDR 0xfffff413 /* Port C Select Register */ | |
385 | ||
386 | #define PCDIR BYTE_REF(PCDIR_ADDR) | |
387 | #define PCDATA BYTE_REF(PCDATA_ADDR) | |
388 | #define PCPDEN BYTE_REF(PCPDEN_ADDR) | |
389 | #define PCSEL BYTE_REF(PCSEL_ADDR) | |
390 | ||
391 | #define PC(x) (1 << (x)) | |
392 | ||
393 | #define PC_LD0 0x01 /* Use LD0 as PC[0] */ | |
394 | #define PC_LD1 0x02 /* Use LD1 as PC[1] */ | |
395 | #define PC_LD2 0x04 /* Use LD2 as PC[2] */ | |
396 | #define PC_LD3 0x08 /* Use LD3 as PC[3] */ | |
397 | #define PC_LFLM 0x10 /* Use LFLM as PC[4] */ | |
398 | #define PC_LLP 0x20 /* Use LLP as PC[5] */ | |
399 | #define PC_LCLK 0x40 /* Use LCLK as PC[6] */ | |
400 | #define PC_LACD 0x80 /* Use LACD as PC[7] */ | |
401 | ||
402 | /* | |
403 | * Port D | |
404 | */ | |
405 | #define PDDIR_ADDR 0xfffff418 /* Port D direction reg */ | |
406 | #define PDDATA_ADDR 0xfffff419 /* Port D data register */ | |
407 | #define PDPUEN_ADDR 0xfffff41a /* Port D Pull-Up enable reg */ | |
408 | #define PDSEL_ADDR 0xfffff41b /* Port D Select Register */ | |
409 | #define PDPOL_ADDR 0xfffff41c /* Port D Polarity Register */ | |
410 | #define PDIRQEN_ADDR 0xfffff41d /* Port D IRQ enable register */ | |
411 | #define PDKBEN_ADDR 0xfffff41e /* Port D Keyboard Enable reg */ | |
412 | #define PDIQEG_ADDR 0xfffff41f /* Port D IRQ Edge Register */ | |
413 | ||
414 | #define PDDIR BYTE_REF(PDDIR_ADDR) | |
415 | #define PDDATA BYTE_REF(PDDATA_ADDR) | |
416 | #define PDPUEN BYTE_REF(PDPUEN_ADDR) | |
417 | #define PDSEL BYTE_REF(PDSEL_ADDR) | |
418 | #define PDPOL BYTE_REF(PDPOL_ADDR) | |
419 | #define PDIRQEN BYTE_REF(PDIRQEN_ADDR) | |
420 | #define PDKBEN BYTE_REF(PDKBEN_ADDR) | |
421 | #define PDIQEG BYTE_REF(PDIQEG_ADDR) | |
422 | ||
423 | #define PD(x) (1 << (x)) | |
424 | ||
425 | #define PD_INT0 0x01 /* Use INT0 as PD[0] */ | |
426 | #define PD_INT1 0x02 /* Use INT1 as PD[1] */ | |
427 | #define PD_INT2 0x04 /* Use INT2 as PD[2] */ | |
428 | #define PD_INT3 0x08 /* Use INT3 as PD[3] */ | |
429 | #define PD_IRQ1 0x10 /* Use IRQ1 as PD[4] */ | |
430 | #define PD_IRQ2 0x20 /* Use IRQ2 as PD[5] */ | |
431 | #define PD_IRQ3 0x40 /* Use IRQ3 as PD[6] */ | |
432 | #define PD_IRQ6 0x80 /* Use IRQ6 as PD[7] */ | |
433 | ||
434 | /* | |
435 | * Port E | |
436 | */ | |
437 | #define PEDIR_ADDR 0xfffff420 /* Port E direction reg */ | |
438 | #define PEDATA_ADDR 0xfffff421 /* Port E data register */ | |
439 | #define PEPUEN_ADDR 0xfffff422 /* Port E Pull-Up enable reg */ | |
440 | #define PESEL_ADDR 0xfffff423 /* Port E Select Register */ | |
441 | ||
442 | #define PEDIR BYTE_REF(PEDIR_ADDR) | |
443 | #define PEDATA BYTE_REF(PEDATA_ADDR) | |
444 | #define PEPUEN BYTE_REF(PEPUEN_ADDR) | |
445 | #define PESEL BYTE_REF(PESEL_ADDR) | |
446 | ||
447 | #define PE(x) (1 << (x)) | |
448 | ||
449 | #define PE_SPMTXD 0x01 /* Use SPMTXD as PE[0] */ | |
450 | #define PE_SPMRXD 0x02 /* Use SPMRXD as PE[1] */ | |
451 | #define PE_SPMCLK 0x04 /* Use SPMCLK as PE[2] */ | |
452 | #define PE_DWE 0x08 /* Use DWE as PE[3] */ | |
453 | #define PE_RXD 0x10 /* Use RXD as PE[4] */ | |
454 | #define PE_TXD 0x20 /* Use TXD as PE[5] */ | |
455 | #define PE_RTS 0x40 /* Use RTS as PE[6] */ | |
456 | #define PE_CTS 0x80 /* Use CTS as PE[7] */ | |
457 | ||
458 | /* | |
459 | * Port F | |
460 | */ | |
461 | #define PFDIR_ADDR 0xfffff428 /* Port F direction reg */ | |
462 | #define PFDATA_ADDR 0xfffff429 /* Port F data register */ | |
463 | #define PFPUEN_ADDR 0xfffff42a /* Port F Pull-Up enable reg */ | |
464 | #define PFSEL_ADDR 0xfffff42b /* Port F Select Register */ | |
465 | ||
466 | #define PFDIR BYTE_REF(PFDIR_ADDR) | |
467 | #define PFDATA BYTE_REF(PFDATA_ADDR) | |
468 | #define PFPUEN BYTE_REF(PFPUEN_ADDR) | |
469 | #define PFSEL BYTE_REF(PFSEL_ADDR) | |
470 | ||
471 | #define PF(x) (1 << (x)) | |
472 | ||
473 | #define PF_LCONTRAST 0x01 /* Use LCONTRAST as PF[0] */ | |
474 | #define PF_IRQ5 0x02 /* Use IRQ5 as PF[1] */ | |
475 | #define PF_CLKO 0x04 /* Use CLKO as PF[2] */ | |
476 | #define PF_A20 0x08 /* Use A20 as PF[3] */ | |
477 | #define PF_A21 0x10 /* Use A21 as PF[4] */ | |
478 | #define PF_A22 0x20 /* Use A22 as PF[5] */ | |
479 | #define PF_A23 0x40 /* Use A23 as PF[6] */ | |
480 | #define PF_CSA1 0x80 /* Use CSA1 as PF[7] */ | |
481 | ||
482 | /* | |
483 | * Port G | |
484 | */ | |
485 | #define PGDIR_ADDR 0xfffff430 /* Port G direction reg */ | |
486 | #define PGDATA_ADDR 0xfffff431 /* Port G data register */ | |
487 | #define PGPUEN_ADDR 0xfffff432 /* Port G Pull-Up enable reg */ | |
488 | #define PGSEL_ADDR 0xfffff433 /* Port G Select Register */ | |
489 | ||
490 | #define PGDIR BYTE_REF(PGDIR_ADDR) | |
491 | #define PGDATA BYTE_REF(PGDATA_ADDR) | |
492 | #define PGPUEN BYTE_REF(PGPUEN_ADDR) | |
493 | #define PGSEL BYTE_REF(PGSEL_ADDR) | |
494 | ||
495 | #define PG(x) (1 << (x)) | |
496 | ||
497 | #define PG_BUSW_DTACK 0x01 /* Use BUSW/DTACK as PG[0] */ | |
498 | #define PG_A0 0x02 /* Use A0 as PG[1] */ | |
499 | #define PG_EMUIRQ 0x04 /* Use EMUIRQ as PG[2] */ | |
500 | #define PG_HIZ_P_D 0x08 /* Use HIZ/P/D as PG[3] */ | |
501 | #define PG_EMUCS 0x10 /* Use EMUCS as PG[4] */ | |
502 | #define PG_EMUBRK 0x20 /* Use EMUBRK as PG[5] */ | |
503 | ||
504 | /********** | |
505 | * | |
506 | * 0xFFFFF5xx -- Pulse-Width Modulator (PWM) | |
507 | * | |
508 | **********/ | |
509 | ||
510 | /* | |
511 | * PWM Control Register | |
512 | */ | |
513 | #define PWMC_ADDR 0xfffff500 | |
514 | #define PWMC WORD_REF(PWMC_ADDR) | |
515 | ||
516 | #define PWMC_CLKSEL_MASK 0x0003 /* Clock Selection */ | |
517 | #define PWMC_CLKSEL_SHIFT 0 | |
518 | #define PWMC_REPEAT_MASK 0x000c /* Sample Repeats */ | |
519 | #define PWMC_REPEAT_SHIFT 2 | |
520 | #define PWMC_EN 0x0010 /* Enable PWM */ | |
521 | #define PMNC_FIFOAV 0x0020 /* FIFO Available */ | |
522 | #define PWMC_IRQEN 0x0040 /* Interrupt Request Enable */ | |
523 | #define PWMC_IRQ 0x0080 /* Interrupt Request (FIFO empty) */ | |
524 | #define PWMC_PRESCALER_MASK 0x7f00 /* Incoming Clock prescaler */ | |
525 | #define PWMC_PRESCALER_SHIFT 8 | |
526 | #define PWMC_CLKSRC 0x8000 /* Clock Source Select */ | |
527 | ||
528 | /* '328-compatible definitions */ | |
529 | #define PWMC_PWMEN PWMC_EN | |
530 | ||
531 | /* | |
532 | * PWM Sample Register | |
533 | */ | |
534 | #define PWMS_ADDR 0xfffff502 | |
535 | #define PWMS WORD_REF(PWMS_ADDR) | |
536 | ||
537 | /* | |
538 | * PWM Period Register | |
539 | */ | |
540 | #define PWMP_ADDR 0xfffff504 | |
541 | #define PWMP BYTE_REF(PWMP_ADDR) | |
542 | ||
543 | /* | |
544 | * PWM Counter Register | |
545 | */ | |
546 | #define PWMCNT_ADDR 0xfffff505 | |
547 | #define PWMCNT BYTE_REF(PWMCNT_ADDR) | |
548 | ||
549 | /********** | |
550 | * | |
551 | * 0xFFFFF6xx -- General-Purpose Timer | |
552 | * | |
553 | **********/ | |
554 | ||
555 | /* | |
556 | * Timer Control register | |
557 | */ | |
558 | #define TCTL_ADDR 0xfffff600 | |
559 | #define TCTL WORD_REF(TCTL_ADDR) | |
560 | ||
561 | #define TCTL_TEN 0x0001 /* Timer Enable */ | |
562 | #define TCTL_CLKSOURCE_MASK 0x000e /* Clock Source: */ | |
563 | #define TCTL_CLKSOURCE_STOP 0x0000 /* Stop count (disabled) */ | |
564 | #define TCTL_CLKSOURCE_SYSCLK 0x0002 /* SYSCLK to prescaler */ | |
565 | #define TCTL_CLKSOURCE_SYSCLK_16 0x0004 /* SYSCLK/16 to prescaler */ | |
566 | #define TCTL_CLKSOURCE_TIN 0x0006 /* TIN to prescaler */ | |
567 | #define TCTL_CLKSOURCE_32KHZ 0x0008 /* 32kHz clock to prescaler */ | |
568 | #define TCTL_IRQEN 0x0010 /* IRQ Enable */ | |
569 | #define TCTL_OM 0x0020 /* Output Mode */ | |
570 | #define TCTL_CAP_MASK 0x00c0 /* Capture Edge: */ | |
571 | #define TCTL_CAP_RE 0x0040 /* Capture on rizing edge */ | |
572 | #define TCTL_CAP_FE 0x0080 /* Capture on falling edge */ | |
573 | #define TCTL_FRR 0x0010 /* Free-Run Mode */ | |
574 | ||
575 | /* '328-compatible definitions */ | |
576 | #define TCTL1_ADDR TCTL_ADDR | |
577 | #define TCTL1 TCTL | |
578 | ||
579 | /* | |
580 | * Timer Prescaler Register | |
581 | */ | |
582 | #define TPRER_ADDR 0xfffff602 | |
583 | #define TPRER WORD_REF(TPRER_ADDR) | |
584 | ||
585 | /* '328-compatible definitions */ | |
586 | #define TPRER1_ADDR TPRER_ADDR | |
587 | #define TPRER1 TPRER | |
588 | ||
589 | /* | |
590 | * Timer Compare Register | |
591 | */ | |
592 | #define TCMP_ADDR 0xfffff604 | |
593 | #define TCMP WORD_REF(TCMP_ADDR) | |
594 | ||
595 | /* '328-compatible definitions */ | |
596 | #define TCMP1_ADDR TCMP_ADDR | |
597 | #define TCMP1 TCMP | |
598 | ||
599 | /* | |
600 | * Timer Capture register | |
601 | */ | |
602 | #define TCR_ADDR 0xfffff606 | |
603 | #define TCR WORD_REF(TCR_ADDR) | |
604 | ||
605 | /* '328-compatible definitions */ | |
606 | #define TCR1_ADDR TCR_ADDR | |
607 | #define TCR1 TCR | |
608 | ||
609 | /* | |
610 | * Timer Counter Register | |
611 | */ | |
612 | #define TCN_ADDR 0xfffff608 | |
613 | #define TCN WORD_REF(TCN_ADDR) | |
614 | ||
615 | /* '328-compatible definitions */ | |
616 | #define TCN1_ADDR TCN_ADDR | |
617 | #define TCN1 TCN | |
618 | ||
619 | /* | |
620 | * Timer Status Register | |
621 | */ | |
622 | #define TSTAT_ADDR 0xfffff60a | |
623 | #define TSTAT WORD_REF(TSTAT_ADDR) | |
624 | ||
625 | #define TSTAT_COMP 0x0001 /* Compare Event occurred */ | |
626 | #define TSTAT_CAPT 0x0001 /* Capture Event occurred */ | |
627 | ||
628 | /* '328-compatible definitions */ | |
629 | #define TSTAT1_ADDR TSTAT_ADDR | |
630 | #define TSTAT1 TSTAT | |
631 | ||
632 | /********** | |
633 | * | |
634 | * 0xFFFFF8xx -- Serial Periferial Interface Master (SPIM) | |
635 | * | |
636 | **********/ | |
637 | ||
638 | /* | |
639 | * SPIM Data Register | |
640 | */ | |
641 | #define SPIMDATA_ADDR 0xfffff800 | |
642 | #define SPIMDATA WORD_REF(SPIMDATA_ADDR) | |
643 | ||
644 | /* | |
645 | * SPIM Control/Status Register | |
646 | */ | |
647 | #define SPIMCONT_ADDR 0xfffff802 | |
648 | #define SPIMCONT WORD_REF(SPIMCONT_ADDR) | |
649 | ||
650 | #define SPIMCONT_BIT_COUNT_MASK 0x000f /* Transfer Length in Bytes */ | |
651 | #define SPIMCONT_BIT_COUNT_SHIFT 0 | |
652 | #define SPIMCONT_POL 0x0010 /* SPMCLK Signel Polarity */ | |
653 | #define SPIMCONT_PHA 0x0020 /* Clock/Data phase relationship */ | |
654 | #define SPIMCONT_IRQEN 0x0040 /* IRQ Enable */ | |
655 | #define SPIMCONT_IRQ 0x0080 /* Interrupt Request */ | |
656 | #define SPIMCONT_XCH 0x0100 /* Exchange */ | |
657 | #define SPIMCONT_ENABLE 0x0200 /* Enable SPIM */ | |
658 | #define SPIMCONT_DATA_RATE_MASK 0xe000 /* SPIM Data Rate */ | |
659 | #define SPIMCONT_DATA_RATE_SHIFT 13 | |
660 | ||
661 | /* '328-compatible definitions */ | |
662 | #define SPIMCONT_SPIMIRQ SPIMCONT_IRQ | |
663 | #define SPIMCONT_SPIMEN SPIMCONT_ENABLE | |
664 | ||
665 | /********** | |
666 | * | |
667 | * 0xFFFFF9xx -- UART | |
668 | * | |
669 | **********/ | |
670 | ||
671 | /* | |
672 | * UART Status/Control Register | |
673 | */ | |
674 | #define USTCNT_ADDR 0xfffff900 | |
675 | #define USTCNT WORD_REF(USTCNT_ADDR) | |
676 | ||
677 | #define USTCNT_TXAE 0x0001 /* Transmitter Available Interrupt Enable */ | |
678 | #define USTCNT_TXHE 0x0002 /* Transmitter Half Empty Enable */ | |
679 | #define USTCNT_TXEE 0x0004 /* Transmitter Empty Interrupt Enable */ | |
680 | #define USTCNT_RXRE 0x0008 /* Receiver Ready Interrupt Enable */ | |
681 | #define USTCNT_RXHE 0x0010 /* Receiver Half-Full Interrupt Enable */ | |
682 | #define USTCNT_RXFE 0x0020 /* Receiver Full Interrupt Enable */ | |
683 | #define USTCNT_CTSD 0x0040 /* CTS Delta Interrupt Enable */ | |
684 | #define USTCNT_ODEN 0x0080 /* Old Data Interrupt Enable */ | |
685 | #define USTCNT_8_7 0x0100 /* Eight or seven-bit transmission */ | |
686 | #define USTCNT_STOP 0x0200 /* Stop bit transmission */ | |
687 | #define USTCNT_ODD 0x0400 /* Odd Parity */ | |
688 | #define USTCNT_PEN 0x0800 /* Parity Enable */ | |
689 | #define USTCNT_CLKM 0x1000 /* Clock Mode Select */ | |
690 | #define USTCNT_TXEN 0x2000 /* Transmitter Enable */ | |
691 | #define USTCNT_RXEN 0x4000 /* Receiver Enable */ | |
692 | #define USTCNT_UEN 0x8000 /* UART Enable */ | |
693 | ||
694 | /* '328-compatible definitions */ | |
695 | #define USTCNT_TXAVAILEN USTCNT_TXAE | |
696 | #define USTCNT_TXHALFEN USTCNT_TXHE | |
697 | #define USTCNT_TXEMPTYEN USTCNT_TXEE | |
698 | #define USTCNT_RXREADYEN USTCNT_RXRE | |
699 | #define USTCNT_RXHALFEN USTCNT_RXHE | |
700 | #define USTCNT_RXFULLEN USTCNT_RXFE | |
701 | #define USTCNT_CTSDELTAEN USTCNT_CTSD | |
702 | #define USTCNT_ODD_EVEN USTCNT_ODD | |
703 | #define USTCNT_PARITYEN USTCNT_PEN | |
704 | #define USTCNT_CLKMODE USTCNT_CLKM | |
705 | #define USTCNT_UARTEN USTCNT_UEN | |
706 | ||
707 | /* | |
708 | * UART Baud Control Register | |
709 | */ | |
710 | #define UBAUD_ADDR 0xfffff902 | |
711 | #define UBAUD WORD_REF(UBAUD_ADDR) | |
712 | ||
713 | #define UBAUD_PRESCALER_MASK 0x003f /* Actual divisor is 65 - PRESCALER */ | |
714 | #define UBAUD_PRESCALER_SHIFT 0 | |
715 | #define UBAUD_DIVIDE_MASK 0x0700 /* Baud Rate freq. divizor */ | |
716 | #define UBAUD_DIVIDE_SHIFT 8 | |
717 | #define UBAUD_BAUD_SRC 0x0800 /* Baud Rate Source */ | |
718 | #define UBAUD_UCLKDIR 0x2000 /* UCLK Direction */ | |
719 | ||
720 | /* | |
721 | * UART Receiver Register | |
722 | */ | |
723 | #define URX_ADDR 0xfffff904 | |
724 | #define URX WORD_REF(URX_ADDR) | |
725 | ||
726 | #define URX_RXDATA_ADDR 0xfffff905 | |
727 | #define URX_RXDATA BYTE_REF(URX_RXDATA_ADDR) | |
728 | ||
729 | #define URX_RXDATA_MASK 0x00ff /* Received data */ | |
730 | #define URX_RXDATA_SHIFT 0 | |
731 | #define URX_PARITY_ERROR 0x0100 /* Parity Error */ | |
732 | #define URX_BREAK 0x0200 /* Break Detected */ | |
733 | #define URX_FRAME_ERROR 0x0400 /* Framing Error */ | |
734 | #define URX_OVRUN 0x0800 /* Serial Overrun */ | |
735 | #define URX_OLD_DATA 0x1000 /* Old data in FIFO */ | |
736 | #define URX_DATA_READY 0x2000 /* Data Ready (FIFO not empty) */ | |
737 | #define URX_FIFO_HALF 0x4000 /* FIFO is Half-Full */ | |
738 | #define URX_FIFO_FULL 0x8000 /* FIFO is Full */ | |
739 | ||
740 | /* | |
741 | * UART Transmitter Register | |
742 | */ | |
743 | #define UTX_ADDR 0xfffff906 | |
744 | #define UTX WORD_REF(UTX_ADDR) | |
745 | ||
746 | #define UTX_TXDATA_ADDR 0xfffff907 | |
747 | #define UTX_TXDATA BYTE_REF(UTX_TXDATA_ADDR) | |
748 | ||
749 | #define UTX_TXDATA_MASK 0x00ff /* Data to be transmitted */ | |
750 | #define UTX_TXDATA_SHIFT 0 | |
751 | #define UTX_CTS_DELTA 0x0100 /* CTS changed */ | |
752 | #define UTX_CTS_STAT 0x0200 /* CTS State */ | |
753 | #define UTX_BUSY 0x0400 /* FIFO is busy, sending a character */ | |
754 | #define UTX_NOCTS 0x0800 /* Ignore CTS */ | |
755 | #define UTX_SEND_BREAK 0x1000 /* Send a BREAK */ | |
756 | #define UTX_TX_AVAIL 0x2000 /* Transmit FIFO has a slot available */ | |
757 | #define UTX_FIFO_HALF 0x4000 /* Transmit FIFO is half empty */ | |
758 | #define UTX_FIFO_EMPTY 0x8000 /* Transmit FIFO is empty */ | |
759 | ||
760 | /* '328-compatible definitions */ | |
761 | #define UTX_CTS_STATUS UTX_CTS_STAT | |
762 | #define UTX_IGNORE_CTS UTX_NOCTS | |
763 | ||
764 | /* | |
765 | * UART Miscellaneous Register | |
766 | */ | |
767 | #define UMISC_ADDR 0xfffff908 | |
768 | #define UMISC WORD_REF(UMISC_ADDR) | |
769 | ||
770 | #define UMISC_TX_POL 0x0004 /* Transmit Polarity */ | |
771 | #define UMISC_RX_POL 0x0008 /* Receive Polarity */ | |
772 | #define UMISC_IRDA_LOOP 0x0010 /* IrDA Loopback Enable */ | |
773 | #define UMISC_IRDA_EN 0x0020 /* Infra-Red Enable */ | |
774 | #define UMISC_RTS 0x0040 /* Set RTS status */ | |
775 | #define UMISC_RTSCONT 0x0080 /* Choose RTS control */ | |
776 | #define UMISC_IR_TEST 0x0400 /* IRDA Test Enable */ | |
777 | #define UMISC_BAUD_RESET 0x0800 /* Reset Baud Rate Generation Counters */ | |
778 | #define UMISC_LOOP 0x1000 /* Serial Loopback Enable */ | |
779 | #define UMISC_FORCE_PERR 0x2000 /* Force Parity Error */ | |
780 | #define UMISC_CLKSRC 0x4000 /* Clock Source */ | |
781 | #define UMISC_BAUD_TEST 0x8000 /* Enable Baud Test Mode */ | |
782 | ||
783 | /* | |
784 | * UART Non-integer Prescaler Register | |
785 | */ | |
786 | #define NIPR_ADDR 0xfffff90a | |
787 | #define NIPR WORD_REF(NIPR_ADDR) | |
788 | ||
789 | #define NIPR_STEP_VALUE_MASK 0x00ff /* NI prescaler step value */ | |
790 | #define NIPR_STEP_VALUE_SHIFT 0 | |
791 | #define NIPR_SELECT_MASK 0x0700 /* Tap Selection */ | |
792 | #define NIPR_SELECT_SHIFT 8 | |
793 | #define NIPR_PRE_SEL 0x8000 /* Non-integer prescaler select */ | |
794 | ||
795 | ||
796 | /* generalization of uart control registers to support multiple ports: */ | |
797 | typedef volatile struct { | |
798 | volatile unsigned short int ustcnt; | |
799 | volatile unsigned short int ubaud; | |
800 | union { | |
801 | volatile unsigned short int w; | |
802 | struct { | |
803 | volatile unsigned char status; | |
804 | volatile unsigned char rxdata; | |
805 | } b; | |
806 | } urx; | |
807 | union { | |
808 | volatile unsigned short int w; | |
809 | struct { | |
810 | volatile unsigned char status; | |
811 | volatile unsigned char txdata; | |
812 | } b; | |
813 | } utx; | |
814 | volatile unsigned short int umisc; | |
815 | volatile unsigned short int nipr; | |
816 | volatile unsigned short int pad1; | |
817 | volatile unsigned short int pad2; | |
f78fc874 | 818 | } __attribute__((packed)) m68328_uart; |
1da177e4 LT |
819 | |
820 | ||
821 | /********** | |
822 | * | |
823 | * 0xFFFFFAxx -- LCD Controller | |
824 | * | |
825 | **********/ | |
826 | ||
827 | /* | |
828 | * LCD Screen Starting Address Register | |
829 | */ | |
830 | #define LSSA_ADDR 0xfffffa00 | |
831 | #define LSSA LONG_REF(LSSA_ADDR) | |
832 | ||
833 | #define LSSA_SSA_MASK 0x1ffffffe /* Bits 0 and 29-31 are reserved */ | |
834 | ||
835 | /* | |
836 | * LCD Virtual Page Width Register | |
837 | */ | |
838 | #define LVPW_ADDR 0xfffffa05 | |
839 | #define LVPW BYTE_REF(LVPW_ADDR) | |
840 | ||
841 | /* | |
842 | * LCD Screen Width Register (not compatible with '328 !!!) | |
843 | */ | |
844 | #define LXMAX_ADDR 0xfffffa08 | |
845 | #define LXMAX WORD_REF(LXMAX_ADDR) | |
846 | ||
847 | #define LXMAX_XM_MASK 0x02f0 /* Bits 0-3 and 10-15 are reserved */ | |
848 | ||
849 | /* | |
850 | * LCD Screen Height Register | |
851 | */ | |
852 | #define LYMAX_ADDR 0xfffffa0a | |
853 | #define LYMAX WORD_REF(LYMAX_ADDR) | |
854 | ||
855 | #define LYMAX_YM_MASK 0x01ff /* Bits 9-15 are reserved */ | |
856 | ||
857 | /* | |
858 | * LCD Cursor X Position Register | |
859 | */ | |
860 | #define LCXP_ADDR 0xfffffa18 | |
861 | #define LCXP WORD_REF(LCXP_ADDR) | |
862 | ||
863 | #define LCXP_CC_MASK 0xc000 /* Cursor Control */ | |
864 | #define LCXP_CC_TRAMSPARENT 0x0000 | |
865 | #define LCXP_CC_BLACK 0x4000 | |
866 | #define LCXP_CC_REVERSED 0x8000 | |
867 | #define LCXP_CC_WHITE 0xc000 | |
868 | #define LCXP_CXP_MASK 0x02ff /* Cursor X position */ | |
869 | ||
870 | /* | |
871 | * LCD Cursor Y Position Register | |
872 | */ | |
873 | #define LCYP_ADDR 0xfffffa1a | |
874 | #define LCYP WORD_REF(LCYP_ADDR) | |
875 | ||
876 | #define LCYP_CYP_MASK 0x01ff /* Cursor Y Position */ | |
877 | ||
878 | /* | |
879 | * LCD Cursor Width and Heigth Register | |
880 | */ | |
881 | #define LCWCH_ADDR 0xfffffa1c | |
882 | #define LCWCH WORD_REF(LCWCH_ADDR) | |
883 | ||
884 | #define LCWCH_CH_MASK 0x001f /* Cursor Height */ | |
885 | #define LCWCH_CH_SHIFT 0 | |
886 | #define LCWCH_CW_MASK 0x1f00 /* Cursor Width */ | |
887 | #define LCWCH_CW_SHIFT 8 | |
888 | ||
889 | /* | |
890 | * LCD Blink Control Register | |
891 | */ | |
892 | #define LBLKC_ADDR 0xfffffa1f | |
893 | #define LBLKC BYTE_REF(LBLKC_ADDR) | |
894 | ||
895 | #define LBLKC_BD_MASK 0x7f /* Blink Divisor */ | |
896 | #define LBLKC_BD_SHIFT 0 | |
897 | #define LBLKC_BKEN 0x80 /* Blink Enabled */ | |
898 | ||
899 | /* | |
900 | * LCD Panel Interface Configuration Register | |
901 | */ | |
902 | #define LPICF_ADDR 0xfffffa20 | |
903 | #define LPICF BYTE_REF(LPICF_ADDR) | |
904 | ||
905 | #define LPICF_GS_MASK 0x03 /* Gray-Scale Mode */ | |
906 | #define LPICF_GS_BW 0x00 | |
907 | #define LPICF_GS_GRAY_4 0x01 | |
908 | #define LPICF_GS_GRAY_16 0x02 | |
909 | #define LPICF_PBSIZ_MASK 0x0c /* Panel Bus Width */ | |
910 | #define LPICF_PBSIZ_1 0x00 | |
911 | #define LPICF_PBSIZ_2 0x04 | |
912 | #define LPICF_PBSIZ_4 0x08 | |
913 | ||
914 | /* | |
915 | * LCD Polarity Configuration Register | |
916 | */ | |
917 | #define LPOLCF_ADDR 0xfffffa21 | |
918 | #define LPOLCF BYTE_REF(LPOLCF_ADDR) | |
919 | ||
920 | #define LPOLCF_PIXPOL 0x01 /* Pixel Polarity */ | |
921 | #define LPOLCF_LPPOL 0x02 /* Line Pulse Polarity */ | |
922 | #define LPOLCF_FLMPOL 0x04 /* Frame Marker Polarity */ | |
923 | #define LPOLCF_LCKPOL 0x08 /* LCD Shift Lock Polarity */ | |
924 | ||
925 | /* | |
926 | * LACD (LCD Alternate Crystal Direction) Rate Control Register | |
927 | */ | |
928 | #define LACDRC_ADDR 0xfffffa23 | |
929 | #define LACDRC BYTE_REF(LACDRC_ADDR) | |
930 | ||
931 | #define LACDRC_ACDSLT 0x80 /* Signal Source Select */ | |
932 | #define LACDRC_ACD_MASK 0x0f /* Alternate Crystal Direction Control */ | |
933 | #define LACDRC_ACD_SHIFT 0 | |
934 | ||
935 | /* | |
936 | * LCD Pixel Clock Divider Register | |
937 | */ | |
938 | #define LPXCD_ADDR 0xfffffa25 | |
939 | #define LPXCD BYTE_REF(LPXCD_ADDR) | |
940 | ||
941 | #define LPXCD_PCD_MASK 0x3f /* Pixel Clock Divider */ | |
942 | #define LPXCD_PCD_SHIFT 0 | |
943 | ||
944 | /* | |
945 | * LCD Clocking Control Register | |
946 | */ | |
947 | #define LCKCON_ADDR 0xfffffa27 | |
948 | #define LCKCON BYTE_REF(LCKCON_ADDR) | |
949 | ||
950 | #define LCKCON_DWS_MASK 0x0f /* Display Wait-State */ | |
951 | #define LCKCON_DWS_SHIFT 0 | |
952 | #define LCKCON_DWIDTH 0x40 /* Display Memory Width */ | |
953 | #define LCKCON_LCDON 0x80 /* Enable LCD Controller */ | |
954 | ||
955 | /* '328-compatible definitions */ | |
956 | #define LCKCON_DW_MASK LCKCON_DWS_MASK | |
957 | #define LCKCON_DW_SHIFT LCKCON_DWS_SHIFT | |
958 | ||
959 | /* | |
960 | * LCD Refresh Rate Adjustment Register | |
961 | */ | |
962 | #define LRRA_ADDR 0xfffffa29 | |
963 | #define LRRA BYTE_REF(LRRA_ADDR) | |
964 | ||
965 | /* | |
966 | * LCD Panning Offset Register | |
967 | */ | |
968 | #define LPOSR_ADDR 0xfffffa2d | |
969 | #define LPOSR BYTE_REF(LPOSR_ADDR) | |
970 | ||
971 | #define LPOSR_POS_MASK 0x0f /* Pixel Offset Code */ | |
972 | #define LPOSR_POS_SHIFT 0 | |
973 | ||
974 | /* | |
975 | * LCD Frame Rate Control Modulation Register | |
976 | */ | |
977 | #define LFRCM_ADDR 0xfffffa31 | |
978 | #define LFRCM BYTE_REF(LFRCM_ADDR) | |
979 | ||
980 | #define LFRCM_YMOD_MASK 0x0f /* Vertical Modulation */ | |
981 | #define LFRCM_YMOD_SHIFT 0 | |
982 | #define LFRCM_XMOD_MASK 0xf0 /* Horizontal Modulation */ | |
983 | #define LFRCM_XMOD_SHIFT 4 | |
984 | ||
985 | /* | |
986 | * LCD Gray Palette Mapping Register | |
987 | */ | |
988 | #define LGPMR_ADDR 0xfffffa33 | |
989 | #define LGPMR BYTE_REF(LGPMR_ADDR) | |
990 | ||
991 | #define LGPMR_G1_MASK 0x0f | |
992 | #define LGPMR_G1_SHIFT 0 | |
993 | #define LGPMR_G2_MASK 0xf0 | |
994 | #define LGPMR_G2_SHIFT 4 | |
995 | ||
996 | /* | |
997 | * PWM Contrast Control Register | |
998 | */ | |
999 | #define PWMR_ADDR 0xfffffa36 | |
1000 | #define PWMR WORD_REF(PWMR_ADDR) | |
1001 | ||
1002 | #define PWMR_PW_MASK 0x00ff /* Pulse Width */ | |
1003 | #define PWMR_PW_SHIFT 0 | |
1004 | #define PWMR_CCPEN 0x0100 /* Contrast Control Enable */ | |
1005 | #define PWMR_SRC_MASK 0x0600 /* Input Clock Source */ | |
1006 | #define PWMR_SRC_LINE 0x0000 /* Line Pulse */ | |
1007 | #define PWMR_SRC_PIXEL 0x0200 /* Pixel Clock */ | |
1008 | #define PWMR_SRC_LCD 0x4000 /* LCD clock */ | |
1009 | ||
1010 | /********** | |
1011 | * | |
1012 | * 0xFFFFFBxx -- Real-Time Clock (RTC) | |
1013 | * | |
1014 | **********/ | |
1015 | ||
1016 | /* | |
1017 | * RTC Hours Minutes and Seconds Register | |
1018 | */ | |
1019 | #define RTCTIME_ADDR 0xfffffb00 | |
1020 | #define RTCTIME LONG_REF(RTCTIME_ADDR) | |
1021 | ||
1022 | #define RTCTIME_SECONDS_MASK 0x0000003f /* Seconds */ | |
1023 | #define RTCTIME_SECONDS_SHIFT 0 | |
1024 | #define RTCTIME_MINUTES_MASK 0x003f0000 /* Minutes */ | |
1025 | #define RTCTIME_MINUTES_SHIFT 16 | |
1026 | #define RTCTIME_HOURS_MASK 0x1f000000 /* Hours */ | |
1027 | #define RTCTIME_HOURS_SHIFT 24 | |
1028 | ||
1029 | /* | |
1030 | * RTC Alarm Register | |
1031 | */ | |
1032 | #define RTCALRM_ADDR 0xfffffb04 | |
1033 | #define RTCALRM LONG_REF(RTCALRM_ADDR) | |
1034 | ||
1035 | #define RTCALRM_SECONDS_MASK 0x0000003f /* Seconds */ | |
1036 | #define RTCALRM_SECONDS_SHIFT 0 | |
1037 | #define RTCALRM_MINUTES_MASK 0x003f0000 /* Minutes */ | |
1038 | #define RTCALRM_MINUTES_SHIFT 16 | |
1039 | #define RTCALRM_HOURS_MASK 0x1f000000 /* Hours */ | |
1040 | #define RTCALRM_HOURS_SHIFT 24 | |
1041 | ||
1042 | /* | |
1043 | * Watchdog Timer Register | |
1044 | */ | |
1045 | #define WATCHDOG_ADDR 0xfffffb0a | |
1046 | #define WATCHDOG WORD_REF(WATCHDOG_ADDR) | |
1047 | ||
1048 | #define WATCHDOG_EN 0x0001 /* Watchdog Enabled */ | |
1049 | #define WATCHDOG_ISEL 0x0002 /* Select the watchdog interrupt */ | |
6c655db0 | 1050 | #define WATCHDOG_INTF 0x0080 /* Watchdog interrupt occurred */ |
1da177e4 LT |
1051 | #define WATCHDOG_CNT_MASK 0x0300 /* Watchdog Counter */ |
1052 | #define WATCHDOG_CNT_SHIFT 8 | |
1053 | ||
1054 | /* | |
1055 | * RTC Control Register | |
1056 | */ | |
1057 | #define RTCCTL_ADDR 0xfffffb0c | |
1058 | #define RTCCTL WORD_REF(RTCCTL_ADDR) | |
1059 | ||
1060 | #define RTCCTL_XTL 0x0020 /* Crystal Selection */ | |
1061 | #define RTCCTL_EN 0x0080 /* RTC Enable */ | |
1062 | ||
1063 | /* '328-compatible definitions */ | |
1064 | #define RTCCTL_384 RTCCTL_XTL | |
1065 | #define RTCCTL_ENABLE RTCCTL_EN | |
1066 | ||
1067 | /* | |
1068 | * RTC Interrupt Status Register | |
1069 | */ | |
1070 | #define RTCISR_ADDR 0xfffffb0e | |
1071 | #define RTCISR WORD_REF(RTCISR_ADDR) | |
1072 | ||
1073 | #define RTCISR_SW 0x0001 /* Stopwatch timed out */ | |
1074 | #define RTCISR_MIN 0x0002 /* 1-minute interrupt has occurred */ | |
1075 | #define RTCISR_ALM 0x0004 /* Alarm interrupt has occurred */ | |
1076 | #define RTCISR_DAY 0x0008 /* 24-hour rollover interrupt has occurred */ | |
1077 | #define RTCISR_1HZ 0x0010 /* 1Hz interrupt has occurred */ | |
1078 | #define RTCISR_HR 0x0020 /* 1-hour interrupt has occurred */ | |
1079 | #define RTCISR_SAM0 0x0100 /* 4Hz / 4.6875Hz interrupt has occurred */ | |
1080 | #define RTCISR_SAM1 0x0200 /* 8Hz / 9.3750Hz interrupt has occurred */ | |
1081 | #define RTCISR_SAM2 0x0400 /* 16Hz / 18.7500Hz interrupt has occurred */ | |
1082 | #define RTCISR_SAM3 0x0800 /* 32Hz / 37.5000Hz interrupt has occurred */ | |
1083 | #define RTCISR_SAM4 0x1000 /* 64Hz / 75.0000Hz interrupt has occurred */ | |
1084 | #define RTCISR_SAM5 0x2000 /* 128Hz / 150.0000Hz interrupt has occurred */ | |
1085 | #define RTCISR_SAM6 0x4000 /* 256Hz / 300.0000Hz interrupt has occurred */ | |
1086 | #define RTCISR_SAM7 0x8000 /* 512Hz / 600.0000Hz interrupt has occurred */ | |
1087 | ||
1088 | /* | |
1089 | * RTC Interrupt Enable Register | |
1090 | */ | |
1091 | #define RTCIENR_ADDR 0xfffffb10 | |
1092 | #define RTCIENR WORD_REF(RTCIENR_ADDR) | |
1093 | ||
1094 | #define RTCIENR_SW 0x0001 /* Stopwatch interrupt enable */ | |
1095 | #define RTCIENR_MIN 0x0002 /* 1-minute interrupt enable */ | |
1096 | #define RTCIENR_ALM 0x0004 /* Alarm interrupt enable */ | |
1097 | #define RTCIENR_DAY 0x0008 /* 24-hour rollover interrupt enable */ | |
1098 | #define RTCIENR_1HZ 0x0010 /* 1Hz interrupt enable */ | |
1099 | #define RTCIENR_HR 0x0020 /* 1-hour interrupt enable */ | |
1100 | #define RTCIENR_SAM0 0x0100 /* 4Hz / 4.6875Hz interrupt enable */ | |
1101 | #define RTCIENR_SAM1 0x0200 /* 8Hz / 9.3750Hz interrupt enable */ | |
1102 | #define RTCIENR_SAM2 0x0400 /* 16Hz / 18.7500Hz interrupt enable */ | |
1103 | #define RTCIENR_SAM3 0x0800 /* 32Hz / 37.5000Hz interrupt enable */ | |
1104 | #define RTCIENR_SAM4 0x1000 /* 64Hz / 75.0000Hz interrupt enable */ | |
1105 | #define RTCIENR_SAM5 0x2000 /* 128Hz / 150.0000Hz interrupt enable */ | |
1106 | #define RTCIENR_SAM6 0x4000 /* 256Hz / 300.0000Hz interrupt enable */ | |
1107 | #define RTCIENR_SAM7 0x8000 /* 512Hz / 600.0000Hz interrupt enable */ | |
1108 | ||
1109 | /* | |
1110 | * Stopwatch Minutes Register | |
1111 | */ | |
1112 | #define STPWCH_ADDR 0xfffffb12 | |
1113 | #define STPWCH WORD_REF(STPWCH) | |
1114 | ||
1115 | #define STPWCH_CNT_MASK 0x003f /* Stopwatch countdown value */ | |
1116 | #define SPTWCH_CNT_SHIFT 0 | |
1117 | ||
1118 | /* | |
1119 | * RTC Day Count Register | |
1120 | */ | |
1121 | #define DAYR_ADDR 0xfffffb1a | |
1122 | #define DAYR WORD_REF(DAYR_ADDR) | |
1123 | ||
1124 | #define DAYR_DAYS_MASK 0x1ff /* Day Setting */ | |
1125 | #define DAYR_DAYS_SHIFT 0 | |
1126 | ||
1127 | /* | |
1128 | * RTC Day Alarm Register | |
1129 | */ | |
1130 | #define DAYALARM_ADDR 0xfffffb1c | |
1131 | #define DAYALARM WORD_REF(DAYALARM_ADDR) | |
1132 | ||
1133 | #define DAYALARM_DAYSAL_MASK 0x01ff /* Day Setting of the Alarm */ | |
1134 | #define DAYALARM_DAYSAL_SHIFT 0 | |
1135 | ||
1136 | /********** | |
1137 | * | |
1138 | * 0xFFFFFCxx -- DRAM Controller | |
1139 | * | |
1140 | **********/ | |
1141 | ||
1142 | /* | |
1143 | * DRAM Memory Configuration Register | |
1144 | */ | |
1145 | #define DRAMMC_ADDR 0xfffffc00 | |
1146 | #define DRAMMC WORD_REF(DRAMMC_ADDR) | |
1147 | ||
1148 | #define DRAMMC_ROW12_MASK 0xc000 /* Row address bit for MD12 */ | |
1149 | #define DRAMMC_ROW12_PA10 0x0000 | |
1150 | #define DRAMMC_ROW12_PA21 0x4000 | |
1151 | #define DRAMMC_ROW12_PA23 0x8000 | |
1152 | #define DRAMMC_ROW0_MASK 0x3000 /* Row address bit for MD0 */ | |
1153 | #define DRAMMC_ROW0_PA11 0x0000 | |
1154 | #define DRAMMC_ROW0_PA22 0x1000 | |
1155 | #define DRAMMC_ROW0_PA23 0x2000 | |
1156 | #define DRAMMC_ROW11 0x0800 /* Row address bit for MD11 PA20/PA22 */ | |
1157 | #define DRAMMC_ROW10 0x0400 /* Row address bit for MD10 PA19/PA21 */ | |
1158 | #define DRAMMC_ROW9 0x0200 /* Row address bit for MD9 PA9/PA19 */ | |
1159 | #define DRAMMC_ROW8 0x0100 /* Row address bit for MD8 PA10/PA20 */ | |
1160 | #define DRAMMC_COL10 0x0080 /* Col address bit for MD10 PA11/PA0 */ | |
1161 | #define DRAMMC_COL9 0x0040 /* Col address bit for MD9 PA10/PA0 */ | |
1162 | #define DRAMMC_COL8 0x0020 /* Col address bit for MD8 PA9/PA0 */ | |
1163 | #define DRAMMC_REF_MASK 0x001f /* Reresh Cycle */ | |
1164 | #define DRAMMC_REF_SHIFT 0 | |
1165 | ||
1166 | /* | |
1167 | * DRAM Control Register | |
1168 | */ | |
1169 | #define DRAMC_ADDR 0xfffffc02 | |
1170 | #define DRAMC WORD_REF(DRAMC_ADDR) | |
1171 | ||
1172 | #define DRAMC_DWE 0x0001 /* DRAM Write Enable */ | |
1173 | #define DRAMC_RST 0x0002 /* Reset Burst Refresh Enable */ | |
1174 | #define DRAMC_LPR 0x0004 /* Low-Power Refresh Enable */ | |
1175 | #define DRAMC_SLW 0x0008 /* Slow RAM */ | |
1176 | #define DRAMC_LSP 0x0010 /* Light Sleep */ | |
1177 | #define DRAMC_MSW 0x0020 /* Slow Multiplexing */ | |
1178 | #define DRAMC_WS_MASK 0x00c0 /* Wait-states */ | |
1179 | #define DRAMC_WS_SHIFT 6 | |
1180 | #define DRAMC_PGSZ_MASK 0x0300 /* Page Size for fast page mode */ | |
1181 | #define DRAMC_PGSZ_SHIFT 8 | |
1182 | #define DRAMC_PGSZ_256K 0x0000 | |
1183 | #define DRAMC_PGSZ_512K 0x0100 | |
1184 | #define DRAMC_PGSZ_1024K 0x0200 | |
1185 | #define DRAMC_PGSZ_2048K 0x0300 | |
1186 | #define DRAMC_EDO 0x0400 /* EDO DRAM */ | |
1187 | #define DRAMC_CLK 0x0800 /* Refresh Timer Clock source select */ | |
1188 | #define DRAMC_BC_MASK 0x3000 /* Page Access Clock Cycle (FP mode) */ | |
1189 | #define DRAMC_BC_SHIFT 12 | |
1190 | #define DRAMC_RM 0x4000 /* Refresh Mode */ | |
1191 | #define DRAMC_EN 0x8000 /* DRAM Controller enable */ | |
1192 | ||
1193 | ||
1194 | /********** | |
1195 | * | |
1196 | * 0xFFFFFDxx -- In-Circuit Emulation (ICE) | |
1197 | * | |
1198 | **********/ | |
1199 | ||
1200 | /* | |
1201 | * ICE Module Address Compare Register | |
1202 | */ | |
1203 | #define ICEMACR_ADDR 0xfffffd00 | |
1204 | #define ICEMACR LONG_REF(ICEMACR_ADDR) | |
1205 | ||
1206 | /* | |
1207 | * ICE Module Address Mask Register | |
1208 | */ | |
1209 | #define ICEMAMR_ADDR 0xfffffd04 | |
1210 | #define ICEMAMR LONG_REF(ICEMAMR_ADDR) | |
1211 | ||
1212 | /* | |
1213 | * ICE Module Control Compare Register | |
1214 | */ | |
1215 | #define ICEMCCR_ADDR 0xfffffd08 | |
1216 | #define ICEMCCR WORD_REF(ICEMCCR_ADDR) | |
1217 | ||
1218 | #define ICEMCCR_PD 0x0001 /* Program/Data Cycle Selection */ | |
1219 | #define ICEMCCR_RW 0x0002 /* Read/Write Cycle Selection */ | |
1220 | ||
1221 | /* | |
1222 | * ICE Module Control Mask Register | |
1223 | */ | |
1224 | #define ICEMCMR_ADDR 0xfffffd0a | |
1225 | #define ICEMCMR WORD_REF(ICEMCMR_ADDR) | |
1226 | ||
1227 | #define ICEMCMR_PDM 0x0001 /* Program/Data Cycle Mask */ | |
1228 | #define ICEMCMR_RWM 0x0002 /* Read/Write Cycle Mask */ | |
1229 | ||
1230 | /* | |
1231 | * ICE Module Control Register | |
1232 | */ | |
1233 | #define ICEMCR_ADDR 0xfffffd0c | |
1234 | #define ICEMCR WORD_REF(ICEMCR_ADDR) | |
1235 | ||
1236 | #define ICEMCR_CEN 0x0001 /* Compare Enable */ | |
1237 | #define ICEMCR_PBEN 0x0002 /* Program Break Enable */ | |
1238 | #define ICEMCR_SB 0x0004 /* Single Breakpoint */ | |
1239 | #define ICEMCR_HMDIS 0x0008 /* HardMap disable */ | |
1240 | #define ICEMCR_BBIEN 0x0010 /* Bus Break Interrupt Enable */ | |
1241 | ||
1242 | /* | |
1243 | * ICE Module Status Register | |
1244 | */ | |
1245 | #define ICEMSR_ADDR 0xfffffd0e | |
1246 | #define ICEMSR WORD_REF(ICEMSR_ADDR) | |
1247 | ||
1248 | #define ICEMSR_EMUEN 0x0001 /* Emulation Enable */ | |
1249 | #define ICEMSR_BRKIRQ 0x0002 /* A-Line Vector Fetch Detected */ | |
1250 | #define ICEMSR_BBIRQ 0x0004 /* Bus Break Interrupt Detected */ | |
1251 | #define ICEMSR_EMIRQ 0x0008 /* EMUIRQ Falling Edge Detected */ | |
1252 | ||
1253 | #endif /* _MC68EZ328_H_ */ |