[mirror_ubuntu-bionic-kernel.git] / arch / m68k / include / asm / atomic.h

/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __ARCH_M68K_ATOMIC__
#define __ARCH_M68K_ATOMIC__

#include <linux/types.h>
#include <linux/irqflags.h>
#include <asm/cmpxchg.h>
#include <asm/barrier.h>

/*
 * Atomic operations that C can't guarantee us.  Useful for
 * resource counting etc..
 */

/*
 * We do not have SMP m68k systems, so we don't have to deal with that.
 */

#define ATOMIC_INIT(i)	{ (i) }

#define atomic_read(v)		READ_ONCE((v)->counter)
#define atomic_set(v, i)	WRITE_ONCE(((v)->counter), (i))

/*
 * The ColdFire parts cannot do some immediate to memory operations,
 * so for them we do not specify the "i" asm constraint.
 */
#ifdef CONFIG_COLDFIRE
#define	ASM_DI	"d"
#else
#define	ASM_DI	"di"
#endif

#define ATOMIC_OP(op, c_op, asm_op)					\
static inline void atomic_##op(int i, atomic_t *v)			\
{									\
	__asm__ __volatile__(#asm_op "l %1,%0" : "+m" (*v) : ASM_DI (i));\
}									\

#ifdef CONFIG_RMW_INSNS

#define ATOMIC_OP_RETURN(op, c_op, asm_op)				\
static inline int atomic_##op##_return(int i, atomic_t *v)		\
{									\
	int t, tmp;							\
									\
	__asm__ __volatile__(						\
			"1:	movel %2,%1\n"				\
			"	" #asm_op "l %3,%1\n"			\
			"	casl %2,%1,%0\n"			\
			"	jne 1b"					\
			: "+m" (*v), "=&d" (t), "=&d" (tmp)		\
			: "g" (i), "2" (atomic_read(v)));		\
	return t;							\
}

#define ATOMIC_FETCH_OP(op, c_op, asm_op)				\
static inline int atomic_fetch_##op(int i, atomic_t *v)			\
{									\
	int t, tmp;							\
									\
	__asm__ __volatile__(						\
			"1:	movel %2,%1\n"				\
			"	" #asm_op "l %3,%1\n"			\
			"	casl %2,%1,%0\n"			\
			"	jne 1b"					\
			: "+m" (*v), "=&d" (t), "=&d" (tmp)		\
			: "g" (i), "2" (atomic_read(v)));		\
	return tmp;							\
}

#else

#define ATOMIC_OP_RETURN(op, c_op, asm_op)				\
static inline int atomic_##op##_return(int i, atomic_t * v)		\
{									\
	unsigned long flags;						\
	int t;								\
									\
	local_irq_save(flags);						\
	t = (v->counter c_op i);					\
	local_irq_restore(flags);					\
									\
	return t;							\
}

#define ATOMIC_FETCH_OP(op, c_op, asm_op)				\
static inline int atomic_fetch_##op(int i, atomic_t * v)		\
{									\
	unsigned long flags;						\
	int t;								\
									\
	local_irq_save(flags);						\
	t = v->counter;							\
	v->counter c_op i;						\
	local_irq_restore(flags);					\
									\
	return t;							\
}

#endif /* CONFIG_RMW_INSNS */

#define ATOMIC_OPS(op, c_op, asm_op)					\
	ATOMIC_OP(op, c_op, asm_op)					\
	ATOMIC_OP_RETURN(op, c_op, asm_op)				\
	ATOMIC_FETCH_OP(op, c_op, asm_op)

ATOMIC_OPS(add, +=, add)
ATOMIC_OPS(sub, -=, sub)

#undef ATOMIC_OPS
#define ATOMIC_OPS(op, c_op, asm_op)					\
	ATOMIC_OP(op, c_op, asm_op)					\
	ATOMIC_FETCH_OP(op, c_op, asm_op)

ATOMIC_OPS(and, &=, and)
ATOMIC_OPS(or, |=, or)
ATOMIC_OPS(xor, ^=, eor)

#undef ATOMIC_OPS
#undef ATOMIC_FETCH_OP
#undef ATOMIC_OP_RETURN
#undef ATOMIC_OP

static inline void atomic_inc(atomic_t *v)
{
	__asm__ __volatile__("addql #1,%0" : "+m" (*v));
}

static inline void atomic_dec(atomic_t *v)
{
	__asm__ __volatile__("subql #1,%0" : "+m" (*v));
}

static inline int atomic_dec_and_test(atomic_t *v)
{
	char c;
	__asm__ __volatile__("subql #1,%1; seq %0" : "=d" (c), "+m" (*v));
	return c != 0;
}

static inline int atomic_dec_and_test_lt(atomic_t *v)
{
	char c;
	__asm__ __volatile__(
		"subql #1,%1; slt %0"
		: "=d" (c), "=m" (*v)
		: "m" (*v));
	return c != 0;
}

static inline int atomic_inc_and_test(atomic_t *v)
{
	char c;
	__asm__ __volatile__("addql #1,%1; seq %0" : "=d" (c), "+m" (*v));
	return c != 0;
}

#ifdef CONFIG_RMW_INSNS

#define atomic_cmpxchg(v, o, n) ((int)cmpxchg(&((v)->counter), (o), (n)))
#define atomic_xchg(v, new) (xchg(&((v)->counter), new))

#else /* !CONFIG_RMW_INSNS */

static inline int atomic_cmpxchg(atomic_t *v, int old, int new)
{
	unsigned long flags;
	int prev;

	local_irq_save(flags);
	prev = atomic_read(v);
	if (prev == old)
		atomic_set(v, new);
	local_irq_restore(flags);
	return prev;
}

static inline int atomic_xchg(atomic_t *v, int new)
{
	unsigned long flags;
	int prev;

	local_irq_save(flags);
	prev = atomic_read(v);
	atomic_set(v, new);
	local_irq_restore(flags);
	return prev;
}

#endif /* !CONFIG_RMW_INSNS */

#define atomic_dec_return(v)	atomic_sub_return(1, (v))
#define atomic_inc_return(v)	atomic_add_return(1, (v))

static inline int atomic_sub_and_test(int i, atomic_t *v)
{
	char c;
	__asm__ __volatile__("subl %2,%1; seq %0"
			     : "=d" (c), "+m" (*v)
			     : ASM_DI (i));
	return c != 0;
}

static inline int atomic_add_negative(int i, atomic_t *v)
{
	char c;
	__asm__ __volatile__("addl %2,%1; smi %0"
			     : "=d" (c), "+m" (*v)
			     : ASM_DI (i));
	return c != 0;
}

static __inline__ int __atomic_add_unless(atomic_t *v, int a, int u)
{
	int c, old;
	c = atomic_read(v);
	for (;;) {
		if (unlikely(c == (u)))
			break;
		old = atomic_cmpxchg((v), c, c + (a));
		if (likely(old == c))
			break;
		c = old;
	}
	return c;
}

#endif /* __ARCH_M68K_ATOMIC __ */
Commit	Line	Data
b2441318	1	/* SPDX-License-Identifier: GPL-2.0 */
69f99746 GU	2	#ifndef __ARCH_M68K_ATOMIC__
	3	#define __ARCH_M68K_ATOMIC__
	4
	5	#include <linux/types.h>
803f6914	6	#include <linux/irqflags.h>
7224c0d1	7	#include <asm/cmpxchg.h>
2db56e86	8	#include <asm/barrier.h>
69f99746 GU	9
	10	/*
	11	* Atomic operations that C can't guarantee us. Useful for
	12	* resource counting etc..
	13	*/
	14
	15	/*
	16	* We do not have SMP m68k systems, so we don't have to deal with that.
	17	*/
	18
	19	#define ATOMIC_INIT(i) { (i) }
	20
62e8a325 PZ	21	#define atomic_read(v) READ_ONCE((v)->counter)
62e8a325 PZ	22	#define atomic_set(v, i) WRITE_ONCE(((v)->counter), (i))
69f99746 GU	23
	24	/*
	25	* The ColdFire parts cannot do some immediate to memory operations,
	26	* so for them we do not specify the "i" asm constraint.
	27	*/
	28	#ifdef CONFIG_COLDFIRE
	29	#define ASM_DI "d"
49148020	30	#else
69f99746	31	#define ASM_DI "di"
49148020	32	#endif
b417b717	33
d839bae4 PZ	34	#define ATOMIC_OP(op, c_op, asm_op) \
	35	static inline void atomic_##op(int i, atomic_t *v) \
	36	{ \
	37	__asm__ __volatile__(#asm_op "l %1,%0" : "+m" (*v) : ASM_DI (i));\
	38	} \
	39
	40	#ifdef CONFIG_RMW_INSNS
	41
	42	#define ATOMIC_OP_RETURN(op, c_op, asm_op) \
	43	static inline int atomic_##op##_return(int i, atomic_t *v) \
	44	{ \
	45	int t, tmp; \
	46	\
	47	__asm__ __volatile__( \
	48	"1: movel %2,%1\n" \
	49	" " #asm_op "l %3,%1\n" \
	50	" casl %2,%1,%0\n" \
	51	" jne 1b" \
	52	: "+m" (*v), "=&d" (t), "=&d" (tmp) \
	53	: "g" (i), "2" (atomic_read(v))); \
	54	return t; \
69f99746 GU	55	}
69f99746 GU	56
e39d88ea PZ	57	#define ATOMIC_FETCH_OP(op, c_op, asm_op) \
	58	static inline int atomic_fetch_##op(int i, atomic_t *v) \
	59	{ \
	60	int t, tmp; \
	61	\
	62	__asm__ __volatile__( \
	63	"1: movel %2,%1\n" \
	64	" " #asm_op "l %3,%1\n" \
	65	" casl %2,%1,%0\n" \
	66	" jne 1b" \
	67	: "+m" (*v), "=&d" (t), "=&d" (tmp) \
	68	: "g" (i), "2" (atomic_read(v))); \
	69	return tmp; \
	70	}
	71
d839bae4 PZ	72	#else
	73
	74	#define ATOMIC_OP_RETURN(op, c_op, asm_op) \
	75	static inline int atomic_##op##_return(int i, atomic_t * v) \
	76	{ \
	77	unsigned long flags; \
	78	int t; \
	79	\
	80	local_irq_save(flags); \
	81	t = (v->counter c_op i); \
	82	local_irq_restore(flags); \
	83	\
	84	return t; \
69f99746 GU	85	}
69f99746 GU	86
e39d88ea PZ	87	#define ATOMIC_FETCH_OP(op, c_op, asm_op) \
	88	static inline int atomic_fetch_##op(int i, atomic_t * v) \
	89	{ \
	90	unsigned long flags; \
	91	int t; \
	92	\
	93	local_irq_save(flags); \
	94	t = v->counter; \
	95	v->counter c_op i; \
	96	local_irq_restore(flags); \
	97	\
	98	return t; \
	99	}
	100
d839bae4 PZ	101	#endif /* CONFIG_RMW_INSNS */
	102
	103	#define ATOMIC_OPS(op, c_op, asm_op) \
	104	ATOMIC_OP(op, c_op, asm_op) \
e39d88ea PZ	105	ATOMIC_OP_RETURN(op, c_op, asm_op) \
e39d88ea PZ	106	ATOMIC_FETCH_OP(op, c_op, asm_op)
d839bae4 PZ	107
	108	ATOMIC_OPS(add, +=, add)
	109	ATOMIC_OPS(sub, -=, sub)
	110
e39d88ea PZ	111	#undef ATOMIC_OPS
	112	#define ATOMIC_OPS(op, c_op, asm_op) \
	113	ATOMIC_OP(op, c_op, asm_op) \
	114	ATOMIC_FETCH_OP(op, c_op, asm_op)
	115
e39d88ea PZ	116	ATOMIC_OPS(and, &=, and)
	117	ATOMIC_OPS(or, \|=, or)
	118	ATOMIC_OPS(xor, ^=, eor)
74b1bc50	119
d839bae4	120	#undef ATOMIC_OPS
e39d88ea	121	#undef ATOMIC_FETCH_OP
d839bae4 PZ	122	#undef ATOMIC_OP_RETURN
	123	#undef ATOMIC_OP
	124
69f99746 GU	125	static inline void atomic_inc(atomic_t *v)
	126	{
	127	__asm__ __volatile__("addql #1,%0" : "+m" (*v));
	128	}
	129
	130	static inline void atomic_dec(atomic_t *v)
	131	{
	132	__asm__ __volatile__("subql #1,%0" : "+m" (*v));
	133	}
	134
	135	static inline int atomic_dec_and_test(atomic_t *v)
	136	{
	137	char c;
	138	__asm__ __volatile__("subql #1,%1; seq %0" : "=d" (c), "+m" (*v));
	139	return c != 0;
	140	}
	141
83b73d6c GU	142	static inline int atomic_dec_and_test_lt(atomic_t *v)
	143	{
	144	char c;
	145	__asm__ __volatile__(
	146	"subql #1,%1; slt %0"
	147	: "=d" (c), "=m" (*v)
	148	: "m" (*v));
	149	return c != 0;
	150	}
	151
69f99746 GU	152	static inline int atomic_inc_and_test(atomic_t *v)
	153	{
	154	char c;
	155	__asm__ __volatile__("addql #1,%1; seq %0" : "=d" (c), "+m" (*v));
	156	return c != 0;
	157	}
	158
	159	#ifdef CONFIG_RMW_INSNS
	160
69f99746 GU	161	#define atomic_cmpxchg(v, o, n) ((int)cmpxchg(&((v)->counter), (o), (n)))
	162	#define atomic_xchg(v, new) (xchg(&((v)->counter), new))
	163
	164	#else /* !CONFIG_RMW_INSNS */
	165
69f99746 GU	166	static inline int atomic_cmpxchg(atomic_t *v, int old, int new)
	167	{
	168	unsigned long flags;
	169	int prev;
	170
	171	local_irq_save(flags);
	172	prev = atomic_read(v);
	173	if (prev == old)
	174	atomic_set(v, new);
	175	local_irq_restore(flags);
	176	return prev;
	177	}
	178
	179	static inline int atomic_xchg(atomic_t *v, int new)
	180	{
	181	unsigned long flags;
	182	int prev;
	183
	184	local_irq_save(flags);
	185	prev = atomic_read(v);
	186	atomic_set(v, new);
	187	local_irq_restore(flags);
	188	return prev;
	189	}
	190
	191	#endif /* !CONFIG_RMW_INSNS */
	192
	193	#define atomic_dec_return(v) atomic_sub_return(1, (v))
	194	#define atomic_inc_return(v) atomic_add_return(1, (v))
	195
	196	static inline int atomic_sub_and_test(int i, atomic_t *v)
	197	{
	198	char c;
	199	__asm__ __volatile__("subl %2,%1; seq %0"
	200	: "=d" (c), "+m" (*v)
	201	: ASM_DI (i));
	202	return c != 0;
	203	}
	204
	205	static inline int atomic_add_negative(int i, atomic_t *v)
	206	{
	207	char c;
	208	__asm__ __volatile__("addl %2,%1; smi %0"
	209	: "=d" (c), "+m" (*v)
35de6749	210	: ASM_DI (i));
69f99746 GU	211	return c != 0;
	212	}
	213
f24219b4	214	static __inline__ int __atomic_add_unless(atomic_t *v, int a, int u)
69f99746 GU	215	{
	216	int c, old;
	217	c = atomic_read(v);
	218	for (;;) {
	219	if (unlikely(c == (u)))
	220	break;
	221	old = atomic_cmpxchg((v), c, c + (a));
	222	if (likely(old == c))
	223	break;
	224	c = old;
	225	}
f24219b4	226	return c;
69f99746 GU	227	}
69f99746 GU	228
69f99746	229	#endif /* __ARCH_M68K_ATOMIC __ */