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1da177e4 LT |
1 | #ifndef __ARCH_M68K_ATOMIC__ |
2 | #define __ARCH_M68K_ATOMIC__ | |
3 | ||
ea435467 | 4 | #include <linux/types.h> |
2856f5e3 | 5 | #include <asm/system.h> |
1da177e4 LT |
6 | |
7 | /* | |
8 | * Atomic operations that C can't guarantee us. Useful for | |
9 | * resource counting etc.. | |
10 | */ | |
11 | ||
12 | /* | |
13 | * We do not have SMP m68k systems, so we don't have to deal with that. | |
14 | */ | |
15 | ||
1da177e4 LT |
16 | #define ATOMIC_INIT(i) { (i) } |
17 | ||
18 | #define atomic_read(v) ((v)->counter) | |
19 | #define atomic_set(v, i) (((v)->counter) = i) | |
20 | ||
21 | static inline void atomic_add(int i, atomic_t *v) | |
22 | { | |
23 | __asm__ __volatile__("addl %1,%0" : "+m" (*v) : "id" (i)); | |
24 | } | |
25 | ||
26 | static inline void atomic_sub(int i, atomic_t *v) | |
27 | { | |
28 | __asm__ __volatile__("subl %1,%0" : "+m" (*v) : "id" (i)); | |
29 | } | |
30 | ||
31 | static inline void atomic_inc(atomic_t *v) | |
32 | { | |
33 | __asm__ __volatile__("addql #1,%0" : "+m" (*v)); | |
34 | } | |
35 | ||
36 | static inline void atomic_dec(atomic_t *v) | |
37 | { | |
38 | __asm__ __volatile__("subql #1,%0" : "+m" (*v)); | |
39 | } | |
40 | ||
41 | static inline int atomic_dec_and_test(atomic_t *v) | |
42 | { | |
43 | char c; | |
44 | __asm__ __volatile__("subql #1,%1; seq %0" : "=d" (c), "+m" (*v)); | |
45 | return c != 0; | |
46 | } | |
47 | ||
48 | static inline int atomic_inc_and_test(atomic_t *v) | |
49 | { | |
50 | char c; | |
51 | __asm__ __volatile__("addql #1,%1; seq %0" : "=d" (c), "+m" (*v)); | |
52 | return c != 0; | |
53 | } | |
54 | ||
55 | #ifdef CONFIG_RMW_INSNS | |
7b61fcda | 56 | |
1da177e4 LT |
57 | static inline int atomic_add_return(int i, atomic_t *v) |
58 | { | |
59 | int t, tmp; | |
60 | ||
61 | __asm__ __volatile__( | |
62 | "1: movel %2,%1\n" | |
63 | " addl %3,%1\n" | |
64 | " casl %2,%1,%0\n" | |
65 | " jne 1b" | |
66 | : "+m" (*v), "=&d" (t), "=&d" (tmp) | |
67 | : "g" (i), "2" (atomic_read(v))); | |
68 | return t; | |
69 | } | |
70 | ||
71 | static inline int atomic_sub_return(int i, atomic_t *v) | |
72 | { | |
73 | int t, tmp; | |
74 | ||
75 | __asm__ __volatile__( | |
76 | "1: movel %2,%1\n" | |
77 | " subl %3,%1\n" | |
78 | " casl %2,%1,%0\n" | |
79 | " jne 1b" | |
80 | : "+m" (*v), "=&d" (t), "=&d" (tmp) | |
81 | : "g" (i), "2" (atomic_read(v))); | |
82 | return t; | |
83 | } | |
7b61fcda RZ |
84 | |
85 | #define atomic_cmpxchg(v, o, n) ((int)cmpxchg(&((v)->counter), (o), (n))) | |
86 | #define atomic_xchg(v, new) (xchg(&((v)->counter), new)) | |
87 | ||
1da177e4 | 88 | #else /* !CONFIG_RMW_INSNS */ |
7b61fcda | 89 | |
1da177e4 LT |
90 | static inline int atomic_add_return(int i, atomic_t * v) |
91 | { | |
92 | unsigned long flags; | |
93 | int t; | |
94 | ||
95 | local_irq_save(flags); | |
96 | t = atomic_read(v); | |
97 | t += i; | |
98 | atomic_set(v, t); | |
99 | local_irq_restore(flags); | |
100 | ||
101 | return t; | |
102 | } | |
103 | ||
104 | static inline int atomic_sub_return(int i, atomic_t * v) | |
105 | { | |
106 | unsigned long flags; | |
107 | int t; | |
108 | ||
109 | local_irq_save(flags); | |
110 | t = atomic_read(v); | |
111 | t -= i; | |
112 | atomic_set(v, t); | |
113 | local_irq_restore(flags); | |
114 | ||
115 | return t; | |
116 | } | |
7b61fcda RZ |
117 | |
118 | static inline int atomic_cmpxchg(atomic_t *v, int old, int new) | |
119 | { | |
120 | unsigned long flags; | |
121 | int prev; | |
122 | ||
123 | local_irq_save(flags); | |
124 | prev = atomic_read(v); | |
125 | if (prev == old) | |
126 | atomic_set(v, new); | |
127 | local_irq_restore(flags); | |
128 | return prev; | |
129 | } | |
130 | ||
131 | static inline int atomic_xchg(atomic_t *v, int new) | |
132 | { | |
133 | unsigned long flags; | |
134 | int prev; | |
135 | ||
136 | local_irq_save(flags); | |
137 | prev = atomic_read(v); | |
138 | atomic_set(v, new); | |
139 | local_irq_restore(flags); | |
140 | return prev; | |
141 | } | |
142 | ||
1da177e4 LT |
143 | #endif /* !CONFIG_RMW_INSNS */ |
144 | ||
145 | #define atomic_dec_return(v) atomic_sub_return(1, (v)) | |
146 | #define atomic_inc_return(v) atomic_add_return(1, (v)) | |
147 | ||
148 | static inline int atomic_sub_and_test(int i, atomic_t *v) | |
149 | { | |
150 | char c; | |
b560177f GU |
151 | __asm__ __volatile__("subl %2,%1; seq %0" |
152 | : "=d" (c), "+m" (*v) | |
153 | : "id" (i)); | |
1da177e4 LT |
154 | return c != 0; |
155 | } | |
156 | ||
157 | static inline int atomic_add_negative(int i, atomic_t *v) | |
158 | { | |
159 | char c; | |
b560177f GU |
160 | __asm__ __volatile__("addl %2,%1; smi %0" |
161 | : "=d" (c), "+m" (*v) | |
162 | : "id" (i)); | |
1da177e4 LT |
163 | return c != 0; |
164 | } | |
165 | ||
166 | static inline void atomic_clear_mask(unsigned long mask, unsigned long *v) | |
167 | { | |
168 | __asm__ __volatile__("andl %1,%0" : "+m" (*v) : "id" (~(mask))); | |
169 | } | |
170 | ||
171 | static inline void atomic_set_mask(unsigned long mask, unsigned long *v) | |
172 | { | |
173 | __asm__ __volatile__("orl %1,%0" : "+m" (*v) : "id" (mask)); | |
174 | } | |
175 | ||
2856f5e3 MD |
176 | static __inline__ int atomic_add_unless(atomic_t *v, int a, int u) |
177 | { | |
178 | int c, old; | |
179 | c = atomic_read(v); | |
180 | for (;;) { | |
181 | if (unlikely(c == (u))) | |
182 | break; | |
183 | old = atomic_cmpxchg((v), c, c + (a)); | |
184 | if (likely(old == c)) | |
185 | break; | |
186 | c = old; | |
187 | } | |
188 | return c != (u); | |
189 | } | |
190 | ||
8426e1f6 NP |
191 | #define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0) |
192 | ||
1da177e4 LT |
193 | /* Atomic operations are already serializing */ |
194 | #define smp_mb__before_atomic_dec() barrier() | |
195 | #define smp_mb__after_atomic_dec() barrier() | |
196 | #define smp_mb__before_atomic_inc() barrier() | |
197 | #define smp_mb__after_atomic_inc() barrier() | |
198 | ||
72099ed2 | 199 | #include <asm-generic/atomic-long.h> |
1da177e4 | 200 | #endif /* __ARCH_M68K_ATOMIC __ */ |