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b2441318 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
3ddc7e26 GU |
2 | #ifndef _M68K_IRQ_H_ |
3 | #define _M68K_IRQ_H_ | |
4 | ||
5 | /* | |
6 | * This should be the same as the max(NUM_X_SOURCES) for all the | |
7 | * different m68k hosts compiled into the kernel. | |
8 | * Currently the Atari has 72 and the Amiga 24, but if both are | |
9 | * supported in the kernel it is better to make room for 72. | |
736b24db MS |
10 | * With EtherNAT add-on card on Atari, the highest interrupt |
11 | * number is 140 so NR_IRQS needs to be 141. | |
3ddc7e26 GU |
12 | */ |
13 | #if defined(CONFIG_COLDFIRE) | |
14 | #define NR_IRQS 256 | |
15 | #elif defined(CONFIG_VME) || defined(CONFIG_SUN3) || defined(CONFIG_SUN3X) | |
16 | #define NR_IRQS 200 | |
736b24db MS |
17 | #elif defined(CONFIG_ATARI) |
18 | #define NR_IRQS 141 | |
19 | #elif defined(CONFIG_MAC) | |
3ddc7e26 GU |
20 | #define NR_IRQS 72 |
21 | #elif defined(CONFIG_Q40) | |
22 | #define NR_IRQS 43 | |
23 | #elif defined(CONFIG_AMIGA) || !defined(CONFIG_MMU) | |
24 | #define NR_IRQS 32 | |
25 | #elif defined(CONFIG_APOLLO) | |
26 | #define NR_IRQS 24 | |
27 | #elif defined(CONFIG_HP300) | |
28 | #define NR_IRQS 8 | |
49148020 | 29 | #else |
3ddc7e26 | 30 | #define NR_IRQS 0 |
49148020 | 31 | #endif |
3ddc7e26 | 32 | |
78ccdffc GU |
33 | #if defined(CONFIG_M68020) || defined(CONFIG_M68030) || \ |
34 | defined(CONFIG_M68040) || defined(CONFIG_M68060) | |
3ddc7e26 | 35 | |
3ddc7e26 GU |
36 | /* |
37 | * Interrupt source definitions | |
38 | * General interrupt sources are the level 1-7. | |
39 | * Adding an interrupt service routine for one of these sources | |
40 | * results in the addition of that routine to a chain of routines. | |
41 | * Each one is called in succession. Each individual interrupt | |
42 | * service routine should determine if the device associated with | |
43 | * that routine requires service. | |
44 | */ | |
45 | ||
46 | #define IRQ_SPURIOUS 0 | |
47 | ||
48 | #define IRQ_AUTO_1 1 /* level 1 interrupt */ | |
49 | #define IRQ_AUTO_2 2 /* level 2 interrupt */ | |
50 | #define IRQ_AUTO_3 3 /* level 3 interrupt */ | |
51 | #define IRQ_AUTO_4 4 /* level 4 interrupt */ | |
52 | #define IRQ_AUTO_5 5 /* level 5 interrupt */ | |
53 | #define IRQ_AUTO_6 6 /* level 6 interrupt */ | |
54 | #define IRQ_AUTO_7 7 /* level 7 interrupt (non-maskable) */ | |
55 | ||
56 | #define IRQ_USER 8 | |
57 | ||
4936f63c GU |
58 | struct irq_data; |
59 | struct irq_chip; | |
60 | struct irq_desc; | |
61 | extern unsigned int m68k_irq_startup(struct irq_data *data); | |
62 | extern unsigned int m68k_irq_startup_irq(unsigned int irq); | |
63 | extern void m68k_irq_shutdown(struct irq_data *data); | |
64 | extern void m68k_setup_auto_interrupt(void (*handler)(unsigned int, | |
65 | struct pt_regs *)); | |
f30a6484 | 66 | extern void m68k_setup_user_interrupt(unsigned int vec, unsigned int cnt); |
4936f63c | 67 | extern void m68k_setup_irq_controller(struct irq_chip *, |
bd0b9ac4 | 68 | void (*handle)(struct irq_desc *desc), |
4936f63c GU |
69 | unsigned int irq, unsigned int cnt); |
70 | ||
4936f63c GU |
71 | extern unsigned int irq_canonicalize(unsigned int irq); |
72 | ||
3ddc7e26 GU |
73 | #else |
74 | #define irq_canonicalize(irq) (irq) | |
78ccdffc | 75 | #endif /* !(CONFIG_M68020 || CONFIG_M68030 || CONFIG_M68040 || CONFIG_M68060) */ |
3ddc7e26 | 76 | |
739735d5 | 77 | asmlinkage void do_IRQ(int irq, struct pt_regs *regs); |
4936f63c | 78 | extern atomic_t irq_err_count; |
739735d5 | 79 | |
3ddc7e26 | 80 | #endif /* _M68K_IRQ_H_ */ |