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3ddc7e26 GU |
1 | #ifndef _M68K_IRQ_H_ |
2 | #define _M68K_IRQ_H_ | |
3 | ||
4 | /* | |
5 | * This should be the same as the max(NUM_X_SOURCES) for all the | |
6 | * different m68k hosts compiled into the kernel. | |
7 | * Currently the Atari has 72 and the Amiga 24, but if both are | |
8 | * supported in the kernel it is better to make room for 72. | |
736b24db MS |
9 | * With EtherNAT add-on card on Atari, the highest interrupt |
10 | * number is 140 so NR_IRQS needs to be 141. | |
3ddc7e26 GU |
11 | */ |
12 | #if defined(CONFIG_COLDFIRE) | |
13 | #define NR_IRQS 256 | |
14 | #elif defined(CONFIG_VME) || defined(CONFIG_SUN3) || defined(CONFIG_SUN3X) | |
15 | #define NR_IRQS 200 | |
736b24db MS |
16 | #elif defined(CONFIG_ATARI) |
17 | #define NR_IRQS 141 | |
18 | #elif defined(CONFIG_MAC) | |
3ddc7e26 GU |
19 | #define NR_IRQS 72 |
20 | #elif defined(CONFIG_Q40) | |
21 | #define NR_IRQS 43 | |
22 | #elif defined(CONFIG_AMIGA) || !defined(CONFIG_MMU) | |
23 | #define NR_IRQS 32 | |
24 | #elif defined(CONFIG_APOLLO) | |
25 | #define NR_IRQS 24 | |
26 | #elif defined(CONFIG_HP300) | |
27 | #define NR_IRQS 8 | |
49148020 | 28 | #else |
3ddc7e26 | 29 | #define NR_IRQS 0 |
49148020 | 30 | #endif |
3ddc7e26 | 31 | |
78ccdffc GU |
32 | #if defined(CONFIG_M68020) || defined(CONFIG_M68030) || \ |
33 | defined(CONFIG_M68040) || defined(CONFIG_M68060) | |
3ddc7e26 | 34 | |
3ddc7e26 GU |
35 | /* |
36 | * Interrupt source definitions | |
37 | * General interrupt sources are the level 1-7. | |
38 | * Adding an interrupt service routine for one of these sources | |
39 | * results in the addition of that routine to a chain of routines. | |
40 | * Each one is called in succession. Each individual interrupt | |
41 | * service routine should determine if the device associated with | |
42 | * that routine requires service. | |
43 | */ | |
44 | ||
45 | #define IRQ_SPURIOUS 0 | |
46 | ||
47 | #define IRQ_AUTO_1 1 /* level 1 interrupt */ | |
48 | #define IRQ_AUTO_2 2 /* level 2 interrupt */ | |
49 | #define IRQ_AUTO_3 3 /* level 3 interrupt */ | |
50 | #define IRQ_AUTO_4 4 /* level 4 interrupt */ | |
51 | #define IRQ_AUTO_5 5 /* level 5 interrupt */ | |
52 | #define IRQ_AUTO_6 6 /* level 6 interrupt */ | |
53 | #define IRQ_AUTO_7 7 /* level 7 interrupt (non-maskable) */ | |
54 | ||
55 | #define IRQ_USER 8 | |
56 | ||
4936f63c GU |
57 | struct irq_data; |
58 | struct irq_chip; | |
59 | struct irq_desc; | |
60 | extern unsigned int m68k_irq_startup(struct irq_data *data); | |
61 | extern unsigned int m68k_irq_startup_irq(unsigned int irq); | |
62 | extern void m68k_irq_shutdown(struct irq_data *data); | |
63 | extern void m68k_setup_auto_interrupt(void (*handler)(unsigned int, | |
64 | struct pt_regs *)); | |
f30a6484 | 65 | extern void m68k_setup_user_interrupt(unsigned int vec, unsigned int cnt); |
4936f63c | 66 | extern void m68k_setup_irq_controller(struct irq_chip *, |
bd0b9ac4 | 67 | void (*handle)(struct irq_desc *desc), |
4936f63c GU |
68 | unsigned int irq, unsigned int cnt); |
69 | ||
4936f63c GU |
70 | extern unsigned int irq_canonicalize(unsigned int irq); |
71 | ||
3ddc7e26 GU |
72 | #else |
73 | #define irq_canonicalize(irq) (irq) | |
78ccdffc | 74 | #endif /* !(CONFIG_M68020 || CONFIG_M68030 || CONFIG_M68040 || CONFIG_M68060) */ |
3ddc7e26 | 75 | |
739735d5 | 76 | asmlinkage void do_IRQ(int irq, struct pt_regs *regs); |
4936f63c | 77 | extern atomic_t irq_err_count; |
739735d5 | 78 | |
3ddc7e26 | 79 | #endif /* _M68K_IRQ_H_ */ |