[mirror_ubuntu-zesty-kernel.git] / arch / m68k / include / asm / m520xsim.h

/****************************************************************************/

/*
 *  m520xsim.h -- ColdFire 5207/5208 System Integration Module support.
 *
 *  (C) Copyright 2005, Intec Automation (mike@steroidmicros.com)
 */

/****************************************************************************/
#ifndef m520xsim_h
#define m520xsim_h
/****************************************************************************/

#define	CPU_NAME		"COLDFIRE(m520x)"
#define	CPU_INSTR_PER_JIFFY	3
#define	MCF_BUSCLK		(MCF_CLK / 2)

#include <asm/m52xxacr.h>

/*
 *  Define the 520x SIM register set addresses.
 */
#define MCFICM_INTC0        0xFC048000  /* Base for Interrupt Ctrl 0 */
#define MCFINTC_IPRH        0x00        /* Interrupt pending 32-63 */
#define MCFINTC_IPRL        0x04        /* Interrupt pending 1-31 */
#define MCFINTC_IMRH        0x08        /* Interrupt mask 32-63 */
#define MCFINTC_IMRL        0x0c        /* Interrupt mask 1-31 */
#define MCFINTC_INTFRCH     0x10        /* Interrupt force 32-63 */
#define MCFINTC_INTFRCL     0x14        /* Interrupt force 1-31 */
#define MCFINTC_SIMR        0x1c        /* Set interrupt mask 0-63 */
#define MCFINTC_CIMR        0x1d        /* Clear interrupt mask 0-63 */
#define MCFINTC_ICR0        0x40        /* Base ICR register */

/*
 *  The common interrupt controller code just wants to know the absolute
 *  address to the SIMR and CIMR registers (not offsets into IPSBAR).
 *  The 520x family only has a single INTC unit.
 */
#define MCFINTC0_SIMR       (MCFICM_INTC0 + MCFINTC_SIMR)
#define MCFINTC0_CIMR       (MCFICM_INTC0 + MCFINTC_CIMR)
#define	MCFINTC0_ICR0       (MCFICM_INTC0 + MCFINTC_ICR0)
#define MCFINTC1_SIMR       (0)
#define MCFINTC1_CIMR       (0)
#define	MCFINTC1_ICR0       (0)

#define MCFINT_VECBASE      64
#define MCFINT_UART0        26          /* Interrupt number for UART0 */
#define MCFINT_UART1        27          /* Interrupt number for UART1 */
#define MCFINT_UART2        28          /* Interrupt number for UART2 */
#define MCFINT_QSPI         31          /* Interrupt number for QSPI */
#define MCFINT_PIT1         4           /* Interrupt number for PIT1 (PIT0 in processor) */

/*
 *  SDRAM configuration registers.
 */
#define MCFSIM_SDMR         0xFC0a8000	/* SDRAM Mode/Extended Mode Register */
#define MCFSIM_SDCR         0xFC0a8004	/* SDRAM Control Register */
#define MCFSIM_SDCFG1       0xFC0a8008	/* SDRAM Configuration Register 1 */
#define MCFSIM_SDCFG2       0xFC0a800c	/* SDRAM Configuration Register 2 */
#define MCFSIM_SDCS0        0xFC0a8110	/* SDRAM Chip Select 0 Configuration */
#define MCFSIM_SDCS1        0xFC0a8114	/* SDRAM Chip Select 1 Configuration */

/*
 * EPORT and GPIO registers.
 */
#define MCFEPORT_EPPAR			0xFC088000
#define MCFEPORT_EPDDR			0xFC088002
#define MCFEPORT_EPIER			0xFC088003
#define MCFEPORT_EPDR			0xFC088004
#define MCFEPORT_EPPDR			0xFC088005
#define MCFEPORT_EPFR			0xFC088006

#define MCFGPIO_PODR_BUSCTL		0xFC0A4000
#define MCFGPIO_PODR_BE			0xFC0A4001
#define MCFGPIO_PODR_CS			0xFC0A4002
#define MCFGPIO_PODR_FECI2C		0xFC0A4003
#define MCFGPIO_PODR_QSPI		0xFC0A4004
#define MCFGPIO_PODR_TIMER		0xFC0A4005
#define MCFGPIO_PODR_UART		0xFC0A4006
#define MCFGPIO_PODR_FECH		0xFC0A4007
#define MCFGPIO_PODR_FECL		0xFC0A4008

#define MCFGPIO_PDDR_BUSCTL		0xFC0A400C
#define MCFGPIO_PDDR_BE			0xFC0A400D
#define MCFGPIO_PDDR_CS			0xFC0A400E
#define MCFGPIO_PDDR_FECI2C		0xFC0A400F
#define MCFGPIO_PDDR_QSPI		0xFC0A4010
#define MCFGPIO_PDDR_TIMER		0xFC0A4011
#define MCFGPIO_PDDR_UART		0xFC0A4012
#define MCFGPIO_PDDR_FECH		0xFC0A4013
#define MCFGPIO_PDDR_FECL		0xFC0A4014

#define MCFGPIO_PPDSDR_BUSCTL		0xFC0A401A
#define MCFGPIO_PPDSDR_BE		0xFC0A401B
#define MCFGPIO_PPDSDR_CS		0xFC0A401C
#define MCFGPIO_PPDSDR_FECI2C		0xFC0A401D
#define MCFGPIO_PPDSDR_QSPI		0xFC0A401E
#define MCFGPIO_PPDSDR_TIMER		0xFC0A401F
#define MCFGPIO_PPDSDR_UART		0xFC0A4021
#define MCFGPIO_PPDSDR_FECH		0xFC0A4021
#define MCFGPIO_PPDSDR_FECL		0xFC0A4022

#define MCFGPIO_PCLRR_BUSCTL		0xFC0A4024
#define MCFGPIO_PCLRR_BE		0xFC0A4025
#define MCFGPIO_PCLRR_CS		0xFC0A4026
#define MCFGPIO_PCLRR_FECI2C		0xFC0A4027
#define MCFGPIO_PCLRR_QSPI		0xFC0A4028
#define MCFGPIO_PCLRR_TIMER		0xFC0A4029
#define MCFGPIO_PCLRR_UART		0xFC0A402A
#define MCFGPIO_PCLRR_FECH		0xFC0A402B
#define MCFGPIO_PCLRR_FECL		0xFC0A402C

/*
 * Generic GPIO support
 */
#define MCFGPIO_PODR			MCFGPIO_PODR_BUSCTL
#define MCFGPIO_PDDR			MCFGPIO_PDDR_BUSCTL
#define MCFGPIO_PPDR			MCFGPIO_PPDSDR_BUSCTL
#define MCFGPIO_SETR			MCFGPIO_PPDSDR_BUSCTL
#define MCFGPIO_CLRR			MCFGPIO_PCLRR_BUSCTL

#define MCFGPIO_PIN_MAX			80
#define MCFGPIO_IRQ_MAX			8
#define MCFGPIO_IRQ_VECBASE		MCFINT_VECBASE

#define MCF_GPIO_PAR_UART		0xFC0A4036
#define MCF_GPIO_PAR_FECI2C		0xFC0A4033
#define MCF_GPIO_PAR_QSPI		0xFC0A4034
#define MCF_GPIO_PAR_FEC		0xFC0A4038

#define MCF_GPIO_PAR_UART_PAR_URXD0         (0x0001)
#define MCF_GPIO_PAR_UART_PAR_UTXD0         (0x0002)

#define MCF_GPIO_PAR_UART_PAR_URXD1         (0x0040)
#define MCF_GPIO_PAR_UART_PAR_UTXD1         (0x0080)

#define MCF_GPIO_PAR_FECI2C_PAR_SDA_URXD2   (0x02)
#define MCF_GPIO_PAR_FECI2C_PAR_SCL_UTXD2   (0x04)

/*
 *  PIT timer module.
 */
#define	MCFPIT_BASE1		0xFC080000	/* Base address of TIMER1 */
#define	MCFPIT_BASE2		0xFC084000	/* Base address of TIMER2 */

/*
 *  UART module.
 */
#define MCFUART_BASE1		0xFC060000	/* Base address of UART1 */
#define MCFUART_BASE2		0xFC064000	/* Base address of UART2 */
#define MCFUART_BASE3		0xFC068000	/* Base address of UART2 */

/*
 *  FEC module.
 */
#define	MCFFEC_BASE		0xFC030000	/* Base of FEC ethernet */
#define	MCFFEC_SIZE		0x800		/* Register set size */

/*
 *  Reset Control Unit.
 */
#define	MCF_RCR			0xFC0A0000
#define	MCF_RSR			0xFC0A0001

#define	MCF_RCR_SWRESET		0x80		/* Software reset bit */
#define	MCF_RCR_FRCSTOUT	0x40		/* Force external reset */

/****************************************************************************/
#endif  /* m520xsim_h */
Commit	Line	Data
7354b62c GU	1	/****************************************************************************/
	2
	3	/*
	4	* m520xsim.h -- ColdFire 5207/5208 System Integration Module support.
	5	*
	6	* (C) Copyright 2005, Intec Automation (mike@steroidmicros.com)
	7	*/
	8
	9	/****************************************************************************/
	10	#ifndef m520xsim_h
	11	#define m520xsim_h
	12	/****************************************************************************/
	13
733f31b7 GU	14	#define CPU_NAME "COLDFIRE(m520x)"
733f31b7 GU	15	#define CPU_INSTR_PER_JIFFY 3
ce3de78a	16	#define MCF_BUSCLK (MCF_CLK / 2)
7fc82b65	17
a12cf0a8 GU	18	#include <asm/m52xxacr.h>
a12cf0a8 GU	19
7354b62c	20	/*
277c5e3e	21	* Define the 520x SIM register set addresses.
7354b62c	22	*/
571f0608	23	#define MCFICM_INTC0 0xFC048000 /* Base for Interrupt Ctrl 0 */
7354b62c GU	24	#define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */
	25	#define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */
	26	#define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */
	27	#define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */
	28	#define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */
	29	#define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */
cd3dd406 GU	30	#define MCFINTC_SIMR 0x1c /* Set interrupt mask 0-63 */
cd3dd406 GU	31	#define MCFINTC_CIMR 0x1d /* Clear interrupt mask 0-63 */
7354b62c GU	32	#define MCFINTC_ICR0 0x40 /* Base ICR register */
7354b62c GU	33
277c5e3e GU	34	/*
	35	* The common interrupt controller code just wants to know the absolute
	36	* address to the SIMR and CIMR registers (not offsets into IPSBAR).
	37	* The 520x family only has a single INTC unit.
	38	*/
571f0608 GU	39	#define MCFINTC0_SIMR (MCFICM_INTC0 + MCFINTC_SIMR)
	40	#define MCFINTC0_CIMR (MCFICM_INTC0 + MCFINTC_CIMR)
	41	#define MCFINTC0_ICR0 (MCFICM_INTC0 + MCFINTC_ICR0)
277c5e3e GU	42	#define MCFINTC1_SIMR (0)
	43	#define MCFINTC1_CIMR (0)
	44	#define MCFINTC1_ICR0 (0)
	45
7354b62c GU	46	#define MCFINT_VECBASE 64
	47	#define MCFINT_UART0 26 /* Interrupt number for UART0 */
	48	#define MCFINT_UART1 27 /* Interrupt number for UART1 */
	49	#define MCFINT_UART2 28 /* Interrupt number for UART2 */
	50	#define MCFINT_QSPI 31 /* Interrupt number for QSPI */
	51	#define MCFINT_PIT1 4 /* Interrupt number for PIT1 (PIT0 in processor) */
	52
5a31be3f GU	53	/*
	54	* SDRAM configuration registers.
	55	*/
571f0608 GU	56	#define MCFSIM_SDMR 0xFC0a8000 /* SDRAM Mode/Extended Mode Register */
	57	#define MCFSIM_SDCR 0xFC0a8004 /* SDRAM Control Register */
	58	#define MCFSIM_SDCFG1 0xFC0a8008 /* SDRAM Configuration Register 1 */
	59	#define MCFSIM_SDCFG2 0xFC0a800c /* SDRAM Configuration Register 2 */
	60	#define MCFSIM_SDCS0 0xFC0a8110 /* SDRAM Chip Select 0 Configuration */
	61	#define MCFSIM_SDCS1 0xFC0a8114 /* SDRAM Chip Select 1 Configuration */
5a31be3f	62
a12cf0a8 GU	63	/*
	64	* EPORT and GPIO registers.
	65	*/
47e0c7e1	66	#define MCFEPORT_EPPAR 0xFC088000
afde8560	67	#define MCFEPORT_EPDDR 0xFC088002
47e0c7e1	68	#define MCFEPORT_EPIER 0xFC088003
afde8560	69	#define MCFEPORT_EPDR 0xFC088004
afde8560	70	#define MCFEPORT_EPPDR 0xFC088005
47e0c7e1	71	#define MCFEPORT_EPFR 0xFC088006
afde8560	72
	73	#define MCFGPIO_PODR_BUSCTL 0xFC0A4000
	74	#define MCFGPIO_PODR_BE 0xFC0A4001
	75	#define MCFGPIO_PODR_CS 0xFC0A4002
	76	#define MCFGPIO_PODR_FECI2C 0xFC0A4003
	77	#define MCFGPIO_PODR_QSPI 0xFC0A4004
	78	#define MCFGPIO_PODR_TIMER 0xFC0A4005
	79	#define MCFGPIO_PODR_UART 0xFC0A4006
	80	#define MCFGPIO_PODR_FECH 0xFC0A4007
	81	#define MCFGPIO_PODR_FECL 0xFC0A4008
	82
	83	#define MCFGPIO_PDDR_BUSCTL 0xFC0A400C
	84	#define MCFGPIO_PDDR_BE 0xFC0A400D
	85	#define MCFGPIO_PDDR_CS 0xFC0A400E
	86	#define MCFGPIO_PDDR_FECI2C 0xFC0A400F
	87	#define MCFGPIO_PDDR_QSPI 0xFC0A4010
	88	#define MCFGPIO_PDDR_TIMER 0xFC0A4011
	89	#define MCFGPIO_PDDR_UART 0xFC0A4012
	90	#define MCFGPIO_PDDR_FECH 0xFC0A4013
	91	#define MCFGPIO_PDDR_FECL 0xFC0A4014
	92
	93	#define MCFGPIO_PPDSDR_BUSCTL 0xFC0A401A
	94	#define MCFGPIO_PPDSDR_BE 0xFC0A401B
	95	#define MCFGPIO_PPDSDR_CS 0xFC0A401C
	96	#define MCFGPIO_PPDSDR_FECI2C 0xFC0A401D
	97	#define MCFGPIO_PPDSDR_QSPI 0xFC0A401E
	98	#define MCFGPIO_PPDSDR_TIMER 0xFC0A401F
	99	#define MCFGPIO_PPDSDR_UART 0xFC0A4021
	100	#define MCFGPIO_PPDSDR_FECH 0xFC0A4021
	101	#define MCFGPIO_PPDSDR_FECL 0xFC0A4022
	102
	103	#define MCFGPIO_PCLRR_BUSCTL 0xFC0A4024
	104	#define MCFGPIO_PCLRR_BE 0xFC0A4025
	105	#define MCFGPIO_PCLRR_CS 0xFC0A4026
	106	#define MCFGPIO_PCLRR_FECI2C 0xFC0A4027
	107	#define MCFGPIO_PCLRR_QSPI 0xFC0A4028
	108	#define MCFGPIO_PCLRR_TIMER 0xFC0A4029
	109	#define MCFGPIO_PCLRR_UART 0xFC0A402A
	110	#define MCFGPIO_PCLRR_FECH 0xFC0A402B
	111	#define MCFGPIO_PCLRR_FECL 0xFC0A402C
57015421	112
afde8560	113	/*
	114	* Generic GPIO support
	115	*/
	116	#define MCFGPIO_PODR MCFGPIO_PODR_BUSCTL
	117	#define MCFGPIO_PDDR MCFGPIO_PDDR_BUSCTL
	118	#define MCFGPIO_PPDR MCFGPIO_PPDSDR_BUSCTL
	119	#define MCFGPIO_SETR MCFGPIO_PPDSDR_BUSCTL
	120	#define MCFGPIO_CLRR MCFGPIO_PCLRR_BUSCTL
	121
	122	#define MCFGPIO_PIN_MAX 80
	123	#define MCFGPIO_IRQ_MAX 8
	124	#define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE
7354b62c	125
571f0608 GU	126	#define MCF_GPIO_PAR_UART 0xFC0A4036
	127	#define MCF_GPIO_PAR_FECI2C 0xFC0A4033
	128	#define MCF_GPIO_PAR_QSPI 0xFC0A4034
	129	#define MCF_GPIO_PAR_FEC 0xFC0A4038
7354b62c GU	130
	131	#define MCF_GPIO_PAR_UART_PAR_URXD0 (0x0001)
	132	#define MCF_GPIO_PAR_UART_PAR_UTXD0 (0x0002)
	133
	134	#define MCF_GPIO_PAR_UART_PAR_URXD1 (0x0040)
	135	#define MCF_GPIO_PAR_UART_PAR_UTXD1 (0x0080)
	136
	137	#define MCF_GPIO_PAR_FECI2C_PAR_SDA_URXD2 (0x02)
	138	#define MCF_GPIO_PAR_FECI2C_PAR_SCL_UTXD2 (0x04)
	139
f317c71a GU	140	/*
	141	* PIT timer module.
	142	*/
	143	#define MCFPIT_BASE1 0xFC080000 /* Base address of TIMER1 */
	144	#define MCFPIT_BASE2 0xFC084000 /* Base address of TIMER2 */
	145
57015421 GU	146	/*
	147	* UART module.
	148	*/
571f0608 GU	149	#define MCFUART_BASE1 0xFC060000 /* Base address of UART1 */
	150	#define MCFUART_BASE2 0xFC064000 /* Base address of UART2 */
	151	#define MCFUART_BASE3 0xFC068000 /* Base address of UART2 */
	152
	153	/*
	154	* FEC module.
	155	*/
	156	#define MCFFEC_BASE 0xFC030000 /* Base of FEC ethernet */
	157	#define MCFFEC_SIZE 0x800 /* Register set size */
57015421	158
25ce4a90	159	/*
25985edc	160	* Reset Control Unit.
25ce4a90 GU	161	*/
	162	#define MCF_RCR 0xFC0A0000
	163	#define MCF_RSR 0xFC0A0001
	164
	165	#define MCF_RCR_SWRESET 0x80 /* Software reset bit */
	166	#define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */
	167
7354b62c GU	168	/****************************************************************************/
7354b62c GU	169	#endif /* m520xsim_h */