[mirror_ubuntu-focal-kernel.git] / arch / m68k / include / asm / m523xsim.h

/****************************************************************************/

/*
 *	m523xsim.h -- ColdFire 523x System Integration Module support.
 *
 *	(C) Copyright 2003-2005, Greg Ungerer <gerg@snapgear.com>
 */

/****************************************************************************/
#ifndef	m523xsim_h
#define	m523xsim_h
/****************************************************************************/

#define	CPU_NAME		"COLDFIRE(m523x)"
#define	CPU_INSTR_PER_JIFFY	3

#include <asm/m52xxacr.h>

/*
 *	Define the 523x SIM register set addresses.
 */
#define	MCFICM_INTC0		0x0c00		/* Base for Interrupt Ctrl 0 */
#define	MCFICM_INTC1		0x0d00		/* Base for Interrupt Ctrl 0 */
#define	MCFINTC_IPRH		0x00		/* Interrupt pending 32-63 */
#define	MCFINTC_IPRL		0x04		/* Interrupt pending 1-31 */
#define	MCFINTC_IMRH		0x08		/* Interrupt mask 32-63 */
#define	MCFINTC_IMRL		0x0c		/* Interrupt mask 1-31 */
#define	MCFINTC_INTFRCH		0x10		/* Interrupt force 32-63 */
#define	MCFINTC_INTFRCL		0x14		/* Interrupt force 1-31 */
#define	MCFINTC_IRLR		0x18		/* */
#define	MCFINTC_IACKL		0x19		/* */
#define	MCFINTC_ICR0		0x40		/* Base ICR register */

#define	MCFINT_VECBASE		64		/* Vector base number */
#define	MCFINT_UART0		13		/* Interrupt number for UART0 */
#define	MCFINT_PIT1		36		/* Interrupt number for PIT1 */
#define MCFINT_QSPI		18		/* Interrupt number for QSPI */

/*
 *	SDRAM configuration registers.
 */
#define	MCFSIM_DCR		0x44		/* SDRAM control */
#define	MCFSIM_DACR0		0x48		/* SDRAM base address 0 */
#define	MCFSIM_DMR0		0x4c		/* SDRAM address mask 0 */
#define	MCFSIM_DACR1		0x50		/* SDRAM base address 1 */
#define	MCFSIM_DMR1		0x54		/* SDRAM address mask 1 */

/*
 *  Reset Controll Unit (relative to IPSBAR).
 */
#define	MCF_RCR			0x110000
#define	MCF_RSR			0x110001

#define	MCF_RCR_SWRESET		0x80		/* Software reset bit */
#define	MCF_RCR_FRCSTOUT	0x40		/* Force external reset */

/*
 *  UART module.
 */
#define MCFUART_BASE1		0x200           /* Base address of UART1 */
#define MCFUART_BASE2		0x240           /* Base address of UART2 */
#define MCFUART_BASE3		0x280           /* Base address of UART3 */

#define MCFGPIO_PODR_ADDR	(MCF_IPSBAR + 0x100000)
#define MCFGPIO_PODR_DATAH	(MCF_IPSBAR + 0x100001)
#define MCFGPIO_PODR_DATAL	(MCF_IPSBAR + 0x100002)
#define MCFGPIO_PODR_BUSCTL	(MCF_IPSBAR + 0x100003)
#define MCFGPIO_PODR_BS		(MCF_IPSBAR + 0x100004)
#define MCFGPIO_PODR_CS		(MCF_IPSBAR + 0x100005)
#define MCFGPIO_PODR_SDRAM	(MCF_IPSBAR + 0x100006)
#define MCFGPIO_PODR_FECI2C	(MCF_IPSBAR + 0x100007)
#define MCFGPIO_PODR_UARTH	(MCF_IPSBAR + 0x100008)
#define MCFGPIO_PODR_UARTL	(MCF_IPSBAR + 0x100009)
#define MCFGPIO_PODR_QSPI	(MCF_IPSBAR + 0x10000A)
#define MCFGPIO_PODR_TIMER	(MCF_IPSBAR + 0x10000B)
#define MCFGPIO_PODR_ETPU	(MCF_IPSBAR + 0x10000C)

#define MCFGPIO_PDDR_ADDR	(MCF_IPSBAR + 0x100010)
#define MCFGPIO_PDDR_DATAH	(MCF_IPSBAR + 0x100011)
#define MCFGPIO_PDDR_DATAL	(MCF_IPSBAR + 0x100012)
#define MCFGPIO_PDDR_BUSCTL	(MCF_IPSBAR + 0x100013)
#define MCFGPIO_PDDR_BS		(MCF_IPSBAR + 0x100014)
#define MCFGPIO_PDDR_CS		(MCF_IPSBAR + 0x100015)
#define MCFGPIO_PDDR_SDRAM	(MCF_IPSBAR + 0x100016)
#define MCFGPIO_PDDR_FECI2C	(MCF_IPSBAR + 0x100017)
#define MCFGPIO_PDDR_UARTH	(MCF_IPSBAR + 0x100018)
#define MCFGPIO_PDDR_UARTL	(MCF_IPSBAR + 0x100019)
#define MCFGPIO_PDDR_QSPI	(MCF_IPSBAR + 0x10001A)
#define MCFGPIO_PDDR_TIMER	(MCF_IPSBAR + 0x10001B)
#define MCFGPIO_PDDR_ETPU	(MCF_IPSBAR + 0x10001C)

#define MCFGPIO_PPDSDR_ADDR	(MCF_IPSBAR + 0x100020)
#define MCFGPIO_PPDSDR_DATAH	(MCF_IPSBAR + 0x100021)
#define MCFGPIO_PPDSDR_DATAL	(MCF_IPSBAR + 0x100022)
#define MCFGPIO_PPDSDR_BUSCTL	(MCF_IPSBAR + 0x100023)
#define MCFGPIO_PPDSDR_BS	(MCF_IPSBAR + 0x100024)
#define MCFGPIO_PPDSDR_CS	(MCF_IPSBAR + 0x100025)
#define MCFGPIO_PPDSDR_SDRAM	(MCF_IPSBAR + 0x100026)
#define MCFGPIO_PPDSDR_FECI2C	(MCF_IPSBAR + 0x100027)
#define MCFGPIO_PPDSDR_UARTH	(MCF_IPSBAR + 0x100028)
#define MCFGPIO_PPDSDR_UARTL	(MCF_IPSBAR + 0x100029)
#define MCFGPIO_PPDSDR_QSPI	(MCF_IPSBAR + 0x10002A)
#define MCFGPIO_PPDSDR_TIMER	(MCF_IPSBAR + 0x10002B)
#define MCFGPIO_PPDSDR_ETPU	(MCF_IPSBAR + 0x10002C)

#define MCFGPIO_PCLRR_ADDR	(MCF_IPSBAR + 0x100030)
#define MCFGPIO_PCLRR_DATAH	(MCF_IPSBAR + 0x100031)
#define MCFGPIO_PCLRR_DATAL	(MCF_IPSBAR + 0x100032)
#define MCFGPIO_PCLRR_BUSCTL	(MCF_IPSBAR + 0x100033)
#define MCFGPIO_PCLRR_BS	(MCF_IPSBAR + 0x100034)
#define MCFGPIO_PCLRR_CS	(MCF_IPSBAR + 0x100035)
#define MCFGPIO_PCLRR_SDRAM	(MCF_IPSBAR + 0x100036)
#define MCFGPIO_PCLRR_FECI2C	(MCF_IPSBAR + 0x100037)
#define MCFGPIO_PCLRR_UARTH	(MCF_IPSBAR + 0x100038)
#define MCFGPIO_PCLRR_UARTL	(MCF_IPSBAR + 0x100039)
#define MCFGPIO_PCLRR_QSPI	(MCF_IPSBAR + 0x10003A)
#define MCFGPIO_PCLRR_TIMER	(MCF_IPSBAR + 0x10003B)
#define MCFGPIO_PCLRR_ETPU	(MCF_IPSBAR + 0x10003C)

/*
 * EPort
 */

#define MCFEPORT_EPDDR		(MCF_IPSBAR + 0x130002)
#define MCFEPORT_EPDR		(MCF_IPSBAR + 0x130004)
#define MCFEPORT_EPPDR		(MCF_IPSBAR + 0x130005)

/*
 * Generic GPIO support
 */
#define MCFGPIO_PODR			MCFGPIO_PODR_ADDR
#define MCFGPIO_PDDR			MCFGPIO_PDDR_ADDR
#define MCFGPIO_PPDR			MCFGPIO_PPDSDR_ADDR
#define MCFGPIO_SETR			MCFGPIO_PPDSDR_ADDR
#define MCFGPIO_CLRR			MCFGPIO_PCLRR_ADDR

#define MCFGPIO_PIN_MAX			107
#define MCFGPIO_IRQ_MAX			8
#define MCFGPIO_IRQ_VECBASE		MCFINT_VECBASE

/*
 * Pin Assignment
*/
#define	MCFGPIO_PAR_QSPI	(MCF_IPSBAR + 0x10004A)
#define	MCFGPIO_PAR_TIMER	(MCF_IPSBAR + 0x10004C)
/****************************************************************************/
#endif	/* m523xsim_h */
Commit	Line	Data
910ce396 GU	1	/****************************************************************************/
	2
	3	/*
	4	* m523xsim.h -- ColdFire 523x System Integration Module support.
	5	*
	6	* (C) Copyright 2003-2005, Greg Ungerer <gerg@snapgear.com>
	7	*/
	8
	9	/****************************************************************************/
	10	#ifndef m523xsim_h
	11	#define m523xsim_h
	12	/****************************************************************************/
	13
733f31b7 GU	14	#define CPU_NAME "COLDFIRE(m523x)"
733f31b7 GU	15	#define CPU_INSTR_PER_JIFFY 3
910ce396	16
a12cf0a8 GU	17	#include <asm/m52xxacr.h>
a12cf0a8 GU	18
910ce396 GU	19	/*
	20	* Define the 523x SIM register set addresses.
	21	*/
	22	#define MCFICM_INTC0 0x0c00 /* Base for Interrupt Ctrl 0 */
	23	#define MCFICM_INTC1 0x0d00 /* Base for Interrupt Ctrl 0 */
	24	#define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */
	25	#define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */
	26	#define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */
	27	#define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */
	28	#define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */
	29	#define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */
	30	#define MCFINTC_IRLR 0x18 /* */
	31	#define MCFINTC_IACKL 0x19 /* */
	32	#define MCFINTC_ICR0 0x40 /* Base ICR register */
	33
	34	#define MCFINT_VECBASE 64 /* Vector base number */
	35	#define MCFINT_UART0 13 /* Interrupt number for UART0 */
	36	#define MCFINT_PIT1 36 /* Interrupt number for PIT1 */
	37	#define MCFINT_QSPI 18 /* Interrupt number for QSPI */
	38
	39	/*
	40	* SDRAM configuration registers.
	41	*/
	42	#define MCFSIM_DCR 0x44 /* SDRAM control */
	43	#define MCFSIM_DACR0 0x48 /* SDRAM base address 0 */
	44	#define MCFSIM_DMR0 0x4c /* SDRAM address mask 0 */
	45	#define MCFSIM_DACR1 0x50 /* SDRAM base address 1 */
	46	#define MCFSIM_DMR1 0x54 /* SDRAM address mask 1 */
	47
55b33f31 GU	48	/*
	49	* Reset Controll Unit (relative to IPSBAR).
	50	*/
	51	#define MCF_RCR 0x110000
	52	#define MCF_RSR 0x110001
	53
	54	#define MCF_RCR_SWRESET 0x80 /* Software reset bit */
	55	#define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */
	56
57015421 GU	57	/*
	58	* UART module.
	59	*/
	60	#define MCFUART_BASE1 0x200 /* Base address of UART1 */
	61	#define MCFUART_BASE2 0x240 /* Base address of UART2 */
	62	#define MCFUART_BASE3 0x280 /* Base address of UART3 */
	63
a03ce7d9	64	#define MCFGPIO_PODR_ADDR (MCF_IPSBAR + 0x100000)
	65	#define MCFGPIO_PODR_DATAH (MCF_IPSBAR + 0x100001)
	66	#define MCFGPIO_PODR_DATAL (MCF_IPSBAR + 0x100002)
	67	#define MCFGPIO_PODR_BUSCTL (MCF_IPSBAR + 0x100003)
	68	#define MCFGPIO_PODR_BS (MCF_IPSBAR + 0x100004)
	69	#define MCFGPIO_PODR_CS (MCF_IPSBAR + 0x100005)
	70	#define MCFGPIO_PODR_SDRAM (MCF_IPSBAR + 0x100006)
	71	#define MCFGPIO_PODR_FECI2C (MCF_IPSBAR + 0x100007)
	72	#define MCFGPIO_PODR_UARTH (MCF_IPSBAR + 0x100008)
	73	#define MCFGPIO_PODR_UARTL (MCF_IPSBAR + 0x100009)
	74	#define MCFGPIO_PODR_QSPI (MCF_IPSBAR + 0x10000A)
	75	#define MCFGPIO_PODR_TIMER (MCF_IPSBAR + 0x10000B)
	76	#define MCFGPIO_PODR_ETPU (MCF_IPSBAR + 0x10000C)
	77
	78	#define MCFGPIO_PDDR_ADDR (MCF_IPSBAR + 0x100010)
	79	#define MCFGPIO_PDDR_DATAH (MCF_IPSBAR + 0x100011)
	80	#define MCFGPIO_PDDR_DATAL (MCF_IPSBAR + 0x100012)
	81	#define MCFGPIO_PDDR_BUSCTL (MCF_IPSBAR + 0x100013)
	82	#define MCFGPIO_PDDR_BS (MCF_IPSBAR + 0x100014)
	83	#define MCFGPIO_PDDR_CS (MCF_IPSBAR + 0x100015)
	84	#define MCFGPIO_PDDR_SDRAM (MCF_IPSBAR + 0x100016)
	85	#define MCFGPIO_PDDR_FECI2C (MCF_IPSBAR + 0x100017)
	86	#define MCFGPIO_PDDR_UARTH (MCF_IPSBAR + 0x100018)
	87	#define MCFGPIO_PDDR_UARTL (MCF_IPSBAR + 0x100019)
	88	#define MCFGPIO_PDDR_QSPI (MCF_IPSBAR + 0x10001A)
	89	#define MCFGPIO_PDDR_TIMER (MCF_IPSBAR + 0x10001B)
	90	#define MCFGPIO_PDDR_ETPU (MCF_IPSBAR + 0x10001C)
	91
	92	#define MCFGPIO_PPDSDR_ADDR (MCF_IPSBAR + 0x100020)
	93	#define MCFGPIO_PPDSDR_DATAH (MCF_IPSBAR + 0x100021)
	94	#define MCFGPIO_PPDSDR_DATAL (MCF_IPSBAR + 0x100022)
	95	#define MCFGPIO_PPDSDR_BUSCTL (MCF_IPSBAR + 0x100023)
	96	#define MCFGPIO_PPDSDR_BS (MCF_IPSBAR + 0x100024)
	97	#define MCFGPIO_PPDSDR_CS (MCF_IPSBAR + 0x100025)
	98	#define MCFGPIO_PPDSDR_SDRAM (MCF_IPSBAR + 0x100026)
	99	#define MCFGPIO_PPDSDR_FECI2C (MCF_IPSBAR + 0x100027)
	100	#define MCFGPIO_PPDSDR_UARTH (MCF_IPSBAR + 0x100028)
	101	#define MCFGPIO_PPDSDR_UARTL (MCF_IPSBAR + 0x100029)
	102	#define MCFGPIO_PPDSDR_QSPI (MCF_IPSBAR + 0x10002A)
	103	#define MCFGPIO_PPDSDR_TIMER (MCF_IPSBAR + 0x10002B)
	104	#define MCFGPIO_PPDSDR_ETPU (MCF_IPSBAR + 0x10002C)
	105
	106	#define MCFGPIO_PCLRR_ADDR (MCF_IPSBAR + 0x100030)
	107	#define MCFGPIO_PCLRR_DATAH (MCF_IPSBAR + 0x100031)
	108	#define MCFGPIO_PCLRR_DATAL (MCF_IPSBAR + 0x100032)
	109	#define MCFGPIO_PCLRR_BUSCTL (MCF_IPSBAR + 0x100033)
	110	#define MCFGPIO_PCLRR_BS (MCF_IPSBAR + 0x100034)
	111	#define MCFGPIO_PCLRR_CS (MCF_IPSBAR + 0x100035)
	112	#define MCFGPIO_PCLRR_SDRAM (MCF_IPSBAR + 0x100036)
	113	#define MCFGPIO_PCLRR_FECI2C (MCF_IPSBAR + 0x100037)
	114	#define MCFGPIO_PCLRR_UARTH (MCF_IPSBAR + 0x100038)
	115	#define MCFGPIO_PCLRR_UARTL (MCF_IPSBAR + 0x100039)
	116	#define MCFGPIO_PCLRR_QSPI (MCF_IPSBAR + 0x10003A)
	117	#define MCFGPIO_PCLRR_TIMER (MCF_IPSBAR + 0x10003B)
	118	#define MCFGPIO_PCLRR_ETPU (MCF_IPSBAR + 0x10003C)
	119
	120	/*
	121	* EPort
	122	*/
	123
	124	#define MCFEPORT_EPDDR (MCF_IPSBAR + 0x130002)
	125	#define MCFEPORT_EPDR (MCF_IPSBAR + 0x130004)
	126	#define MCFEPORT_EPPDR (MCF_IPSBAR + 0x130005)
	127
128	/*
129	* Generic GPIO support
130	*/
131	#define MCFGPIO_PODR MCFGPIO_PODR_ADDR
132	#define MCFGPIO_PDDR MCFGPIO_PDDR_ADDR
133	#define MCFGPIO_PPDR MCFGPIO_PPDSDR_ADDR
134	#define MCFGPIO_SETR MCFGPIO_PPDSDR_ADDR
135	#define MCFGPIO_CLRR MCFGPIO_PCLRR_ADDR
136
137	#define MCFGPIO_PIN_MAX 107
138	#define MCFGPIO_IRQ_MAX 8
139	#define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE
140
91d60417 SK	141	/*
	142	* Pin Assignment
	143	*/
	144	#define MCFGPIO_PAR_QSPI (MCF_IPSBAR + 0x10004A)
	145	#define MCFGPIO_PAR_TIMER (MCF_IPSBAR + 0x10004C)
910ce396 GU	146	/****************************************************************************/
910ce396 GU	147	#endif /* m523xsim_h */