projects / mirror_ubuntu-bionic-kernel.git / blame
| Commit | Line | Data |
|---|---|---|
| b2441318 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
| bea8bcb1 SK |
2 | /* |
| 3 | * m5441xsim.h -- Coldfire 5441x register definitions | |
| 4 | * | |
| 5 | * (C) Copyright 2012, Steven King <sfking@fdwdc.com> | |
| 6 | */ | |
| 7 | ||
| 8 | #ifndef m5441xsim_h | |
| 9 | #define m5441xsim_h | |
| 10 | ||
| 11 | #define CPU_NAME "COLDFIRE(m5441x)" | |
| 12 | #define CPU_INSTR_PER_JIFFY 2 | |
| 13 | #define MCF_BUSCLK (MCF_CLK / 2) | |
| 81d33350 | 14 | #define MACHINE MACH_M5441X |
| cbd5b982 | 15 | #define FPUTYPE 0 |
| 8cf4a973 GU |
16 | #define IOMEMBASE 0xe0000000 |
| 17 | #define IOMEMSIZE 0x20000000 | |
| bea8bcb1 SK |
18 | |
| 19 | #include <asm/m54xxacr.h> | |
| 20 | ||
| 21 | /* | |
| 22 | * Reset Controller Module. | |
| 23 | */ | |
| 24 | ||
| 25 | #define MCF_RCR 0xec090000 | |
| 26 | #define MCF_RSR 0xec090001 | |
| 27 | ||
| 28 | #define MCF_RCR_SWRESET 0x80 /* Software reset bit */ | |
| 29 | #define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */ | |
| 30 | ||
| 31 | /* | |
| 32 | * Interrupt Controller Modules. | |
| 33 | */ | |
| 34 | /* the 5441x have 3 interrupt controllers, each control 64 interrupts */ | |
| 35 | #define MCFINT_VECBASE 64 | |
| 36 | #define MCFINT0_VECBASE MCFINT_VECBASE | |
| 37 | #define MCFINT1_VECBASE (MCFINT0_VECBASE + 64) | |
| 38 | #define MCFINT2_VECBASE (MCFINT1_VECBASE + 64) | |
| 39 | ||
| 40 | /* interrupt controller 0 */ | |
| 41 | #define MCFINTC0_SIMR 0xfc04801c | |
| 42 | #define MCFINTC0_CIMR 0xfc04801d | |
| 43 | #define MCFINTC0_ICR0 0xfc048040 | |
| 44 | /* interrupt controller 1 */ | |
| 45 | #define MCFINTC1_SIMR 0xfc04c01c | |
| 46 | #define MCFINTC1_CIMR 0xfc04c01d | |
| 47 | #define MCFINTC1_ICR0 0xfc04c040 | |
| 48 | /* interrupt controller 2 */ | |
| 49 | #define MCFINTC2_SIMR 0xfc05001c | |
| 50 | #define MCFINTC2_CIMR 0xfc05001d | |
| 51 | #define MCFINTC2_ICR0 0xfc050040 | |
| 52 | ||
| 53 | /* on interrupt controller 0 */ | |
| 54 | #define MCFINT0_EPORT0 1 | |
| 55 | #define MCFINT0_UART0 26 | |
| 56 | #define MCFINT0_UART1 27 | |
| 57 | #define MCFINT0_UART2 28 | |
| 58 | #define MCFINT0_UART3 29 | |
| 59 | #define MCFINT0_I2C0 30 | |
| 60 | #define MCFINT0_DSPI0 31 | |
| 61 | ||
| 62 | #define MCFINT0_TIMER0 32 | |
| 63 | #define MCFINT0_TIMER1 33 | |
| 64 | #define MCFINT0_TIMER2 34 | |
| 65 | #define MCFINT0_TIMER3 35 | |
| 66 | ||
| 67 | #define MCFINT0_FECRX0 36 | |
| 68 | #define MCFINT0_FECTX0 40 | |
| 69 | #define MCFINT0_FECENTC0 42 | |
| 70 | ||
| 71 | #define MCFINT0_FECRX1 49 | |
| 72 | #define MCFINT0_FECTX1 53 | |
| 73 | #define MCFINT0_FECENTC1 55 | |
| 74 | ||
| 75 | /* on interrupt controller 1 */ | |
| 76 | #define MCFINT1_UART4 48 | |
| 77 | #define MCFINT1_UART5 49 | |
| 78 | #define MCFINT1_UART6 50 | |
| 79 | #define MCFINT1_UART7 51 | |
| 80 | #define MCFINT1_UART8 52 | |
| 81 | #define MCFINT1_UART9 53 | |
| 82 | #define MCFINT1_DSPI1 54 | |
| 83 | #define MCFINT1_DSPI2 55 | |
| 84 | #define MCFINT1_DSPI3 56 | |
| 85 | #define MCFINT1_I2C1 57 | |
| 86 | #define MCFINT1_I2C2 58 | |
| 87 | #define MCFINT1_I2C3 59 | |
| 88 | #define MCFINT1_I2C4 60 | |
| 89 | #define MCFINT1_I2C5 61 | |
| 90 | ||
| 91 | /* on interrupt controller 2 */ | |
| 92 | #define MCFINT2_PIT0 13 | |
| 93 | #define MCFINT2_PIT1 14 | |
| 94 | #define MCFINT2_PIT2 15 | |
| 95 | #define MCFINT2_PIT3 16 | |
| 96 | #define MCFINT2_RTC 26 | |
| 97 | ||
| 98 | /* | |
| 99 | * PIT timer module. | |
| 100 | */ | |
| 101 | #define MCFPIT_BASE0 0xFC080000 /* Base address of TIMER0 */ | |
| 102 | #define MCFPIT_BASE1 0xFC084000 /* Base address of TIMER1 */ | |
| 103 | #define MCFPIT_BASE2 0xFC088000 /* Base address of TIMER2 */ | |
| 104 | #define MCFPIT_BASE3 0xFC08C000 /* Base address of TIMER3 */ | |
| 105 | ||
| 106 | ||
| 107 | #define MCF_IRQ_PIT1 (MCFINT2_VECBASE + MCFINT2_PIT1) | |
| 108 | ||
| 109 | /* | |
| 110 | * Power Management | |
| 111 | */ | |
| 112 | #define MCFPM_WCR 0xfc040013 | |
| 113 | #define MCFPM_PPMSR0 0xfc04002c | |
| 114 | #define MCFPM_PPMCR0 0xfc04002d | |
| 115 | #define MCFPM_PPMSR1 0xfc04002e | |
| 116 | #define MCFPM_PPMCR1 0xfc04002f | |
| 117 | #define MCFPM_PPMHR0 0xfc040030 | |
| 118 | #define MCFPM_PPMLR0 0xfc040034 | |
| 119 | #define MCFPM_PPMHR1 0xfc040038 | |
| 120 | #define MCFPM_PPMLR1 0xfc04003c | |
| 121 | #define MCFPM_LPCR 0xec090007 | |
| 122 | /* | |
| 123 | * UART module. | |
| 124 | */ | |
| 125 | #define MCFUART_BASE0 0xfc060000 /* Base address of UART0 */ | |
| 126 | #define MCFUART_BASE1 0xfc064000 /* Base address of UART1 */ | |
| 127 | #define MCFUART_BASE2 0xfc068000 /* Base address of UART2 */ | |
| 128 | #define MCFUART_BASE3 0xfc06c000 /* Base address of UART3 */ | |
| 129 | #define MCFUART_BASE4 0xec060000 /* Base address of UART4 */ | |
| 130 | #define MCFUART_BASE5 0xec064000 /* Base address of UART5 */ | |
| 131 | #define MCFUART_BASE6 0xec068000 /* Base address of UART6 */ | |
| 132 | #define MCFUART_BASE7 0xec06c000 /* Base address of UART7 */ | |
| 133 | #define MCFUART_BASE8 0xec070000 /* Base address of UART8 */ | |
| 134 | #define MCFUART_BASE9 0xec074000 /* Base address of UART9 */ | |
| 135 | ||
| 136 | #define MCF_IRQ_UART0 (MCFINT0_VECBASE + MCFINT0_UART0) | |
| 137 | #define MCF_IRQ_UART1 (MCFINT0_VECBASE + MCFINT0_UART1) | |
| 138 | #define MCF_IRQ_UART2 (MCFINT0_VECBASE + MCFINT0_UART2) | |
| 139 | #define MCF_IRQ_UART3 (MCFINT0_VECBASE + MCFINT0_UART3) | |
| 140 | #define MCF_IRQ_UART4 (MCFINT1_VECBASE + MCFINT1_UART4) | |
| 141 | #define MCF_IRQ_UART5 (MCFINT1_VECBASE + MCFINT1_UART5) | |
| 142 | #define MCF_IRQ_UART6 (MCFINT1_VECBASE + MCFINT1_UART6) | |
| 143 | #define MCF_IRQ_UART7 (MCFINT1_VECBASE + MCFINT1_UART7) | |
| 144 | #define MCF_IRQ_UART8 (MCFINT1_VECBASE + MCFINT1_UART8) | |
| 145 | #define MCF_IRQ_UART9 (MCFINT1_VECBASE + MCFINT1_UART9) | |
| 146 | /* | |
| 147 | * FEC modules. | |
| 148 | */ | |
| 149 | #define MCFFEC_BASE0 0xfc0d4000 | |
| 150 | #define MCFFEC_SIZE0 0x800 | |
| 151 | #define MCF_IRQ_FECRX0 (MCFINT0_VECBASE + MCFINT0_FECRX0) | |
| 152 | #define MCF_IRQ_FECTX0 (MCFINT0_VECBASE + MCFINT0_FECTX0) | |
| 153 | #define MCF_IRQ_FECENTC0 (MCFINT0_VECBASE + MCFINT0_FECENTC0) | |
| 154 | ||
| 155 | #define MCFFEC_BASE1 0xfc0d8000 | |
| 156 | #define MCFFEC_SIZE1 0x800 | |
| 157 | #define MCF_IRQ_FECRX1 (MCFINT0_VECBASE + MCFINT0_FECRX1) | |
| 158 | #define MCF_IRQ_FECTX1 (MCFINT0_VECBASE + MCFINT0_FECTX1) | |
| 159 | #define MCF_IRQ_FECENTC1 (MCFINT0_VECBASE + MCFINT0_FECENTC1) | |
| 160 | /* | |
| 161 | * I2C modules. | |
| 162 | */ | |
| 163 | #define MCFI2C_BASE0 0xfc058000 | |
| 164 | #define MCFI2C_SIZE0 0x20 | |
| 165 | #define MCFI2C_BASE1 0xfc038000 | |
| 166 | #define MCFI2C_SIZE1 0x20 | |
| 167 | #define MCFI2C_BASE2 0xec010000 | |
| 168 | #define MCFI2C_SIZE2 0x20 | |
| 169 | #define MCFI2C_BASE3 0xec014000 | |
| 170 | #define MCFI2C_SIZE3 0x20 | |
| 171 | #define MCFI2C_BASE4 0xec018000 | |
| 172 | #define MCFI2C_SIZE4 0x20 | |
| 173 | #define MCFI2C_BASE5 0xec01c000 | |
| 174 | #define MCFI2C_SIZE5 0x20 | |
| 175 | ||
| 176 | #define MCF_IRQ_I2C0 (MCFINT0_VECBASE + MCFINT0_I2C0) | |
| 177 | #define MCF_IRQ_I2C1 (MCFINT1_VECBASE + MCFINT1_I2C1) | |
| 178 | #define MCF_IRQ_I2C2 (MCFINT1_VECBASE + MCFINT1_I2C2) | |
| 179 | #define MCF_IRQ_I2C3 (MCFINT1_VECBASE + MCFINT1_I2C3) | |
| 180 | #define MCF_IRQ_I2C4 (MCFINT1_VECBASE + MCFINT1_I2C4) | |
| 181 | #define MCF_IRQ_I2C5 (MCFINT1_VECBASE + MCFINT1_I2C5) | |
| 182 | /* | |
| 183 | * EPORT Module. | |
| 184 | */ | |
| 185 | #define MCFEPORT_EPPAR 0xfc090000 | |
| 186 | #define MCFEPORT_EPIER 0xfc090003 | |
| 187 | #define MCFEPORT_EPFR 0xfc090006 | |
| c785a3d7 SK |
188 | /* |
| 189 | * RTC Module. | |
| 190 | */ | |
| 191 | #define MCFRTC_BASE 0xfc0a8000 | |
| 192 | #define MCFRTC_SIZE (0xfc0a8840 - 0xfc0a8000) | |
| 193 | #define MCF_IRQ_RTC (MCFINT2_VECBASE + MCFINT2_RTC) | |
| bea8bcb1 SK |
194 | |
| 195 | /* | |
| 196 | * GPIO Module. | |
| 197 | */ | |
| 198 | #define MCFGPIO_PODR_A 0xec094000 | |
| 199 | #define MCFGPIO_PODR_B 0xec094001 | |
| 200 | #define MCFGPIO_PODR_C 0xec094002 | |
| 201 | #define MCFGPIO_PODR_D 0xec094003 | |
| 202 | #define MCFGPIO_PODR_E 0xec094004 | |
| 203 | #define MCFGPIO_PODR_F 0xec094005 | |
| 204 | #define MCFGPIO_PODR_G 0xec094006 | |
| 205 | #define MCFGPIO_PODR_H 0xec094007 | |
| 206 | #define MCFGPIO_PODR_I 0xec094008 | |
| 207 | #define MCFGPIO_PODR_J 0xec094009 | |
| 208 | #define MCFGPIO_PODR_K 0xec09400a | |
| 209 | ||
| 210 | #define MCFGPIO_PDDR_A 0xec09400c | |
| 211 | #define MCFGPIO_PDDR_B 0xec09400d | |
| 212 | #define MCFGPIO_PDDR_C 0xec09400e | |
| 213 | #define MCFGPIO_PDDR_D 0xec09400f | |
| 214 | #define MCFGPIO_PDDR_E 0xec094010 | |
| 215 | #define MCFGPIO_PDDR_F 0xec094011 | |
| 216 | #define MCFGPIO_PDDR_G 0xec094012 | |
| 217 | #define MCFGPIO_PDDR_H 0xec094013 | |
| 218 | #define MCFGPIO_PDDR_I 0xec094014 | |
| 219 | #define MCFGPIO_PDDR_J 0xec094015 | |
| 220 | #define MCFGPIO_PDDR_K 0xec094016 | |
| 221 | ||
| 222 | #define MCFGPIO_PPDSDR_A 0xec094018 | |
| 223 | #define MCFGPIO_PPDSDR_B 0xec094019 | |
| 224 | #define MCFGPIO_PPDSDR_C 0xec09401a | |
| 225 | #define MCFGPIO_PPDSDR_D 0xec09401b | |
| 226 | #define MCFGPIO_PPDSDR_E 0xec09401c | |
| 227 | #define MCFGPIO_PPDSDR_F 0xec09401d | |
| 228 | #define MCFGPIO_PPDSDR_G 0xec09401e | |
| 229 | #define MCFGPIO_PPDSDR_H 0xec09401f | |
| 230 | #define MCFGPIO_PPDSDR_I 0xec094020 | |
| 231 | #define MCFGPIO_PPDSDR_J 0xec094021 | |
| 232 | #define MCFGPIO_PPDSDR_K 0xec094022 | |
| 233 | ||
| 234 | #define MCFGPIO_PCLRR_A 0xec094024 | |
| 235 | #define MCFGPIO_PCLRR_B 0xec094025 | |
| 236 | #define MCFGPIO_PCLRR_C 0xec094026 | |
| 237 | #define MCFGPIO_PCLRR_D 0xec094027 | |
| 238 | #define MCFGPIO_PCLRR_E 0xec094028 | |
| 239 | #define MCFGPIO_PCLRR_F 0xec094029 | |
| 240 | #define MCFGPIO_PCLRR_G 0xec09402a | |
| 241 | #define MCFGPIO_PCLRR_H 0xec09402b | |
| 242 | #define MCFGPIO_PCLRR_I 0xec09402c | |
| 243 | #define MCFGPIO_PCLRR_J 0xec09402d | |
| 244 | #define MCFGPIO_PCLRR_K 0xec09402e | |
| 245 | ||
| 246 | #define MCFGPIO_PAR_FBCTL 0xec094048 | |
| 247 | #define MCFGPIO_PAR_BE 0xec094049 | |
| 248 | #define MCFGPIO_PAR_CS 0xec09404a | |
| 249 | #define MCFGPIO_PAR_CANI2C 0xec09404b | |
| 250 | #define MCFGPIO_PAR_IRQ0H 0xec09404c | |
| 251 | #define MCFGPIO_PAR_IRQ0L 0xec09404d | |
| 252 | #define MCFGPIO_PAR_DSPIOWH 0xec09404e | |
| 253 | #define MCFGPIO_PAR_DSPIOWL 0xec09404f | |
| 254 | #define MCFGPIO_PAR_TIMER 0xec094050 | |
| 255 | #define MCFGPIO_PAR_UART2 0xec094051 | |
| 256 | #define MCFGPIO_PAR_UART1 0xec094052 | |
| 257 | #define MCFGPIO_PAR_UART0 0xec094053 | |
| 258 | #define MCFGPIO_PAR_SDHCH 0xec094054 | |
| 259 | #define MCFGPIO_PAR_SDHCL 0xec094055 | |
| 260 | #define MCFGPIO_PAR_SIMP0H 0xec094056 | |
| 261 | #define MCFGPIO_PAR_SIMP0L 0xec094057 | |
| 262 | #define MCFGPIO_PAR_SSI0H 0xec094058 | |
| 263 | #define MCFGPIO_PAR_SSI0L 0xec094059 | |
| 264 | #define MCFGPIO_PAR_DEBUGH1 0xec09405a | |
| 265 | #define MCFGPIO_PAR_DEBUGH0 0xec09405b | |
| 266 | #define MCFGPIO_PAR_DEBUGl 0xec09405c | |
| 267 | #define MCFGPIO_PAR_FEC 0xec09405e | |
| 268 | ||
| 269 | /* generalization for generic gpio support */ | |
| 270 | #define MCFGPIO_PODR MCFGPIO_PODR_A | |
| 271 | #define MCFGPIO_PDDR MCFGPIO_PDDR_A | |
| 272 | #define MCFGPIO_PPDR MCFGPIO_PPDSDR_A | |
| 273 | #define MCFGPIO_SETR MCFGPIO_PPDSDR_A | |
| 274 | #define MCFGPIO_CLRR MCFGPIO_PCLRR_A | |
| 275 | ||
| 276 | #define MCFGPIO_IRQ_MIN 17 | |
| 277 | #define MCFGPIO_IRQ_MAX 24 | |
| 278 | #define MCFGPIO_IRQ_VECBASE (MCFINT_VECBASE - MCFGPIO_IRQ_MIN) | |
| 279 | #define MCFGPIO_PIN_MAX 87 | |
| 280 | ||
| 281 | #endif /* m5441xsim_h */ |