[mirror_ubuntu-bionic-kernel.git] / arch / m68k / include / asm / mcfslt.h

/****************************************************************************/

/*
 *	mcfslt.h -- ColdFire internal Slice (SLT) timer support defines.
 *
 *	(C) Copyright 2004, Greg Ungerer (gerg@snapgear.com)
 *	(C) Copyright 2009, Philippe De Muyter (phdm@macqel.be)
 */

/****************************************************************************/
#ifndef mcfslt_h
#define mcfslt_h
/****************************************************************************/

/*
 *	Define the SLT timer register set addresses.
 */
#define MCFSLT_STCNT		0x00	/* Terminal count */
#define MCFSLT_SCR		0x04	/* Control */
#define MCFSLT_SCNT		0x08	/* Current count */
#define MCFSLT_SSR		0x0C	/* Status */

/*
 *	Bit definitions for the SCR control register.
 */
#define MCFSLT_SCR_RUN		0x04000000	/* Run mode (continuous) */
#define MCFSLT_SCR_IEN		0x02000000	/* Interrupt enable */
#define MCFSLT_SCR_TEN		0x01000000	/* Timer enable */

/*
 *	Bit definitions for the SSR status register.
 */
#define MCFSLT_SSR_BE		0x02000000	/* Bus error condition */
#define MCFSLT_SSR_TE		0x01000000	/* Timeout condition */

/****************************************************************************/
#endif	/* mcfslt_h */
Commit	Line	Data
ea49f8ff PDM	1	/****************************************************************************/
	2
	3	/*
	4	* mcfslt.h -- ColdFire internal Slice (SLT) timer support defines.
	5	*
	6	* (C) Copyright 2004, Greg Ungerer (gerg@snapgear.com)
	7	* (C) Copyright 2009, Philippe De Muyter (phdm@macqel.be)
	8	*/
	9
	10	/****************************************************************************/
	11	#ifndef mcfslt_h
	12	#define mcfslt_h
	13	/****************************************************************************/
	14
ea49f8ff PDM	15	/*
	16	* Define the SLT timer register set addresses.
	17	*/
	18	#define MCFSLT_STCNT 0x00 /* Terminal count */
	19	#define MCFSLT_SCR 0x04 /* Control */
	20	#define MCFSLT_SCNT 0x08 /* Current count */
	21	#define MCFSLT_SSR 0x0C /* Status */
	22
	23	/*
	24	* Bit definitions for the SCR control register.
	25	*/
	26	#define MCFSLT_SCR_RUN 0x04000000 /* Run mode (continuous) */
	27	#define MCFSLT_SCR_IEN 0x02000000 /* Interrupt enable */
	28	#define MCFSLT_SCR_TEN 0x01000000 /* Timer enable */
	29
	30	/*
	31	* Bit definitions for the SSR status register.
	32	*/
	33	#define MCFSLT_SSR_BE 0x02000000 /* Bus error condition */
	34	#define MCFSLT_SSR_TE 0x01000000 /* Timeout condition */
	35
	36	/****************************************************************************/
	37	#endif /* mcfslt_h */