[mirror_ubuntu-kernels.git] / arch / m68k / include / asm / mcfuart.h

/* SPDX-License-Identifier: GPL-2.0 */
/****************************************************************************/

/*
 *	mcfuart.h -- ColdFire internal UART support defines.
 *
 *	(C) Copyright 1999-2003, Greg Ungerer (gerg@snapgear.com)
 * 	(C) Copyright 2000, Lineo Inc. (www.lineo.com) 
 */

/****************************************************************************/
#ifndef	mcfuart_h
#define	mcfuart_h
/****************************************************************************/

#include <linux/serial_core.h>
#include <linux/platform_device.h>

struct mcf_platform_uart {
	unsigned long	mapbase;	/* Physical address base */
	void __iomem	*membase;	/* Virtual address if mapped */
	unsigned int	irq;		/* Interrupt vector */
	unsigned int	uartclk;	/* UART clock rate */
};

/*
 *	Define the ColdFire UART register set addresses.
 */
#define	MCFUART_UMR		0x00		/* Mode register (r/w) */
#define	MCFUART_USR		0x04		/* Status register (r) */
#define	MCFUART_UCSR		0x04		/* Clock Select (w) */
#define	MCFUART_UCR		0x08		/* Command register (w) */
#define	MCFUART_URB		0x0c		/* Receiver Buffer (r) */
#define	MCFUART_UTB		0x0c		/* Transmit Buffer (w) */
#define	MCFUART_UIPCR		0x10		/* Input Port Change (r) */
#define	MCFUART_UACR		0x10		/* Auxiliary Control (w) */
#define	MCFUART_UISR		0x14		/* Interrupt Status (r) */
#define	MCFUART_UIMR		0x14		/* Interrupt Mask (w) */
#define	MCFUART_UBG1		0x18		/* Baud Rate MSB (r/w) */
#define	MCFUART_UBG2		0x1c		/* Baud Rate LSB (r/w) */
#ifdef	CONFIG_M5272
#define	MCFUART_UTF		0x28		/* Transmitter FIFO (r/w) */
#define	MCFUART_URF		0x2c		/* Receiver FIFO (r/w) */
#define	MCFUART_UFPD		0x30		/* Frac Prec. Divider (r/w) */
#endif
#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \
	defined(CONFIG_M5249) || defined(CONFIG_M525x) || \
	defined(CONFIG_M5307) || defined(CONFIG_M5407)
#define	MCFUART_UIVR		0x30		/* Interrupt Vector (r/w) */
#endif
#define	MCFUART_UIPR		0x34		/* Input Port (r) */
#define	MCFUART_UOP1		0x38		/* Output Port Bit Set (w) */
#define	MCFUART_UOP0		0x3c		/* Output Port Bit Reset (w) */


/*
 *	Define bit flags in Mode Register 1 (MR1).
 */
#define	MCFUART_MR1_RXRTS	0x80		/* Auto RTS flow control */
#define	MCFUART_MR1_RXIRQFULL	0x40		/* RX IRQ type FULL */
#define	MCFUART_MR1_RXIRQRDY	0x00		/* RX IRQ type RDY */
#define	MCFUART_MR1_RXERRBLOCK	0x20		/* RX block error mode */
#define	MCFUART_MR1_RXERRCHAR	0x00		/* RX char error mode */

#define	MCFUART_MR1_PARITYNONE	0x10		/* No parity */
#define	MCFUART_MR1_PARITYEVEN	0x00		/* Even parity */
#define	MCFUART_MR1_PARITYODD	0x04		/* Odd parity */
#define	MCFUART_MR1_PARITYSPACE	0x08		/* Space parity */
#define	MCFUART_MR1_PARITYMARK	0x0c		/* Mark parity */

#define	MCFUART_MR1_CS5		0x00		/* 5 bits per char */
#define	MCFUART_MR1_CS6		0x01		/* 6 bits per char */
#define	MCFUART_MR1_CS7		0x02		/* 7 bits per char */
#define	MCFUART_MR1_CS8		0x03		/* 8 bits per char */

/*
 *	Define bit flags in Mode Register 2 (MR2).
 */
#define	MCFUART_MR2_LOOPBACK	0x80		/* Loopback mode */
#define	MCFUART_MR2_REMOTELOOP	0xc0		/* Remote loopback mode */
#define	MCFUART_MR2_AUTOECHO	0x40		/* Automatic echo */
#define	MCFUART_MR2_TXRTS	0x20		/* Assert RTS on TX */
#define	MCFUART_MR2_TXCTS	0x10		/* Auto CTS flow control */

#define	MCFUART_MR2_STOP1	0x07		/* 1 stop bit */
#define	MCFUART_MR2_STOP15	0x08		/* 1.5 stop bits */
#define	MCFUART_MR2_STOP2	0x0f		/* 2 stop bits */

/*
 *	Define bit flags in Status Register (USR).
 */
#define	MCFUART_USR_RXBREAK	0x80		/* Received BREAK */
#define	MCFUART_USR_RXFRAMING	0x40		/* Received framing error */
#define	MCFUART_USR_RXPARITY	0x20		/* Received parity error */
#define	MCFUART_USR_RXOVERRUN	0x10		/* Received overrun error */
#define	MCFUART_USR_TXEMPTY	0x08		/* Transmitter empty */
#define	MCFUART_USR_TXREADY	0x04		/* Transmitter ready */
#define	MCFUART_USR_RXFULL	0x02		/* Receiver full */
#define	MCFUART_USR_RXREADY	0x01		/* Receiver ready */

#define	MCFUART_USR_RXERR	(MCFUART_USR_RXBREAK | MCFUART_USR_RXFRAMING | \
				MCFUART_USR_RXPARITY | MCFUART_USR_RXOVERRUN)

/*
 *	Define bit flags in Clock Select Register (UCSR).
 */
#define	MCFUART_UCSR_RXCLKTIMER	0xd0		/* RX clock is timer */
#define	MCFUART_UCSR_RXCLKEXT16	0xe0		/* RX clock is external x16 */
#define	MCFUART_UCSR_RXCLKEXT1	0xf0		/* RX clock is external x1 */

#define	MCFUART_UCSR_TXCLKTIMER	0x0d		/* TX clock is timer */
#define	MCFUART_UCSR_TXCLKEXT16	0x0e		/* TX clock is external x16 */
#define	MCFUART_UCSR_TXCLKEXT1	0x0f		/* TX clock is external x1 */

/*
 *	Define bit flags in Command Register (UCR).
 */
#define	MCFUART_UCR_CMDNULL		0x00	/* No command */
#define	MCFUART_UCR_CMDRESETMRPTR	0x10	/* Reset MR pointer */
#define	MCFUART_UCR_CMDRESETRX		0x20	/* Reset receiver */
#define	MCFUART_UCR_CMDRESETTX		0x30	/* Reset transmitter */
#define	MCFUART_UCR_CMDRESETERR		0x40	/* Reset error status */
#define	MCFUART_UCR_CMDRESETBREAK	0x50	/* Reset BREAK change */
#define	MCFUART_UCR_CMDBREAKSTART	0x60	/* Start BREAK */
#define	MCFUART_UCR_CMDBREAKSTOP	0x70	/* Stop BREAK */

#define	MCFUART_UCR_TXNULL	0x00		/* No TX command */
#define	MCFUART_UCR_TXENABLE	0x04		/* Enable TX */
#define	MCFUART_UCR_TXDISABLE	0x08		/* Disable TX */
#define	MCFUART_UCR_RXNULL	0x00		/* No RX command */
#define	MCFUART_UCR_RXENABLE	0x01		/* Enable RX */
#define	MCFUART_UCR_RXDISABLE	0x02		/* Disable RX */

/*
 *	Define bit flags in Input Port Change Register (UIPCR).
 */
#define	MCFUART_UIPCR_CTSCOS	0x10		/* CTS change of state */
#define	MCFUART_UIPCR_CTS	0x01		/* CTS value */

/*
 *	Define bit flags in Input Port Register (UIP).
 */
#define	MCFUART_UIPR_CTS	0x01		/* CTS value */

/*
 *	Define bit flags in Output Port Registers (UOP).
 *	Clear bit by writing to UOP0, set by writing to UOP1.
 */
#define	MCFUART_UOP_RTS		0x01		/* RTS set or clear */

/*
 *	Define bit flags in the Auxiliary Control Register (UACR).
 */
#define	MCFUART_UACR_IEC	0x01		/* Input enable control */

/*
 *	Define bit flags in Interrupt Status Register (UISR).
 *	These same bits are used for the Interrupt Mask Register (UIMR).
 */
#define	MCFUART_UIR_COS		0x80		/* Change of state (CTS) */
#define	MCFUART_UIR_DELTABREAK	0x04		/* Break start or stop */
#define	MCFUART_UIR_RXREADY	0x02		/* Receiver ready */
#define	MCFUART_UIR_TXREADY	0x01		/* Transmitter ready */

#ifdef	CONFIG_M5272
/*
 *	Define bit flags in the Transmitter FIFO Register (UTF).
 */
#define	MCFUART_UTF_TXB		0x1f		/* Transmitter data level */
#define	MCFUART_UTF_FULL	0x20		/* Transmitter fifo full */
#define	MCFUART_UTF_TXS		0xc0		/* Transmitter status */

/*
 *	Define bit flags in the Receiver FIFO Register (URF).
 */
#define	MCFUART_URF_RXB		0x1f		/* Receiver data level */
#define	MCFUART_URF_FULL	0x20		/* Receiver fifo full */
#define	MCFUART_URF_RXS		0xc0		/* Receiver status */
#endif

#if defined(CONFIG_M54xx)
#define MCFUART_TXFIFOSIZE	512
#elif defined(CONFIG_M5272)
#define MCFUART_TXFIFOSIZE	25
#else
#define MCFUART_TXFIFOSIZE	1
#endif
/****************************************************************************/
#endif	/* mcfuart_h */
Commit	Line	Data
b2441318	1	/* SPDX-License-Identifier: GPL-2.0 */
1da177e4 LT	2	/****************************************************************************/
	3
	4	/*
	5	* mcfuart.h -- ColdFire internal UART support defines.
	6	*
	7	* (C) Copyright 1999-2003, Greg Ungerer (gerg@snapgear.com)
	8	* (C) Copyright 2000, Lineo Inc. (www.lineo.com)
	9	*/
	10
	11	/****************************************************************************/
	12	#ifndef mcfuart_h
	13	#define mcfuart_h
	14	/****************************************************************************/
	15
99dc736f GU	16	#include <linux/serial_core.h>
	17	#include <linux/platform_device.h>
	18
	19	struct mcf_platform_uart {
	20	unsigned long mapbase; /* Physical address base */
	21	void __iomem membase; / Virtual address if mapped */
	22	unsigned int irq; /* Interrupt vector */
	23	unsigned int uartclk; /* UART clock rate */
	24	};
	25
1da177e4 LT	26	/*
	27	* Define the ColdFire UART register set addresses.
	28	*/
	29	#define MCFUART_UMR 0x00 /* Mode register (r/w) */
	30	#define MCFUART_USR 0x04 /* Status register (r) */
	31	#define MCFUART_UCSR 0x04 /* Clock Select (w) */
	32	#define MCFUART_UCR 0x08 /* Command register (w) */
	33	#define MCFUART_URB 0x0c /* Receiver Buffer (r) */
	34	#define MCFUART_UTB 0x0c /* Transmit Buffer (w) */
	35	#define MCFUART_UIPCR 0x10 /* Input Port Change (r) */
	36	#define MCFUART_UACR 0x10 /* Auxiliary Control (w) */
ab690d9f	37	#define MCFUART_UISR 0x14 /* Interrupt Status (r) */
1da177e4 LT	38	#define MCFUART_UIMR 0x14 /* Interrupt Mask (w) */
	39	#define MCFUART_UBG1 0x18 /* Baud Rate MSB (r/w) */
	40	#define MCFUART_UBG2 0x1c /* Baud Rate LSB (r/w) */
	41	#ifdef CONFIG_M5272
	42	#define MCFUART_UTF 0x28 /* Transmitter FIFO (r/w) */
	43	#define MCFUART_URF 0x2c /* Receiver FIFO (r/w) */
	44	#define MCFUART_UFPD 0x30 /* Frac Prec. Divider (r/w) */
55148f6f GU	45	#endif
55148f6f GU	46	#if defined(CONFIG_M5206) \|\| defined(CONFIG_M5206e) \|\| \
04e037aa SK	47	defined(CONFIG_M5249) \|\| defined(CONFIG_M525x) \|\| \
04e037aa SK	48	defined(CONFIG_M5307) \|\| defined(CONFIG_M5407)
1da177e4 LT	49	#define MCFUART_UIVR 0x30 /* Interrupt Vector (r/w) */
	50	#endif
	51	#define MCFUART_UIPR 0x34 /* Input Port (r) */
	52	#define MCFUART_UOP1 0x38 /* Output Port Bit Set (w) */
	53	#define MCFUART_UOP0 0x3c /* Output Port Bit Reset (w) */
	54
	55
	56	/*
	57	* Define bit flags in Mode Register 1 (MR1).
	58	*/
	59	#define MCFUART_MR1_RXRTS 0x80 /* Auto RTS flow control */
	60	#define MCFUART_MR1_RXIRQFULL 0x40 /* RX IRQ type FULL */
	61	#define MCFUART_MR1_RXIRQRDY 0x00 /* RX IRQ type RDY */
	62	#define MCFUART_MR1_RXERRBLOCK 0x20 /* RX block error mode */
	63	#define MCFUART_MR1_RXERRCHAR 0x00 /* RX char error mode */
	64
	65	#define MCFUART_MR1_PARITYNONE 0x10 /* No parity */
	66	#define MCFUART_MR1_PARITYEVEN 0x00 /* Even parity */
	67	#define MCFUART_MR1_PARITYODD 0x04 /* Odd parity */
	68	#define MCFUART_MR1_PARITYSPACE 0x08 /* Space parity */
	69	#define MCFUART_MR1_PARITYMARK 0x0c /* Mark parity */
	70
	71	#define MCFUART_MR1_CS5 0x00 /* 5 bits per char */
	72	#define MCFUART_MR1_CS6 0x01 /* 6 bits per char */
	73	#define MCFUART_MR1_CS7 0x02 /* 7 bits per char */
	74	#define MCFUART_MR1_CS8 0x03 /* 8 bits per char */
	75
	76	/*
	77	* Define bit flags in Mode Register 2 (MR2).
	78	*/
	79	#define MCFUART_MR2_LOOPBACK 0x80 /* Loopback mode */
	80	#define MCFUART_MR2_REMOTELOOP 0xc0 /* Remote loopback mode */
	81	#define MCFUART_MR2_AUTOECHO 0x40 /* Automatic echo */
	82	#define MCFUART_MR2_TXRTS 0x20 /* Assert RTS on TX */
	83	#define MCFUART_MR2_TXCTS 0x10 /* Auto CTS flow control */
	84
	85	#define MCFUART_MR2_STOP1 0x07 /* 1 stop bit */
	86	#define MCFUART_MR2_STOP15 0x08 /* 1.5 stop bits */
	87	#define MCFUART_MR2_STOP2 0x0f /* 2 stop bits */
	88
	89	/*
	90	* Define bit flags in Status Register (USR).
	91	*/
	92	#define MCFUART_USR_RXBREAK 0x80 /* Received BREAK */
	93	#define MCFUART_USR_RXFRAMING 0x40 /* Received framing error */
	94	#define MCFUART_USR_RXPARITY 0x20 /* Received parity error */
	95	#define MCFUART_USR_RXOVERRUN 0x10 /* Received overrun error */
	96	#define MCFUART_USR_TXEMPTY 0x08 /* Transmitter empty */
	97	#define MCFUART_USR_TXREADY 0x04 /* Transmitter ready */
	98	#define MCFUART_USR_RXFULL 0x02 /* Receiver full */
	99	#define MCFUART_USR_RXREADY 0x01 /* Receiver ready */
	100
	101	#define MCFUART_USR_RXERR (MCFUART_USR_RXBREAK \| MCFUART_USR_RXFRAMING \| \
	102	MCFUART_USR_RXPARITY \| MCFUART_USR_RXOVERRUN)
	103
	104	/*
	105	* Define bit flags in Clock Select Register (UCSR).
	106	*/
	107	#define MCFUART_UCSR_RXCLKTIMER 0xd0 /* RX clock is timer */
	108	#define MCFUART_UCSR_RXCLKEXT16 0xe0 /* RX clock is external x16 */
	109	#define MCFUART_UCSR_RXCLKEXT1 0xf0 /* RX clock is external x1 */
	110
	111	#define MCFUART_UCSR_TXCLKTIMER 0x0d /* TX clock is timer */
	112	#define MCFUART_UCSR_TXCLKEXT16 0x0e /* TX clock is external x16 */
113	#define MCFUART_UCSR_TXCLKEXT1 0x0f /* TX clock is external x1 */
114
115	/*
116	* Define bit flags in Command Register (UCR).
117	*/
118	#define MCFUART_UCR_CMDNULL 0x00 /* No command */
119	#define MCFUART_UCR_CMDRESETMRPTR 0x10 /* Reset MR pointer */
120	#define MCFUART_UCR_CMDRESETRX 0x20 /* Reset receiver */
121	#define MCFUART_UCR_CMDRESETTX 0x30 /* Reset transmitter */
122	#define MCFUART_UCR_CMDRESETERR 0x40 /* Reset error status */
123	#define MCFUART_UCR_CMDRESETBREAK 0x50 /* Reset BREAK change */
124	#define MCFUART_UCR_CMDBREAKSTART 0x60 /* Start BREAK */
125	#define MCFUART_UCR_CMDBREAKSTOP 0x70 /* Stop BREAK */
126
127	#define MCFUART_UCR_TXNULL 0x00 /* No TX command */
128	#define MCFUART_UCR_TXENABLE 0x04 /* Enable TX */
129	#define MCFUART_UCR_TXDISABLE 0x08 /* Disable TX */
130	#define MCFUART_UCR_RXNULL 0x00 /* No RX command */
131	#define MCFUART_UCR_RXENABLE 0x01 /* Enable RX */
132	#define MCFUART_UCR_RXDISABLE 0x02 /* Disable RX */
133
134	/*
135	* Define bit flags in Input Port Change Register (UIPCR).
136	*/
137	#define MCFUART_UIPCR_CTSCOS 0x10 /* CTS change of state */
138	#define MCFUART_UIPCR_CTS 0x01 /* CTS value */
139
140	/*
141	* Define bit flags in Input Port Register (UIP).
142	*/
143	#define MCFUART_UIPR_CTS 0x01 /* CTS value */
144
145	/*
146	* Define bit flags in Output Port Registers (UOP).
147	* Clear bit by writing to UOP0, set by writing to UOP1.
148	*/
149	#define MCFUART_UOP_RTS 0x01 /* RTS set or clear */
150
151	/*
152	* Define bit flags in the Auxiliary Control Register (UACR).
153	*/
154	#define MCFUART_UACR_IEC 0x01 /* Input enable control */
155
156	/*
157	* Define bit flags in Interrupt Status Register (UISR).
158	* These same bits are used for the Interrupt Mask Register (UIMR).
159	*/
160	#define MCFUART_UIR_COS 0x80 /* Change of state (CTS) */
161	#define MCFUART_UIR_DELTABREAK 0x04 /* Break start or stop */
162	#define MCFUART_UIR_RXREADY 0x02 /* Receiver ready */
163	#define MCFUART_UIR_TXREADY 0x01 /* Transmitter ready */
164
165	#ifdef CONFIG_M5272
166	/*
167	* Define bit flags in the Transmitter FIFO Register (UTF).
168	*/
169	#define MCFUART_UTF_TXB 0x1f /* Transmitter data level */
170	#define MCFUART_UTF_FULL 0x20 /* Transmitter fifo full */
171	#define MCFUART_UTF_TXS 0xc0 /* Transmitter status */
172
173	/*
174	* Define bit flags in the Receiver FIFO Register (URF).
175	*/
176	#define MCFUART_URF_RXB 0x1f /* Receiver data level */
177	#define MCFUART_URF_FULL 0x20 /* Receiver fifo full */
178	#define MCFUART_URF_RXS 0xc0 /* Receiver status */
179	#endif
180
5b2e6555	181	#if defined(CONFIG_M54xx)
48a232d1 PDM	182	#define MCFUART_TXFIFOSIZE 512
48a232d1 PDM	183	#elif defined(CONFIG_M5272)
3732b68f PDM	184	#define MCFUART_TXFIFOSIZE 25
	185	#else
	186	#define MCFUART_TXFIFOSIZE 1
	187	#endif
1da177e4 LT	188	/****************************************************************************/
1da177e4 LT	189	#endif /* mcfuart_h */