[mirror_ubuntu-jammy-kernel.git] / arch / m68k / mac / oss.c

// SPDX-License-Identifier: GPL-2.0
/*
 *	Operating System Services (OSS) chip handling
 *	Written by Joshua M. Thompson (funaho@jurai.org)
 *
 *
 *	This chip is used in the IIfx in place of VIA #2. It acts like a fancy
 *	VIA chip with prorammable interrupt levels.
 *
 * 990502 (jmt) - Major rewrite for new interrupt architecture as well as some
 *		  recent insights into OSS operational details.
 * 990610 (jmt) - Now taking full advantage of the OSS. Interrupts are mapped
 *		  to mostly match the A/UX interrupt scheme supported on the
 *		  VIA side. Also added support for enabling the ISM irq again
 *		  since we now have a functional IOP manager.
 */

#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/mm.h>
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/irq.h>

#include <asm/macintosh.h>
#include <asm/macints.h>
#include <asm/mac_via.h>
#include <asm/mac_oss.h>

int oss_present;
volatile struct mac_oss *oss;

/*
 * Initialize the OSS
 */

void __init oss_init(void)
{
	int i;

	if (macintosh_config->ident != MAC_MODEL_IIFX)
		return;

	oss = (struct mac_oss *) OSS_BASE;
	pr_debug("OSS detected at %p", oss);
	oss_present = 1;

	/* Disable all interrupts. Unlike a VIA it looks like we    */
	/* do this by setting the source's interrupt level to zero. */

	for (i = 0; i < OSS_NUM_SOURCES; i++)
		oss->irq_level[i] = 0;
}

/*
 * Handle OSS interrupts.
 * XXX how do you clear a pending IRQ? is it even necessary?
 */

static void oss_iopism_irq(struct irq_desc *desc)
{
	generic_handle_irq(IRQ_MAC_ADB);
}

static void oss_scsi_irq(struct irq_desc *desc)
{
	generic_handle_irq(IRQ_MAC_SCSI);
}

static void oss_nubus_irq(struct irq_desc *desc)
{
	u16 events, irq_bit;
	int irq_num;

	events = oss->irq_pending & OSS_IP_NUBUS;
	irq_num = NUBUS_SOURCE_BASE + 5;
	irq_bit = OSS_IP_NUBUS5;
	do {
		if (events & irq_bit) {
			events &= ~irq_bit;
			generic_handle_irq(irq_num);
		}
		--irq_num;
		irq_bit >>= 1;
	} while (events);
}

static void oss_iopscc_irq(struct irq_desc *desc)
{
	generic_handle_irq(IRQ_MAC_SCC);
}

/*
 * Register the OSS and NuBus interrupt dispatchers.
 *
 * This IRQ mapping is laid out with two things in mind: first, we try to keep
 * things on their own levels to avoid having to do double-dispatches. Second,
 * the levels match as closely as possible the alternate IRQ mapping mode (aka
 * "A/UX mode") available on some VIA machines.
 */

#define OSS_IRQLEV_IOPISM    IRQ_AUTO_1
#define OSS_IRQLEV_SCSI      IRQ_AUTO_2
#define OSS_IRQLEV_NUBUS     IRQ_AUTO_3
#define OSS_IRQLEV_IOPSCC    IRQ_AUTO_4
#define OSS_IRQLEV_VIA1      IRQ_AUTO_6

void __init oss_register_interrupts(void)
{
	irq_set_chained_handler(OSS_IRQLEV_IOPISM, oss_iopism_irq);
	irq_set_chained_handler(OSS_IRQLEV_SCSI,   oss_scsi_irq);
	irq_set_chained_handler(OSS_IRQLEV_NUBUS,  oss_nubus_irq);
	irq_set_chained_handler(OSS_IRQLEV_IOPSCC, oss_iopscc_irq);
	irq_set_chained_handler(OSS_IRQLEV_VIA1,   via1_irq);

	/* OSS_VIA1 gets enabled here because it has no machspec interrupt. */
	oss->irq_level[OSS_VIA1] = OSS_IRQLEV_VIA1;
}

/*
 * Enable an OSS interrupt
 *
 * It looks messy but it's rather straightforward. The switch() statement
 * just maps the machspec interrupt numbers to the right OSS interrupt
 * source (if the OSS handles that interrupt) and then sets the interrupt
 * level for that source to nonzero, thus enabling the interrupt.
 */

void oss_irq_enable(int irq) {
	switch(irq) {
		case IRQ_MAC_SCC:
			oss->irq_level[OSS_IOPSCC] = OSS_IRQLEV_IOPSCC;
			return;
		case IRQ_MAC_ADB:
			oss->irq_level[OSS_IOPISM] = OSS_IRQLEV_IOPISM;
			return;
		case IRQ_MAC_SCSI:
			oss->irq_level[OSS_SCSI] = OSS_IRQLEV_SCSI;
			return;
		case IRQ_NUBUS_9:
		case IRQ_NUBUS_A:
		case IRQ_NUBUS_B:
		case IRQ_NUBUS_C:
		case IRQ_NUBUS_D:
		case IRQ_NUBUS_E:
			irq -= NUBUS_SOURCE_BASE;
			oss->irq_level[irq] = OSS_IRQLEV_NUBUS;
			return;
	}

	if (IRQ_SRC(irq) == 1)
		via_irq_enable(irq);
}

/*
 * Disable an OSS interrupt
 *
 * Same as above except we set the source's interrupt level to zero,
 * to disable the interrupt.
 */

void oss_irq_disable(int irq) {
	switch(irq) {
		case IRQ_MAC_SCC:
			oss->irq_level[OSS_IOPSCC] = 0;
			return;
		case IRQ_MAC_ADB:
			oss->irq_level[OSS_IOPISM] = 0;
			return;
		case IRQ_MAC_SCSI:
			oss->irq_level[OSS_SCSI] = 0;
			return;
		case IRQ_NUBUS_9:
		case IRQ_NUBUS_A:
		case IRQ_NUBUS_B:
		case IRQ_NUBUS_C:
		case IRQ_NUBUS_D:
		case IRQ_NUBUS_E:
			irq -= NUBUS_SOURCE_BASE;
			oss->irq_level[irq] = 0;
			return;
	}

	if (IRQ_SRC(irq) == 1)
		via_irq_disable(irq);
}
Commit	Line	Data
b2441318	1	// SPDX-License-Identifier: GPL-2.0
1da177e4	2	/*
da3fb3c9	3	* Operating System Services (OSS) chip handling
1da177e4 LT	4	* Written by Joshua M. Thompson (funaho@jurai.org)
	5	*
	6	*
	7	* This chip is used in the IIfx in place of VIA #2. It acts like a fancy
	8	* VIA chip with prorammable interrupt levels.
	9	*
	10	* 990502 (jmt) - Major rewrite for new interrupt architecture as well as some
	11	* recent insights into OSS operational details.
0c79cf6a	12	* 990610 (jmt) - Now taking full advantage of the OSS. Interrupts are mapped
1da177e4 LT	13	* to mostly match the A/UX interrupt scheme supported on the
	14	* VIA side. Also added support for enabling the ISM irq again
	15	* since we now have a functional IOP manager.
	16	*/
	17
	18	#include <linux/types.h>
	19	#include <linux/kernel.h>
	20	#include <linux/mm.h>
	21	#include <linux/delay.h>
	22	#include <linux/init.h>
ddc7fd25	23	#include <linux/irq.h>
1da177e4	24
1da177e4 LT	25	#include <asm/macintosh.h>
	26	#include <asm/macints.h>
	27	#include <asm/mac_via.h>
	28	#include <asm/mac_oss.h>
	29
	30	int oss_present;
	31	volatile struct mac_oss *oss;
	32
1da177e4 LT	33	/*
1da177e4 LT	34	* Initialize the OSS
1da177e4 LT	35	*/
	36
	37	void __init oss_init(void)
	38	{
	39	int i;
	40
7a0bb442 FT	41	if (macintosh_config->ident != MAC_MODEL_IIFX)
7a0bb442 FT	42	return;
1da177e4 LT	43
1da177e4 LT	44	oss = (struct mac_oss *) OSS_BASE;
7a0bb442 FT	45	pr_debug("OSS detected at %p", oss);
7a0bb442 FT	46	oss_present = 1;
1da177e4 LT	47
	48	/* Disable all interrupts. Unlike a VIA it looks like we */
	49	/* do this by setting the source's interrupt level to zero. */
	50
b24f670b	51	for (i = 0; i < OSS_NUM_SOURCES; i++)
da3fb3c9	52	oss->irq_level[i] = 0;
1da177e4 LT	53	}
1da177e4 LT	54
1da177e4	55	/*
317b749e FT	56	* Handle OSS interrupts.
317b749e FT	57	* XXX how do you clear a pending IRQ? is it even necessary?
1da177e4 LT	58	*/
1da177e4 LT	59
317b749e	60	static void oss_iopism_irq(struct irq_desc *desc)
9145db56	61	{
317b749e	62	generic_handle_irq(IRQ_MAC_ADB);
9145db56	63	}
1da177e4	64
317b749e FT	65	static void oss_scsi_irq(struct irq_desc *desc)
	66	{
	67	generic_handle_irq(IRQ_MAC_SCSI);
	68	}
1da177e4	69
bd0b9ac4	70	static void oss_nubus_irq(struct irq_desc *desc)
9145db56	71	{
317b749e FT	72	u16 events, irq_bit;
317b749e FT	73	int irq_num;
9145db56 GU	74
9145db56 GU	75	events = oss->irq_pending & OSS_IP_NUBUS;
317b749e FT	76	irq_num = NUBUS_SOURCE_BASE + 5;
317b749e FT	77	irq_bit = OSS_IP_NUBUS5;
9145db56	78	do {
9145db56	79	if (events & irq_bit) {
317b749e FT	80	events &= ~irq_bit;
317b749e FT	81	generic_handle_irq(irq_num);
9145db56	82	}
317b749e FT	83	--irq_num;
	84	irq_bit >>= 1;
	85	} while (events);
	86	}
	87
	88	static void oss_iopscc_irq(struct irq_desc *desc)
	89	{
	90	generic_handle_irq(IRQ_MAC_SCC);
9145db56	91	}
9145db56 GU	92
	93	/*
	94	* Register the OSS and NuBus interrupt dispatchers.
da3fb3c9 FT	95	*
	96	* This IRQ mapping is laid out with two things in mind: first, we try to keep
	97	* things on their own levels to avoid having to do double-dispatches. Second,
	98	* the levels match as closely as possible the alternate IRQ mapping mode (aka
	99	* "A/UX mode") available on some VIA machines.
9145db56 GU	100	*/
9145db56 GU	101
da3fb3c9 FT	102	#define OSS_IRQLEV_IOPISM IRQ_AUTO_1
	103	#define OSS_IRQLEV_SCSI IRQ_AUTO_2
	104	#define OSS_IRQLEV_NUBUS IRQ_AUTO_3
	105	#define OSS_IRQLEV_IOPSCC IRQ_AUTO_4
	106	#define OSS_IRQLEV_VIA1 IRQ_AUTO_6
	107
9145db56 GU	108	void __init oss_register_interrupts(void)
9145db56 GU	109	{
317b749e FT	110	irq_set_chained_handler(OSS_IRQLEV_IOPISM, oss_iopism_irq);
317b749e FT	111	irq_set_chained_handler(OSS_IRQLEV_SCSI, oss_scsi_irq);
da3fb3c9	112	irq_set_chained_handler(OSS_IRQLEV_NUBUS, oss_nubus_irq);
317b749e	113	irq_set_chained_handler(OSS_IRQLEV_IOPSCC, oss_iopscc_irq);
da3fb3c9 FT	114	irq_set_chained_handler(OSS_IRQLEV_VIA1, via1_irq);
	115
	116	/* OSS_VIA1 gets enabled here because it has no machspec interrupt. */
317b749e	117	oss->irq_level[OSS_VIA1] = OSS_IRQLEV_VIA1;
9145db56	118	}
1da177e4 LT	119
	120	/*
	121	* Enable an OSS interrupt
	122	*
	123	* It looks messy but it's rather straightforward. The switch() statement
	124	* just maps the machspec interrupt numbers to the right OSS interrupt
	125	* source (if the OSS handles that interrupt) and then sets the interrupt
	126	* level for that source to nonzero, thus enabling the interrupt.
	127	*/
	128
	129	void oss_irq_enable(int irq) {
1da177e4	130	switch(irq) {
80614e5a	131	case IRQ_MAC_SCC:
1da177e4	132	oss->irq_level[OSS_IOPSCC] = OSS_IRQLEV_IOPSCC;
da3fb3c9	133	return;
1da177e4 LT	134	case IRQ_MAC_ADB:
1da177e4 LT	135	oss->irq_level[OSS_IOPISM] = OSS_IRQLEV_IOPISM;
da3fb3c9	136	return;
1da177e4 LT	137	case IRQ_MAC_SCSI:
1da177e4 LT	138	oss->irq_level[OSS_SCSI] = OSS_IRQLEV_SCSI;
da3fb3c9	139	return;
1da177e4 LT	140	case IRQ_NUBUS_9:
	141	case IRQ_NUBUS_A:
	142	case IRQ_NUBUS_B:
	143	case IRQ_NUBUS_C:
	144	case IRQ_NUBUS_D:
	145	case IRQ_NUBUS_E:
	146	irq -= NUBUS_SOURCE_BASE;
	147	oss->irq_level[irq] = OSS_IRQLEV_NUBUS;
da3fb3c9	148	return;
1da177e4	149	}
da3fb3c9 FT	150
	151	if (IRQ_SRC(irq) == 1)
	152	via_irq_enable(irq);
1da177e4 LT	153	}
	154
	155	/*
	156	* Disable an OSS interrupt
	157	*
	158	* Same as above except we set the source's interrupt level to zero,
	159	* to disable the interrupt.
	160	*/
	161
	162	void oss_irq_disable(int irq) {
1da177e4	163	switch(irq) {
80614e5a	164	case IRQ_MAC_SCC:
da3fb3c9 FT	165	oss->irq_level[OSS_IOPSCC] = 0;
da3fb3c9 FT	166	return;
1da177e4	167	case IRQ_MAC_ADB:
da3fb3c9 FT	168	oss->irq_level[OSS_IOPISM] = 0;
da3fb3c9 FT	169	return;
1da177e4	170	case IRQ_MAC_SCSI:
da3fb3c9 FT	171	oss->irq_level[OSS_SCSI] = 0;
da3fb3c9 FT	172	return;
1da177e4 LT	173	case IRQ_NUBUS_9:
	174	case IRQ_NUBUS_A:
	175	case IRQ_NUBUS_B:
	176	case IRQ_NUBUS_C:
	177	case IRQ_NUBUS_D:
	178	case IRQ_NUBUS_E:
	179	irq -= NUBUS_SOURCE_BASE;
da3fb3c9 FT	180	oss->irq_level[irq] = 0;
da3fb3c9 FT	181	return;
1da177e4	182	}
da3fb3c9 FT	183
	184	if (IRQ_SRC(irq) == 1)
	185	via_irq_disable(irq);
1da177e4	186	}