[mirror_ubuntu-bionic-kernel.git] / arch / m68k / mac / oss.c

// SPDX-License-Identifier: GPL-2.0
/*
 *	Operating System Services (OSS) chip handling
 *	Written by Joshua M. Thompson (funaho@jurai.org)
 *
 *
 *	This chip is used in the IIfx in place of VIA #2. It acts like a fancy
 *	VIA chip with prorammable interrupt levels.
 *
 * 990502 (jmt) - Major rewrite for new interrupt architecture as well as some
 *		  recent insights into OSS operational details.
 * 990610 (jmt) - Now taking full advantage of the OSS. Interrupts are mapped
 *		  to mostly match the A/UX interrupt scheme supported on the
 *		  VIA side. Also added support for enabling the ISM irq again
 *		  since we now have a functional IOP manager.
 */

#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/mm.h>
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/irq.h>

#include <asm/macintosh.h>
#include <asm/macints.h>
#include <asm/mac_via.h>
#include <asm/mac_oss.h>

int oss_present;
volatile struct mac_oss *oss;

/*
 * Initialize the OSS
 */

void __init oss_init(void)
{
	int i;

	if (macintosh_config->ident != MAC_MODEL_IIFX)
		return;

	oss = (struct mac_oss *) OSS_BASE;
	pr_debug("OSS detected at %p", oss);
	oss_present = 1;

	/* Disable all interrupts. Unlike a VIA it looks like we    */
	/* do this by setting the source's interrupt level to zero. */

	for (i = 0; i < OSS_NUM_SOURCES; i++)
		oss->irq_level[i] = 0;
}

/*
 * Handle miscellaneous OSS interrupts.
 */

static void oss_irq(struct irq_desc *desc)
{
	int events = oss->irq_pending &
		(OSS_IP_IOPSCC | OSS_IP_SCSI | OSS_IP_IOPISM);

	if (events & OSS_IP_IOPSCC) {
		oss->irq_pending &= ~OSS_IP_IOPSCC;
		generic_handle_irq(IRQ_MAC_SCC);
	}

	if (events & OSS_IP_SCSI) {
		oss->irq_pending &= ~OSS_IP_SCSI;
		generic_handle_irq(IRQ_MAC_SCSI);
	}

	if (events & OSS_IP_IOPISM) {
		oss->irq_pending &= ~OSS_IP_IOPISM;
		generic_handle_irq(IRQ_MAC_ADB);
	}
}

/*
 * Nubus IRQ handler, OSS style
 *
 * Unlike the VIA/RBV this is on its own autovector interrupt level.
 */

static void oss_nubus_irq(struct irq_desc *desc)
{
	int events, irq_bit, i;

	events = oss->irq_pending & OSS_IP_NUBUS;
	if (!events)
		return;

	/* There are only six slots on the OSS, not seven */

	i = 6;
	irq_bit = 0x40;
	do {
		--i;
		irq_bit >>= 1;
		if (events & irq_bit) {
			oss->irq_pending &= ~irq_bit;
			generic_handle_irq(NUBUS_SOURCE_BASE + i);
		}
	} while(events & (irq_bit - 1));
}

/*
 * Register the OSS and NuBus interrupt dispatchers.
 *
 * This IRQ mapping is laid out with two things in mind: first, we try to keep
 * things on their own levels to avoid having to do double-dispatches. Second,
 * the levels match as closely as possible the alternate IRQ mapping mode (aka
 * "A/UX mode") available on some VIA machines.
 */

#define OSS_IRQLEV_IOPISM    IRQ_AUTO_1
#define OSS_IRQLEV_SCSI      IRQ_AUTO_2
#define OSS_IRQLEV_NUBUS     IRQ_AUTO_3
#define OSS_IRQLEV_IOPSCC    IRQ_AUTO_4
#define OSS_IRQLEV_VIA1      IRQ_AUTO_6

void __init oss_register_interrupts(void)
{
	irq_set_chained_handler(OSS_IRQLEV_IOPISM, oss_irq);
	irq_set_chained_handler(OSS_IRQLEV_SCSI,   oss_irq);
	irq_set_chained_handler(OSS_IRQLEV_NUBUS,  oss_nubus_irq);
	irq_set_chained_handler(OSS_IRQLEV_IOPSCC, oss_irq);
	irq_set_chained_handler(OSS_IRQLEV_VIA1,   via1_irq);

	/* OSS_VIA1 gets enabled here because it has no machspec interrupt. */
	oss->irq_level[OSS_VIA1] = IRQ_AUTO_6;
}

/*
 * Enable an OSS interrupt
 *
 * It looks messy but it's rather straightforward. The switch() statement
 * just maps the machspec interrupt numbers to the right OSS interrupt
 * source (if the OSS handles that interrupt) and then sets the interrupt
 * level for that source to nonzero, thus enabling the interrupt.
 */

void oss_irq_enable(int irq) {
	switch(irq) {
		case IRQ_MAC_SCC:
			oss->irq_level[OSS_IOPSCC] = OSS_IRQLEV_IOPSCC;
			return;
		case IRQ_MAC_ADB:
			oss->irq_level[OSS_IOPISM] = OSS_IRQLEV_IOPISM;
			return;
		case IRQ_MAC_SCSI:
			oss->irq_level[OSS_SCSI] = OSS_IRQLEV_SCSI;
			return;
		case IRQ_NUBUS_9:
		case IRQ_NUBUS_A:
		case IRQ_NUBUS_B:
		case IRQ_NUBUS_C:
		case IRQ_NUBUS_D:
		case IRQ_NUBUS_E:
			irq -= NUBUS_SOURCE_BASE;
			oss->irq_level[irq] = OSS_IRQLEV_NUBUS;
			return;
	}

	if (IRQ_SRC(irq) == 1)
		via_irq_enable(irq);
}

/*
 * Disable an OSS interrupt
 *
 * Same as above except we set the source's interrupt level to zero,
 * to disable the interrupt.
 */

void oss_irq_disable(int irq) {
	switch(irq) {
		case IRQ_MAC_SCC:
			oss->irq_level[OSS_IOPSCC] = 0;
			return;
		case IRQ_MAC_ADB:
			oss->irq_level[OSS_IOPISM] = 0;
			return;
		case IRQ_MAC_SCSI:
			oss->irq_level[OSS_SCSI] = 0;
			return;
		case IRQ_NUBUS_9:
		case IRQ_NUBUS_A:
		case IRQ_NUBUS_B:
		case IRQ_NUBUS_C:
		case IRQ_NUBUS_D:
		case IRQ_NUBUS_E:
			irq -= NUBUS_SOURCE_BASE;
			oss->irq_level[irq] = 0;
			return;
	}

	if (IRQ_SRC(irq) == 1)
		via_irq_disable(irq);
}
Commit	Line	Data
b2441318	1	// SPDX-License-Identifier: GPL-2.0
1da177e4	2	/*
da3fb3c9	3	* Operating System Services (OSS) chip handling
1da177e4 LT	4	* Written by Joshua M. Thompson (funaho@jurai.org)
	5	*
	6	*
	7	* This chip is used in the IIfx in place of VIA #2. It acts like a fancy
	8	* VIA chip with prorammable interrupt levels.
	9	*
	10	* 990502 (jmt) - Major rewrite for new interrupt architecture as well as some
	11	* recent insights into OSS operational details.
0c79cf6a	12	* 990610 (jmt) - Now taking full advantage of the OSS. Interrupts are mapped
1da177e4 LT	13	* to mostly match the A/UX interrupt scheme supported on the
	14	* VIA side. Also added support for enabling the ISM irq again
	15	* since we now have a functional IOP manager.
	16	*/
	17
	18	#include <linux/types.h>
	19	#include <linux/kernel.h>
	20	#include <linux/mm.h>
	21	#include <linux/delay.h>
	22	#include <linux/init.h>
ddc7fd25	23	#include <linux/irq.h>
1da177e4	24
1da177e4 LT	25	#include <asm/macintosh.h>
	26	#include <asm/macints.h>
	27	#include <asm/mac_via.h>
	28	#include <asm/mac_oss.h>
	29
	30	int oss_present;
	31	volatile struct mac_oss *oss;
	32
1da177e4 LT	33	/*
1da177e4 LT	34	* Initialize the OSS
1da177e4 LT	35	*/
	36
	37	void __init oss_init(void)
	38	{
	39	int i;
	40
7a0bb442 FT	41	if (macintosh_config->ident != MAC_MODEL_IIFX)
7a0bb442 FT	42	return;
1da177e4 LT	43
1da177e4 LT	44	oss = (struct mac_oss *) OSS_BASE;
7a0bb442 FT	45	pr_debug("OSS detected at %p", oss);
7a0bb442 FT	46	oss_present = 1;
1da177e4 LT	47
	48	/* Disable all interrupts. Unlike a VIA it looks like we */
	49	/* do this by setting the source's interrupt level to zero. */
	50
b24f670b	51	for (i = 0; i < OSS_NUM_SOURCES; i++)
da3fb3c9	52	oss->irq_level[i] = 0;
1da177e4 LT	53	}
1da177e4 LT	54
1da177e4	55	/*
da3fb3c9	56	* Handle miscellaneous OSS interrupts.
1da177e4 LT	57	*/
1da177e4 LT	58
bd0b9ac4	59	static void oss_irq(struct irq_desc *desc)
9145db56	60	{
da3fb3c9	61	int events = oss->irq_pending &
625b86ad	62	(OSS_IP_IOPSCC \| OSS_IP_SCSI \| OSS_IP_IOPISM);
9145db56	63
da3fb3c9 FT	64	if (events & OSS_IP_IOPSCC) {
	65	oss->irq_pending &= ~OSS_IP_IOPSCC;
	66	generic_handle_irq(IRQ_MAC_SCC);
	67	}
	68
	69	if (events & OSS_IP_SCSI) {
9145db56 GU	70	oss->irq_pending &= ~OSS_IP_SCSI;
9145db56 GU	71	generic_handle_irq(IRQ_MAC_SCSI);
da3fb3c9 FT	72	}
	73
	74	if (events & OSS_IP_IOPISM) {
	75	oss->irq_pending &= ~OSS_IP_IOPISM;
	76	generic_handle_irq(IRQ_MAC_ADB);
9145db56 GU	77	}
9145db56 GU	78	}
1da177e4 LT	79
	80	/*
	81	* Nubus IRQ handler, OSS style
	82	*
	83	* Unlike the VIA/RBV this is on its own autovector interrupt level.
	84	*/
	85
bd0b9ac4	86	static void oss_nubus_irq(struct irq_desc *desc)
9145db56 GU	87	{
	88	int events, irq_bit, i;
	89
	90	events = oss->irq_pending & OSS_IP_NUBUS;
	91	if (!events)
	92	return;
	93
9145db56 GU	94	/* There are only six slots on the OSS, not seven */
	95
	96	i = 6;
	97	irq_bit = 0x40;
	98	do {
	99	--i;
	100	irq_bit >>= 1;
	101	if (events & irq_bit) {
	102	oss->irq_pending &= ~irq_bit;
	103	generic_handle_irq(NUBUS_SOURCE_BASE + i);
	104	}
	105	} while(events & (irq_bit - 1));
	106	}
9145db56 GU	107
	108	/*
	109	* Register the OSS and NuBus interrupt dispatchers.
da3fb3c9 FT	110	*
	111	* This IRQ mapping is laid out with two things in mind: first, we try to keep
	112	* things on their own levels to avoid having to do double-dispatches. Second,
	113	* the levels match as closely as possible the alternate IRQ mapping mode (aka
	114	* "A/UX mode") available on some VIA machines.
9145db56 GU	115	*/
9145db56 GU	116
da3fb3c9 FT	117	#define OSS_IRQLEV_IOPISM IRQ_AUTO_1
	118	#define OSS_IRQLEV_SCSI IRQ_AUTO_2
	119	#define OSS_IRQLEV_NUBUS IRQ_AUTO_3
	120	#define OSS_IRQLEV_IOPSCC IRQ_AUTO_4
	121	#define OSS_IRQLEV_VIA1 IRQ_AUTO_6
	122
9145db56 GU	123	void __init oss_register_interrupts(void)
9145db56 GU	124	{
da3fb3c9 FT	125	irq_set_chained_handler(OSS_IRQLEV_IOPISM, oss_irq);
	126	irq_set_chained_handler(OSS_IRQLEV_SCSI, oss_irq);
	127	irq_set_chained_handler(OSS_IRQLEV_NUBUS, oss_nubus_irq);
	128	irq_set_chained_handler(OSS_IRQLEV_IOPSCC, oss_irq);
	129	irq_set_chained_handler(OSS_IRQLEV_VIA1, via1_irq);
	130
	131	/* OSS_VIA1 gets enabled here because it has no machspec interrupt. */
	132	oss->irq_level[OSS_VIA1] = IRQ_AUTO_6;
9145db56	133	}
1da177e4 LT	134
	135	/*
	136	* Enable an OSS interrupt
	137	*
	138	* It looks messy but it's rather straightforward. The switch() statement
	139	* just maps the machspec interrupt numbers to the right OSS interrupt
	140	* source (if the OSS handles that interrupt) and then sets the interrupt
	141	* level for that source to nonzero, thus enabling the interrupt.
	142	*/
	143
	144	void oss_irq_enable(int irq) {
1da177e4	145	switch(irq) {
80614e5a	146	case IRQ_MAC_SCC:
1da177e4	147	oss->irq_level[OSS_IOPSCC] = OSS_IRQLEV_IOPSCC;
da3fb3c9	148	return;
1da177e4 LT	149	case IRQ_MAC_ADB:
1da177e4 LT	150	oss->irq_level[OSS_IOPISM] = OSS_IRQLEV_IOPISM;
da3fb3c9	151	return;
1da177e4 LT	152	case IRQ_MAC_SCSI:
1da177e4 LT	153	oss->irq_level[OSS_SCSI] = OSS_IRQLEV_SCSI;
da3fb3c9	154	return;
1da177e4 LT	155	case IRQ_NUBUS_9:
	156	case IRQ_NUBUS_A:
	157	case IRQ_NUBUS_B:
	158	case IRQ_NUBUS_C:
	159	case IRQ_NUBUS_D:
	160	case IRQ_NUBUS_E:
	161	irq -= NUBUS_SOURCE_BASE;
	162	oss->irq_level[irq] = OSS_IRQLEV_NUBUS;
da3fb3c9	163	return;
1da177e4	164	}
da3fb3c9 FT	165
	166	if (IRQ_SRC(irq) == 1)
	167	via_irq_enable(irq);
1da177e4 LT	168	}
	169
	170	/*
	171	* Disable an OSS interrupt
	172	*
	173	* Same as above except we set the source's interrupt level to zero,
	174	* to disable the interrupt.
	175	*/
	176
	177	void oss_irq_disable(int irq) {
1da177e4	178	switch(irq) {
80614e5a	179	case IRQ_MAC_SCC:
da3fb3c9 FT	180	oss->irq_level[OSS_IOPSCC] = 0;
da3fb3c9 FT	181	return;
1da177e4	182	case IRQ_MAC_ADB:
da3fb3c9 FT	183	oss->irq_level[OSS_IOPISM] = 0;
da3fb3c9 FT	184	return;
1da177e4	185	case IRQ_MAC_SCSI:
da3fb3c9 FT	186	oss->irq_level[OSS_SCSI] = 0;
da3fb3c9 FT	187	return;
1da177e4 LT	188	case IRQ_NUBUS_9:
	189	case IRQ_NUBUS_A:
	190	case IRQ_NUBUS_B:
	191	case IRQ_NUBUS_C:
	192	case IRQ_NUBUS_D:
	193	case IRQ_NUBUS_E:
	194	irq -= NUBUS_SOURCE_BASE;
da3fb3c9 FT	195	oss->irq_level[irq] = 0;
da3fb3c9 FT	196	return;
1da177e4	197	}
da3fb3c9 FT	198
	199	if (IRQ_SRC(irq) == 1)
	200	via_irq_disable(irq);
1da177e4	201	}