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1da177e4 LT |
1 | /***************************************************************************/ |
2 | ||
3 | /* | |
4 | * linux/arch/m68knommu/platform/5206/config.c | |
5 | * | |
6 | * Copyright (C) 1999-2002, Greg Ungerer (gerg@snapgear.com) | |
7 | * Copyright (C) 2000-2001, Lineo Inc. (www.lineo.com) | |
8 | */ | |
9 | ||
10 | /***************************************************************************/ | |
11 | ||
12 | #include <linux/config.h> | |
13 | #include <linux/kernel.h> | |
14 | #include <linux/sched.h> | |
15 | #include <linux/param.h> | |
16 | #include <linux/init.h> | |
17 | #include <linux/interrupt.h> | |
18 | #include <asm/irq.h> | |
19 | #include <asm/dma.h> | |
20 | #include <asm/traps.h> | |
21 | #include <asm/machdep.h> | |
22 | #include <asm/coldfire.h> | |
23 | #include <asm/mcftimer.h> | |
24 | #include <asm/mcfsim.h> | |
25 | #include <asm/mcfdma.h> | |
26 | ||
27 | /***************************************************************************/ | |
28 | ||
29 | void coldfire_tick(void); | |
30 | void coldfire_timer_init(irqreturn_t (*handler)(int, void *, struct pt_regs *)); | |
31 | unsigned long coldfire_timer_offset(void); | |
32 | void coldfire_trap_init(void); | |
33 | void coldfire_reset(void); | |
34 | ||
35 | /***************************************************************************/ | |
36 | ||
37 | /* | |
38 | * DMA channel base address table. | |
39 | */ | |
40 | unsigned int dma_base_addr[MAX_M68K_DMA_CHANNELS] = { | |
41 | MCF_MBAR + MCFDMA_BASE0, | |
42 | MCF_MBAR + MCFDMA_BASE1, | |
43 | }; | |
44 | ||
45 | unsigned int dma_device_address[MAX_M68K_DMA_CHANNELS]; | |
46 | ||
47 | /***************************************************************************/ | |
48 | ||
49 | void mcf_autovector(unsigned int vec) | |
50 | { | |
51 | volatile unsigned char *mbar; | |
52 | unsigned char icr; | |
53 | ||
54 | if ((vec >= 25) && (vec <= 31)) { | |
55 | vec -= 25; | |
56 | mbar = (volatile unsigned char *) MCF_MBAR; | |
57 | icr = MCFSIM_ICR_AUTOVEC | (vec << 3); | |
58 | *(mbar + MCFSIM_ICR1 + vec) = icr; | |
59 | vec = 0x1 << (vec + 1); | |
60 | mcf_setimr(mcf_getimr() & ~vec); | |
61 | } | |
62 | } | |
63 | ||
64 | /***************************************************************************/ | |
65 | ||
66 | void mcf_settimericr(unsigned int timer, unsigned int level) | |
67 | { | |
68 | volatile unsigned char *icrp; | |
69 | unsigned int icr, imr; | |
70 | ||
71 | if (timer <= 2) { | |
72 | switch (timer) { | |
73 | case 2: icr = MCFSIM_TIMER2ICR; imr = MCFSIM_IMR_TIMER2; break; | |
74 | default: icr = MCFSIM_TIMER1ICR; imr = MCFSIM_IMR_TIMER1; break; | |
75 | } | |
76 | ||
77 | icrp = (volatile unsigned char *) (MCF_MBAR + icr); | |
78 | *icrp = MCFSIM_ICR_AUTOVEC | (level << 2) | MCFSIM_ICR_PRI3; | |
79 | mcf_setimr(mcf_getimr() & ~imr); | |
80 | } | |
81 | } | |
82 | ||
83 | /***************************************************************************/ | |
84 | ||
85 | int mcf_timerirqpending(int timer) | |
86 | { | |
87 | unsigned int imr = 0; | |
88 | ||
89 | switch (timer) { | |
90 | case 1: imr = MCFSIM_IMR_TIMER1; break; | |
91 | case 2: imr = MCFSIM_IMR_TIMER2; break; | |
92 | default: break; | |
93 | } | |
94 | return (mcf_getipr() & imr); | |
95 | } | |
96 | ||
97 | /***************************************************************************/ | |
98 | ||
99 | void config_BSP(char *commandp, int size) | |
100 | { | |
101 | mcf_setimr(MCFSIM_IMR_MASKALL); | |
102 | ||
103 | #if defined(CONFIG_BOOTPARAM) | |
104 | strncpy(commandp, CONFIG_BOOTPARAM_STRING, size); | |
105 | commandp[size-1] = 0; | |
106 | #else | |
107 | memset(commandp, 0, size); | |
108 | #endif | |
109 | ||
110 | mach_sched_init = coldfire_timer_init; | |
111 | mach_tick = coldfire_tick; | |
112 | mach_gettimeoffset = coldfire_timer_offset; | |
113 | mach_trap_init = coldfire_trap_init; | |
114 | mach_reset = coldfire_reset; | |
115 | } | |
116 | ||
117 | /***************************************************************************/ |