[mirror_ubuntu-jammy-kernel.git] / arch / m68knommu / platform / 5307 / config.c

/***************************************************************************/

/*
 *	linux/arch/m68knommu/platform/5307/config.c
 *
 *	Copyright (C) 1999-2002, Greg Ungerer (gerg@snapgear.com)
 *	Copyright (C) 2000, Lineo (www.lineo.com)
 */

/***************************************************************************/

#include <linux/kernel.h>
#include <linux/param.h>
#include <linux/init.h>
#include <linux/io.h>
#include <asm/machdep.h>
#include <asm/coldfire.h>
#include <asm/mcfsim.h>
#include <asm/mcfuart.h>
#include <asm/mcfwdebug.h>

/***************************************************************************/

/*
 *	Some platforms need software versions of the GPIO data registers.
 */
unsigned short ppdata;
unsigned char ledbank = 0xff;

/***************************************************************************/

static struct mcf_platform_uart m5307_uart_platform[] = {
	{
		.mapbase	= MCF_MBAR + MCFUART_BASE1,
		.irq		= 73,
	},
	{
		.mapbase 	= MCF_MBAR + MCFUART_BASE2,
		.irq		= 74,
	},
	{ },
};

static struct platform_device m5307_uart = {
	.name			= "mcfuart",
	.id			= 0,
	.dev.platform_data	= m5307_uart_platform,
};

static struct platform_device *m5307_devices[] __initdata = {
	&m5307_uart,
};

/***************************************************************************/

static void __init m5307_uart_init_line(int line, int irq)
{
	if (line == 0) {
		writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI1, MCF_MBAR + MCFSIM_UART1ICR);
		writeb(irq, MCF_MBAR + MCFUART_BASE1 + MCFUART_UIVR);
		mcf_mapirq2imr(irq, MCFINTC_UART0);
	} else if (line == 1) {
		writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI2, MCF_MBAR + MCFSIM_UART2ICR);
		writeb(irq, MCF_MBAR + MCFUART_BASE2 + MCFUART_UIVR);
		mcf_mapirq2imr(irq, MCFINTC_UART1);
	}
}

static void __init m5307_uarts_init(void)
{
	const int nrlines = ARRAY_SIZE(m5307_uart_platform);
	int line;

	for (line = 0; (line < nrlines); line++)
		m5307_uart_init_line(line, m5307_uart_platform[line].irq);
}

/***************************************************************************/

static void __init m5307_timers_init(void)
{
	/* Timer1 is always used as system timer */
	writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI3,
		MCF_MBAR + MCFSIM_TIMER1ICR);
	mcf_mapirq2imr(MCF_IRQ_TIMER, MCFINTC_TIMER1);

#ifdef CONFIG_HIGHPROFILE
	/* Timer2 is to be used as a high speed profile timer  */
	writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3,
		MCF_MBAR + MCFSIM_TIMER2ICR);
	mcf_mapirq2imr(MCF_IRQ_PROFILER, MCFINTC_TIMER2);
#endif
}

/***************************************************************************/

void m5307_cpu_reset(void)
{
	local_irq_disable();
	/* Set watchdog to soft reset, and enabled */
	__raw_writeb(0xc0, MCF_MBAR + MCFSIM_SYPCR);
	for (;;)
		/* wait for watchdog to timeout */;
}

/***************************************************************************/

void __init config_BSP(char *commandp, int size)
{
#if defined(CONFIG_NETtel) || \
    defined(CONFIG_SECUREEDGEMP3) || defined(CONFIG_CLEOPATRA)
	/* Copy command line from FLASH to local buffer... */
	memcpy(commandp, (char *) 0xf0004000, size);
	commandp[size-1] = 0;
#endif

	mach_reset = m5307_cpu_reset;
	m5307_timers_init();
	m5307_uarts_init();

	/* Only support the external interrupts on their primary level */
	mcf_mapirq2imr(25, MCFINTC_EINT1);
	mcf_mapirq2imr(27, MCFINTC_EINT3);
	mcf_mapirq2imr(29, MCFINTC_EINT5);
	mcf_mapirq2imr(31, MCFINTC_EINT7);

#ifdef CONFIG_BDM_DISABLE
	/*
	 * Disable the BDM clocking.  This also turns off most of the rest of
	 * the BDM device.  This is good for EMC reasons. This option is not
	 * incompatible with the memory protection option.
	 */
	wdebug(MCFDEBUG_CSR, MCFDEBUG_CSR_PSTCLK);
#endif
}

/***************************************************************************/

static int __init init_BSP(void)
{
	platform_add_devices(m5307_devices, ARRAY_SIZE(m5307_devices));
	return 0;
}

arch_initcall(init_BSP);

/***************************************************************************/
Commit	Line	Data
1da177e4 LT	1	/***************************************************************************/
	2
	3	/*
	4	* linux/arch/m68knommu/platform/5307/config.c
	5	*
	6	* Copyright (C) 1999-2002, Greg Ungerer (gerg@snapgear.com)
	7	* Copyright (C) 2000, Lineo (www.lineo.com)
	8	*/
	9
	10	/***************************************************************************/
	11
1da177e4	12	#include <linux/kernel.h>
1da177e4 LT	13	#include <linux/param.h>
1da177e4 LT	14	#include <linux/init.h>
96db271a	15	#include <linux/io.h>
1da177e4 LT	16	#include <asm/machdep.h>
1da177e4 LT	17	#include <asm/coldfire.h>
1da177e4	18	#include <asm/mcfsim.h>
96db271a	19	#include <asm/mcfuart.h>
1da177e4 LT	20	#include <asm/mcfwdebug.h>
	21
	22	/***************************************************************************/
	23
1da177e4 LT	24	/*
	25	* Some platforms need software versions of the GPIO data registers.
	26	*/
	27	unsigned short ppdata;
	28	unsigned char ledbank = 0xff;
	29
	30	/***************************************************************************/
	31
96db271a GU	32	static struct mcf_platform_uart m5307_uart_platform[] = {
	33	{
	34	.mapbase = MCF_MBAR + MCFUART_BASE1,
	35	.irq = 73,
	36	},
	37	{
	38	.mapbase = MCF_MBAR + MCFUART_BASE2,
	39	.irq = 74,
	40	},
	41	{ },
	42	};
	43
	44	static struct platform_device m5307_uart = {
	45	.name = "mcfuart",
	46	.id = 0,
	47	.dev.platform_data = m5307_uart_platform,
1da177e4 LT	48	};
1da177e4 LT	49
96db271a GU	50	static struct platform_device *m5307_devices[] __initdata = {
	51	&m5307_uart,
	52	};
	53
	54	/***************************************************************************/
	55
	56	static void __init m5307_uart_init_line(int line, int irq)
	57	{
	58	if (line == 0) {
9242ef12 GU	59	writeb(MCFSIM_ICR_LEVEL6 \| MCFSIM_ICR_PRI1, MCF_MBAR + MCFSIM_UART1ICR);
9242ef12 GU	60	writeb(irq, MCF_MBAR + MCFUART_BASE1 + MCFUART_UIVR);
39f0fb6a	61	mcf_mapirq2imr(irq, MCFINTC_UART0);
96db271a	62	} else if (line == 1) {
9242ef12 GU	63	writeb(MCFSIM_ICR_LEVEL6 \| MCFSIM_ICR_PRI2, MCF_MBAR + MCFSIM_UART2ICR);
9242ef12 GU	64	writeb(irq, MCF_MBAR + MCFUART_BASE2 + MCFUART_UIVR);
39f0fb6a	65	mcf_mapirq2imr(irq, MCFINTC_UART1);
96db271a GU	66	}
	67	}
	68
	69	static void __init m5307_uarts_init(void)
	70	{
	71	const int nrlines = ARRAY_SIZE(m5307_uart_platform);
	72	int line;
	73
	74	for (line = 0; (line < nrlines); line++)
	75	m5307_uart_init_line(line, m5307_uart_platform[line].irq);
	76	}
1da177e4 LT	77
	78	/***************************************************************************/
	79
04b75b10	80	static void __init m5307_timers_init(void)
1da177e4	81	{
04b75b10 GU	82	/* Timer1 is always used as system timer */
	83	writeb(MCFSIM_ICR_AUTOVEC \| MCFSIM_ICR_LEVEL6 \| MCFSIM_ICR_PRI3,
	84	MCF_MBAR + MCFSIM_TIMER1ICR);
39f0fb6a	85	mcf_mapirq2imr(MCF_IRQ_TIMER, MCFINTC_TIMER1);
04b75b10 GU	86
	87	#ifdef CONFIG_HIGHPROFILE
	88	/* Timer2 is to be used as a high speed profile timer */
	89	writeb(MCFSIM_ICR_AUTOVEC \| MCFSIM_ICR_LEVEL7 \| MCFSIM_ICR_PRI3,
	90	MCF_MBAR + MCFSIM_TIMER2ICR);
39f0fb6a	91	mcf_mapirq2imr(MCF_IRQ_PROFILER, MCFINTC_TIMER2);
04b75b10	92	#endif
1da177e4 LT	93	}
	94
	95	/***************************************************************************/
	96
c18e52c7 GU	97	void m5307_cpu_reset(void)
	98	{
	99	local_irq_disable();
	100	/* Set watchdog to soft reset, and enabled */
	101	__raw_writeb(0xc0, MCF_MBAR + MCFSIM_SYPCR);
	102	for (;;)
	103	/* wait for watchdog to timeout */;
	104	}
	105
	106	/***************************************************************************/
	107
96db271a	108	void __init config_BSP(char *commandp, int size)
1da177e4	109	{
3947fca7	110	#if defined(CONFIG_NETtel) \|\| \
cff28b56	111	defined(CONFIG_SECUREEDGEMP3) \|\| defined(CONFIG_CLEOPATRA)
1da177e4 LT	112	/* Copy command line from FLASH to local buffer... */
	113	memcpy(commandp, (char *) 0xf0004000, size);
	114	commandp[size-1] = 0;
1da177e4 LT	115	#endif
1da177e4 LT	116
c18e52c7	117	mach_reset = m5307_cpu_reset;
04b75b10	118	m5307_timers_init();
39f0fb6a GU	119	m5307_uarts_init();
	120
	121	/* Only support the external interrupts on their primary level */
	122	mcf_mapirq2imr(25, MCFINTC_EINT1);
	123	mcf_mapirq2imr(27, MCFINTC_EINT3);
	124	mcf_mapirq2imr(29, MCFINTC_EINT5);
	125	mcf_mapirq2imr(31, MCFINTC_EINT7);
1da177e4	126
96db271a	127	#ifdef CONFIG_BDM_DISABLE
1da177e4 LT	128	/*
	129	* Disable the BDM clocking. This also turns off most of the rest of
	130	* the BDM device. This is good for EMC reasons. This option is not
	131	* incompatible with the memory protection option.
	132	*/
	133	wdebug(MCFDEBUG_CSR, MCFDEBUG_CSR_PSTCLK);
	134	#endif
	135	}
	136
	137	/***************************************************************************/
96db271a GU	138
	139	static int __init init_BSP(void)
	140	{
96db271a GU	141	platform_add_devices(m5307_devices, ARRAY_SIZE(m5307_devices));
	142	return 0;
	143	}
	144
	145	arch_initcall(init_BSP);
	146
	147	/***************************************************************************/