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1da177e4 LT |
1 | /* |
2 | * linux/arch/m68knommu/platform/68360/config.c | |
3 | * | |
4 | * Copyright (c) 2000 Michael Leslie <mleslie@lineo.com> | |
5 | * Copyright (C) 1993 Hamish Macdonald | |
6 | * Copyright (C) 1999 D. Jeff Dionne <jeff@uclinux.org> | |
7 | * | |
8 | * This file is subject to the terms and conditions of the GNU General Public | |
9 | * License. See the file COPYING in the main directory of this archive | |
10 | * for more details. | |
11 | */ | |
12 | ||
13 | #include <stdarg.h> | |
1da177e4 LT |
14 | #include <linux/types.h> |
15 | #include <linux/kernel.h> | |
16 | #include <linux/mm.h> | |
17 | #include <linux/tty.h> | |
18 | #include <linux/console.h> | |
19 | ||
20 | #include <asm/setup.h> | |
21 | #include <asm/system.h> | |
22 | #include <asm/pgtable.h> | |
23 | #include <asm/irq.h> | |
24 | #include <asm/machdep.h> | |
25 | #include <asm/m68360.h> | |
26 | ||
27 | #ifdef CONFIG_UCQUICC | |
28 | #include <asm/bootstd.h> | |
29 | #endif | |
30 | ||
31 | extern void m360_cpm_reset(void); | |
32 | ||
33 | // Mask to select if the PLL prescaler is enabled. | |
34 | #define MCU_PREEN ((unsigned short)(0x0001 << 13)) | |
35 | ||
36 | #if defined(CONFIG_UCQUICC) | |
37 | #define OSCILLATOR (unsigned long int)33000000 | |
38 | #endif | |
39 | ||
40 | unsigned long int system_clock; | |
41 | ||
42 | void M68360_init_IRQ(void); | |
43 | ||
44 | extern QUICC *pquicc; | |
45 | ||
46 | /* TODO DON"T Hard Code this */ | |
47 | /* calculate properly using the right PLL and prescaller */ | |
48 | // unsigned int system_clock = 33000000l; | |
49 | extern unsigned long int system_clock; //In kernel setup.c | |
50 | ||
51 | extern void config_M68360_irq(void); | |
52 | ||
53 | void BSP_sched_init(void (*timer_routine)(int, void *, struct pt_regs *)) | |
54 | { | |
55 | unsigned char prescaler; | |
56 | unsigned short tgcr_save; | |
57 | int return_value; | |
58 | ||
59 | #if 0 | |
60 | /* Restart mode, Enable int, 32KHz, Enable timer */ | |
61 | TCTL = TCTL_OM | TCTL_IRQEN | TCTL_CLKSOURCE_32KHZ | TCTL_TEN; | |
62 | /* Set prescaler (Divide 32KHz by 32)*/ | |
63 | TPRER = 31; | |
64 | /* Set compare register 32Khz / 32 / 10 = 100 */ | |
65 | TCMP = 10; | |
66 | ||
67 | request_irq(IRQ_MACHSPEC | 1, timer_routine, IRQ_FLG_LOCK, "timer", NULL); | |
68 | #endif | |
69 | ||
70 | /* General purpose quicc timers: MC68360UM p7-20 */ | |
71 | ||
72 | /* Set up timer 1 (in [1..4]) to do 100Hz */ | |
73 | tgcr_save = pquicc->timer_tgcr & 0xfff0; | |
74 | pquicc->timer_tgcr = tgcr_save; /* stop and reset timer 1 */ | |
75 | /* pquicc->timer_tgcr |= 0x4444; */ /* halt timers when FREEZE (ie bdm freeze) */ | |
76 | ||
77 | prescaler = 8; | |
78 | pquicc->timer_tmr1 = 0x001a | /* or=1, frr=1, iclk=01b */ | |
79 | (unsigned short)((prescaler - 1) << 8); | |
80 | ||
81 | pquicc->timer_tcn1 = 0x0000; /* initial count */ | |
82 | /* calculate interval for 100Hz based on the _system_clock: */ | |
83 | pquicc->timer_trr1 = (system_clock/ prescaler) / HZ; /* reference count */ | |
84 | ||
85 | pquicc->timer_ter1 = 0x0003; /* clear timer events */ | |
86 | ||
87 | /* enable timer 1 interrupt in CIMR */ | |
88 | // request_irq(IRQ_MACHSPEC | CPMVEC_TIMER1, timer_routine, IRQ_FLG_LOCK, "timer", NULL); | |
89 | //return_value = request_irq( CPMVEC_TIMER1, timer_routine, IRQ_FLG_LOCK, "timer", NULL); | |
90 | return_value = request_irq(CPMVEC_TIMER1 , timer_routine, IRQ_FLG_LOCK, | |
91 | "Timer", NULL); | |
92 | ||
93 | /* Start timer 1: */ | |
94 | tgcr_save = (pquicc->timer_tgcr & 0xfff0) | 0x0001; | |
95 | pquicc->timer_tgcr = tgcr_save; | |
96 | } | |
97 | ||
98 | ||
99 | void BSP_tick(void) | |
100 | { | |
101 | /* Reset Timer1 */ | |
102 | /* TSTAT &= 0; */ | |
103 | ||
104 | pquicc->timer_ter1 = 0x0002; /* clear timer event */ | |
105 | } | |
106 | ||
107 | unsigned long BSP_gettimeoffset (void) | |
108 | { | |
109 | return 0; | |
110 | } | |
111 | ||
112 | void BSP_gettod (int *yearp, int *monp, int *dayp, | |
113 | int *hourp, int *minp, int *secp) | |
114 | { | |
115 | } | |
116 | ||
117 | int BSP_hwclk(int op, struct hwclk_time *t) | |
118 | { | |
119 | if (!op) { | |
120 | /* read */ | |
121 | } else { | |
122 | /* write */ | |
123 | } | |
124 | return 0; | |
125 | } | |
126 | ||
127 | int BSP_set_clock_mmss (unsigned long nowtime) | |
128 | { | |
129 | #if 0 | |
130 | short real_seconds = nowtime % 60, real_minutes = (nowtime / 60) % 60; | |
131 | ||
132 | tod->second1 = real_seconds / 10; | |
133 | tod->second2 = real_seconds % 10; | |
134 | tod->minute1 = real_minutes / 10; | |
135 | tod->minute2 = real_minutes % 10; | |
136 | #endif | |
137 | return 0; | |
138 | } | |
139 | ||
140 | void BSP_reset (void) | |
141 | { | |
142 | local_irq_disable(); | |
bda65838 GU |
143 | asm volatile ( |
144 | "moveal #_start, %a0;\n" | |
145 | "moveb #0, 0xFFFFF300;\n" | |
146 | "moveal 0(%a0), %sp;\n" | |
147 | "moveal 4(%a0), %a0;\n" | |
148 | "jmp (%a0);\n" | |
149 | ); | |
1da177e4 LT |
150 | } |
151 | ||
152 | unsigned char *scc1_hwaddr; | |
153 | static int errno; | |
154 | ||
155 | #if defined (CONFIG_UCQUICC) | |
156 | _bsc0(char *, getserialnum) | |
157 | _bsc1(unsigned char *, gethwaddr, int, a) | |
158 | _bsc1(char *, getbenv, char *, a) | |
159 | #endif | |
160 | ||
161 | ||
162 | void config_BSP(char *command, int len) | |
163 | { | |
164 | unsigned char *p; | |
165 | ||
166 | m360_cpm_reset(); | |
167 | ||
168 | /* Calculate the real system clock value. */ | |
169 | { | |
170 | unsigned int local_pllcr = (unsigned int)(pquicc->sim_pllcr); | |
171 | if( local_pllcr & MCU_PREEN ) // If the prescaler is dividing by 128 | |
172 | { | |
173 | int mf = (int)(pquicc->sim_pllcr & 0x0fff); | |
174 | system_clock = (OSCILLATOR / 128) * (mf + 1); | |
175 | } | |
176 | else | |
177 | { | |
178 | int mf = (int)(pquicc->sim_pllcr & 0x0fff); | |
179 | system_clock = (OSCILLATOR) * (mf + 1); | |
180 | } | |
181 | } | |
182 | ||
183 | printk(KERN_INFO "\n68360 QUICC support (C) 2000 Lineo Inc.\n"); | |
184 | ||
185 | #if defined(CONFIG_UCQUICC) && 0 | |
186 | printk(KERN_INFO "uCquicc serial string [%s]\n",getserialnum()); | |
187 | p = scc1_hwaddr = gethwaddr(0); | |
188 | printk(KERN_INFO "uCquicc hwaddr %.2x:%.2x:%.2x:%.2x:%.2x:%.2x\n", | |
189 | p[0], p[1], p[2], p[3], p[4], p[5]); | |
190 | ||
191 | p = getbenv("APPEND"); | |
192 | if (p) | |
193 | strcpy(p,command); | |
194 | else | |
195 | command[0] = 0; | |
196 | #else | |
197 | scc1_hwaddr = "\00\01\02\03\04\05"; | |
198 | #endif | |
199 | ||
200 | mach_sched_init = BSP_sched_init; | |
201 | mach_tick = BSP_tick; | |
202 | mach_gettimeoffset = BSP_gettimeoffset; | |
203 | mach_gettod = BSP_gettod; | |
204 | mach_hwclk = NULL; | |
205 | mach_set_clock_mmss = NULL; | |
206 | mach_reset = BSP_reset; | |
207 | } |