[mirror_ubuntu-artful-kernel.git] / arch / m68knommu / platform / coldfire / intc-2.c

/*
 * intc-2.c
 *
 * General interrupt controller code for the many ColdFire cores that use
 * interrupt controllers with 63 interrupt sources, organized as 56 fully-
 * programmable + 7 fixed-level interrupt sources. This includes the 523x
 * family, the 5270, 5271, 5274, 5275, and the 528x family which have two such
 * controllers, and the 547x and 548x families which have only one of them.
 *
 * (C) Copyright 2009, Greg Ungerer <gerg@snapgear.com>
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file COPYING in the main directory of this archive
 * for more details.
 */

#include <linux/types.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <asm/coldfire.h>
#include <asm/mcfsim.h>
#include <asm/traps.h>

/*
 * Bit definitions for the ICR family of registers.
 */
#define MCFSIM_ICR_LEVEL(l)	((l)<<3)	/* Level l intr */
#define MCFSIM_ICR_PRI(p)	(p)		/* Priority p intr */

/*
 *	Each vector needs a unique priority and level associated with it.
 *	We don't really care so much what they are, we don't rely on the
 *	traditional priority interrupt scheme of the m68k/ColdFire.
 */
static u8 intc_intpri = MCFSIM_ICR_LEVEL(6) | MCFSIM_ICR_PRI(6);

#ifdef MCFICM_INTC1
#define NR_VECS	128
#else
#define NR_VECS	64
#endif

static void intc_irq_mask(unsigned int irq)
{
	if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECBASE + NR_VECS)) {
		unsigned long imraddr;
		u32 val, imrbit;

		irq -= MCFINT_VECBASE;
		imraddr = MCF_IPSBAR;
#ifdef MCFICM_INTC1
		imraddr += (irq & 0x40) ? MCFICM_INTC1 : MCFICM_INTC0;
#else
		imraddr += MCFICM_INTC0;
#endif
		imraddr += (irq & 0x20) ? MCFINTC_IMRH : MCFINTC_IMRL;
		imrbit = 0x1 << (irq & 0x1f);

		val = __raw_readl(imraddr);
		__raw_writel(val | imrbit, imraddr);
	}
}

static void intc_irq_unmask(unsigned int irq)
{
	if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECBASE + NR_VECS)) {
		unsigned long intaddr, imraddr, icraddr;
		u32 val, imrbit;

		irq -= MCFINT_VECBASE;
		intaddr = MCF_IPSBAR;
#ifdef MCFICM_INTC1
		intaddr += (irq & 0x40) ? MCFICM_INTC1 : MCFICM_INTC0;
#else
		intaddr += MCFICM_INTC0;
#endif
		imraddr = intaddr + ((irq & 0x20) ? MCFINTC_IMRH : MCFINTC_IMRL);
		icraddr = intaddr + MCFINTC_ICR0 + (irq & 0x3f);
		imrbit = 0x1 << (irq & 0x1f);

		/* Don't set the "maskall" bit! */
		if ((irq & 0x20) == 0)
			imrbit |= 0x1;

		if (__raw_readb(icraddr) == 0)
			__raw_writeb(intc_intpri--, icraddr);

		val = __raw_readl(imraddr);
		__raw_writel(val & ~imrbit, imraddr);
	}
}

static struct irq_chip intc_irq_chip = {
	.name		= "CF-INTC",
	.mask		= intc_irq_mask,
	.unmask		= intc_irq_unmask,
};

void __init init_IRQ(void)
{
	int irq;

	init_vectors();

	/* Mask all interrupt sources */
	__raw_writel(0x1, MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_IMRL);
#ifdef MCFICM_INTC1
	__raw_writel(0x1, MCF_IPSBAR + MCFICM_INTC1 + MCFINTC_IMRL);
#endif

	for (irq = 0; (irq < NR_IRQS); irq++) {
		irq_desc[irq].status = IRQ_DISABLED;
		irq_desc[irq].action = NULL;
		irq_desc[irq].depth = 1;
		irq_desc[irq].chip = &intc_irq_chip;
	}
}
Commit	Line	Data
2fba4f0b	1	/*
03cbc385 PDM	2	* intc-2.c
03cbc385 PDM	3	*
8851338d PDM	4	* General interrupt controller code for the many ColdFire cores that use
	5	* interrupt controllers with 63 interrupt sources, organized as 56 fully-
	6	* programmable + 7 fixed-level interrupt sources. This includes the 523x
	7	* family, the 5270, 5271, 5274, 5275, and the 528x family which have two such
	8	* controllers, and the 547x and 548x families which have only one of them.
2fba4f0b GU	9	*
	10	* (C) Copyright 2009, Greg Ungerer <gerg@snapgear.com>
	11	*
	12	* This file is subject to the terms and conditions of the GNU General Public
	13	* License. See the file COPYING in the main directory of this archive
	14	* for more details.
	15	*/
	16
	17	#include <linux/types.h>
	18	#include <linux/init.h>
	19	#include <linux/kernel.h>
	20	#include <linux/interrupt.h>
	21	#include <linux/irq.h>
	22	#include <linux/io.h>
	23	#include <asm/coldfire.h>
	24	#include <asm/mcfsim.h>
	25	#include <asm/traps.h>
	26
	27	/*
8851338d PDM	28	* Bit definitions for the ICR family of registers.
	29	*/
	30	#define MCFSIM_ICR_LEVEL(l) ((l)<<3) /* Level l intr */
	31	#define MCFSIM_ICR_PRI(p) (p) /* Priority p intr */
	32
	33	/*
	34	* Each vector needs a unique priority and level associated with it.
2fba4f0b	35	* We don't really care so much what they are, we don't rely on the
8851338d	36	* traditional priority interrupt scheme of the m68k/ColdFire.
2fba4f0b	37	*/
8851338d PDM	38	static u8 intc_intpri = MCFSIM_ICR_LEVEL(6) \| MCFSIM_ICR_PRI(6);
	39
	40	#ifdef MCFICM_INTC1
	41	#define NR_VECS 128
	42	#else
	43	#define NR_VECS 64
	44	#endif
2fba4f0b GU	45
	46	static void intc_irq_mask(unsigned int irq)
	47	{
8851338d	48	if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECBASE + NR_VECS)) {
2fba4f0b GU	49	unsigned long imraddr;
	50	u32 val, imrbit;
	51
	52	irq -= MCFINT_VECBASE;
	53	imraddr = MCF_IPSBAR;
8851338d	54	#ifdef MCFICM_INTC1
2fba4f0b	55	imraddr += (irq & 0x40) ? MCFICM_INTC1 : MCFICM_INTC0;
8851338d PDM	56	#else
	57	imraddr += MCFICM_INTC0;
	58	#endif
2fba4f0b GU	59	imraddr += (irq & 0x20) ? MCFINTC_IMRH : MCFINTC_IMRL;
	60	imrbit = 0x1 << (irq & 0x1f);
	61
	62	val = __raw_readl(imraddr);
	63	__raw_writel(val \| imrbit, imraddr);
	64	}
	65	}
	66
	67	static void intc_irq_unmask(unsigned int irq)
	68	{
8851338d	69	if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECBASE + NR_VECS)) {
2fba4f0b GU	70	unsigned long intaddr, imraddr, icraddr;
	71	u32 val, imrbit;
	72
	73	irq -= MCFINT_VECBASE;
	74	intaddr = MCF_IPSBAR;
8851338d	75	#ifdef MCFICM_INTC1
2fba4f0b	76	intaddr += (irq & 0x40) ? MCFICM_INTC1 : MCFICM_INTC0;
8851338d PDM	77	#else
	78	intaddr += MCFICM_INTC0;
	79	#endif
2fba4f0b GU	80	imraddr = intaddr + ((irq & 0x20) ? MCFINTC_IMRH : MCFINTC_IMRL);
	81	icraddr = intaddr + MCFINTC_ICR0 + (irq & 0x3f);
	82	imrbit = 0x1 << (irq & 0x1f);
	83
	84	/* Don't set the "maskall" bit! */
	85	if ((irq & 0x20) == 0)
	86	imrbit \|= 0x1;
	87
	88	if (__raw_readb(icraddr) == 0)
	89	__raw_writeb(intc_intpri--, icraddr);
	90
	91	val = __raw_readl(imraddr);
	92	__raw_writel(val & ~imrbit, imraddr);
	93	}
	94	}
	95
	96	static struct irq_chip intc_irq_chip = {
	97	.name = "CF-INTC",
	98	.mask = intc_irq_mask,
	99	.unmask = intc_irq_unmask,
	100	};
	101
	102	void __init init_IRQ(void)
	103	{
	104	int irq;
	105
	106	init_vectors();
	107
	108	/* Mask all interrupt sources */
	109	__raw_writel(0x1, MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_IMRL);
8851338d	110	#ifdef MCFICM_INTC1
2fba4f0b	111	__raw_writel(0x1, MCF_IPSBAR + MCFICM_INTC1 + MCFINTC_IMRL);
8851338d	112	#endif
2fba4f0b GU	113
	114	for (irq = 0; (irq < NR_IRQS); irq++) {
	115	irq_desc[irq].status = IRQ_DISABLED;
	116	irq_desc[irq].action = NULL;
	117	irq_desc[irq].depth = 1;
	118	irq_desc[irq].chip = &intc_irq_chip;
	119	}
	120	}
	121