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1/***************************************************************************/
2
3/*
4 * timers.c -- generic ColdFire hardware timer support.
5 *
a7f61fa4 6 * Copyright (C) 1999-2008, Greg Ungerer <gerg@snapgear.com>
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7 */
8
9/***************************************************************************/
10
1da177e4 11#include <linux/kernel.h>
2f2c2679 12#include <linux/init.h>
1da177e4 13#include <linux/sched.h>
1da177e4 14#include <linux/interrupt.h>
c52a2cda 15#include <linux/irq.h>
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16#include <linux/profile.h>
17#include <linux/clocksource.h>
0b7ac8e4 18#include <asm/io.h>
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19#include <asm/traps.h>
20#include <asm/machdep.h>
21#include <asm/coldfire.h>
22#include <asm/mcftimer.h>
23#include <asm/mcfsim.h>
24
25/***************************************************************************/
26
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27/*
28 * By default use timer1 as the system clock timer.
29 */
a7f61fa4 30#define FREQ (MCF_BUSCLK / 16)
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31#define TA(a) (MCF_MBAR + MCFTIMER_BASE1 + (a))
32
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33/*
34 * Default the timer and vector to use for ColdFire. Some ColdFire
35 * CPU's and some boards may want different. Their sub-architecture
36 * startup code (in config.c) can change these if they want.
37 */
38unsigned int mcf_timervector = 29;
39unsigned int mcf_profilevector = 31;
40unsigned int mcf_timerlevel = 5;
41
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42/*
43 * These provide the underlying interrupt vector support.
44 * Unfortunately it is a little different on each ColdFire.
45 */
46extern void mcf_settimericr(int timer, int level);
a7f61fa4 47void coldfire_profile_init(void);
1da177e4 48
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49#if defined(CONFIG_M532x)
50#define __raw_readtrr __raw_readl
51#define __raw_writetrr __raw_writel
52#else
53#define __raw_readtrr __raw_readw
54#define __raw_writetrr __raw_writew
55#endif
56
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57static u32 mcftmr_cycles_per_jiffy;
58static u32 mcftmr_cnt;
59
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60/***************************************************************************/
61
a7f61fa4 62static irqreturn_t mcftmr_tick(int irq, void *dummy)
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63{
64 /* Reset the ColdFire timer */
0b7ac8e4 65 __raw_writeb(MCFTIMER_TER_CAP | MCFTIMER_TER_REF, TA(MCFTIMER_TER));
2f2c2679 66
a7f61fa4 67 mcftmr_cnt += mcftmr_cycles_per_jiffy;
2f2c2679 68 return arch_timer_interrupt(irq, dummy);
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69}
70
71/***************************************************************************/
72
a7f61fa4 73static struct irqaction mcftmr_timer_irq = {
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74 .name = "timer",
75 .flags = IRQF_DISABLED | IRQF_TIMER,
a7f61fa4 76 .handler = mcftmr_tick,
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77};
78
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79/***************************************************************************/
80
8e19608e 81static cycle_t mcftmr_read_clk(struct clocksource *cs)
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82{
83 unsigned long flags;
84 u32 cycles;
85 u16 tcn;
86
87 local_irq_save(flags);
88 tcn = __raw_readw(TA(MCFTIMER_TCN));
89 cycles = mcftmr_cnt;
90 local_irq_restore(flags);
91
92 return cycles + tcn;
93}
94
95/***************************************************************************/
96
97static struct clocksource mcftmr_clk = {
98 .name = "tmr",
99 .rating = 250,
100 .read = mcftmr_read_clk,
101 .shift = 20,
102 .mask = CLOCKSOURCE_MASK(32),
103 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
104};
105
106/***************************************************************************/
4342f4ac 107
2f2c2679 108void hw_timer_init(void)
1da177e4 109{
a7f61fa4 110 setup_irq(mcf_timervector, &mcftmr_timer_irq);
c52a2cda 111
0b7ac8e4 112 __raw_writew(MCFTIMER_TMR_DISABLE, TA(MCFTIMER_TMR));
a7f61fa4 113 mcftmr_cycles_per_jiffy = FREQ / HZ;
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114 /*
115 * The coldfire timer runs from 0 to TRR included, then 0
116 * again and so on. It counts thus actually TRR + 1 steps
117 * for 1 tick, not TRR. So if you want n cycles,
118 * initialize TRR with n - 1.
119 */
120 __raw_writetrr(mcftmr_cycles_per_jiffy - 1, TA(MCFTIMER_TRR));
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121 __raw_writew(MCFTIMER_TMR_ENORI | MCFTIMER_TMR_CLK16 |
122 MCFTIMER_TMR_RESTART | MCFTIMER_TMR_ENABLE, TA(MCFTIMER_TMR));
1da177e4 123
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124 mcftmr_clk.mult = clocksource_hz2mult(FREQ, mcftmr_clk.shift);
125 clocksource_register(&mcftmr_clk);
126
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127 mcf_settimericr(1, mcf_timerlevel);
128
129#ifdef CONFIG_HIGHPROFILE
130 coldfire_profile_init();
131#endif
132}
133
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134/***************************************************************************/
135#ifdef CONFIG_HIGHPROFILE
136/***************************************************************************/
137
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138/*
139 * By default use timer2 as the profiler clock timer.
140 */
141#define PA(a) (MCF_MBAR + MCFTIMER_BASE2 + (a))
142
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143/*
144 * Choose a reasonably fast profile timer. Make it an odd value to
d08df601 145 * try and get good coverage of kernel operations.
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146 */
147#define PROFILEHZ 1013
148
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149/*
150 * Use the other timer to provide high accuracy profiling info.
151 */
c051b011 152irqreturn_t coldfire_profile_tick(int irq, void *dummy)
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153{
154 /* Reset ColdFire timer2 */
0b7ac8e4 155 __raw_writeb(MCFTIMER_TER_CAP | MCFTIMER_TER_REF, PA(MCFTIMER_TER));
1da177e4 156 if (current->pid)
6ef1e567 157 profile_tick(CPU_PROFILING);
c051b011 158 return IRQ_HANDLED;
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159}
160
161/***************************************************************************/
162
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163static struct irqaction coldfire_profile_irq = {
164 .name = "profile timer",
165 .flags = IRQF_DISABLED | IRQF_TIMER,
166 .handler = coldfire_profile_tick,
167};
168
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169void coldfire_profile_init(void)
170{
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171 printk(KERN_INFO "PROFILE: lodging TIMER2 @ %dHz as profile timer\n",
172 PROFILEHZ);
173
174 setup_irq(mcf_profilevector, &coldfire_profile_irq);
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175
176 /* Set up TIMER 2 as high speed profile clock */
0b7ac8e4 177 __raw_writew(MCFTIMER_TMR_DISABLE, PA(MCFTIMER_TMR));
1da177e4 178
6ef1e567 179 __raw_writetrr(((MCF_BUSCLK / 16) / PROFILEHZ), PA(MCFTIMER_TRR));
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180 __raw_writew(MCFTIMER_TMR_ENORI | MCFTIMER_TMR_CLK16 |
181 MCFTIMER_TMR_RESTART | MCFTIMER_TMR_ENABLE, PA(MCFTIMER_TMR));
1da177e4 182
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183 mcf_settimericr(2, 7);
184}
185
186/***************************************************************************/
187#endif /* CONFIG_HIGHPROFILE */
188/***************************************************************************/