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[mirror_ubuntu-jammy-kernel.git] / arch / m68knommu / platform / coldfire / timers.c
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1/***************************************************************************/
2
3/*
4 * timers.c -- generic ColdFire hardware timer support.
5 *
a7f61fa4 6 * Copyright (C) 1999-2008, Greg Ungerer <gerg@snapgear.com>
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7 */
8
9/***************************************************************************/
10
1da177e4 11#include <linux/kernel.h>
2f2c2679 12#include <linux/init.h>
1da177e4 13#include <linux/sched.h>
1da177e4 14#include <linux/interrupt.h>
c52a2cda 15#include <linux/irq.h>
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16#include <linux/profile.h>
17#include <linux/clocksource.h>
0b7ac8e4 18#include <asm/io.h>
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19#include <asm/traps.h>
20#include <asm/machdep.h>
21#include <asm/coldfire.h>
22#include <asm/mcftimer.h>
23#include <asm/mcfsim.h>
24
25/***************************************************************************/
26
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27/*
28 * By default use timer1 as the system clock timer.
29 */
a7f61fa4 30#define FREQ (MCF_BUSCLK / 16)
58f0ac98 31#define TA(a) (MCFTIMER_BASE1 + (a))
0b7ac8e4 32
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33/*
34 * These provide the underlying interrupt vector support.
35 * Unfortunately it is a little different on each ColdFire.
36 */
a7f61fa4 37void coldfire_profile_init(void);
1da177e4 38
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39#if defined(CONFIG_M532x)
40#define __raw_readtrr __raw_readl
41#define __raw_writetrr __raw_writel
42#else
43#define __raw_readtrr __raw_readw
44#define __raw_writetrr __raw_writew
45#endif
46
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47static u32 mcftmr_cycles_per_jiffy;
48static u32 mcftmr_cnt;
49
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50/***************************************************************************/
51
a7f61fa4 52static irqreturn_t mcftmr_tick(int irq, void *dummy)
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53{
54 /* Reset the ColdFire timer */
0b7ac8e4 55 __raw_writeb(MCFTIMER_TER_CAP | MCFTIMER_TER_REF, TA(MCFTIMER_TER));
2f2c2679 56
a7f61fa4 57 mcftmr_cnt += mcftmr_cycles_per_jiffy;
2f2c2679 58 return arch_timer_interrupt(irq, dummy);
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59}
60
61/***************************************************************************/
62
a7f61fa4 63static struct irqaction mcftmr_timer_irq = {
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64 .name = "timer",
65 .flags = IRQF_DISABLED | IRQF_TIMER,
a7f61fa4 66 .handler = mcftmr_tick,
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67};
68
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69/***************************************************************************/
70
8e19608e 71static cycle_t mcftmr_read_clk(struct clocksource *cs)
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72{
73 unsigned long flags;
74 u32 cycles;
75 u16 tcn;
76
77 local_irq_save(flags);
78 tcn = __raw_readw(TA(MCFTIMER_TCN));
79 cycles = mcftmr_cnt;
80 local_irq_restore(flags);
81
82 return cycles + tcn;
83}
84
85/***************************************************************************/
86
87static struct clocksource mcftmr_clk = {
88 .name = "tmr",
89 .rating = 250,
90 .read = mcftmr_read_clk,
91 .shift = 20,
92 .mask = CLOCKSOURCE_MASK(32),
93 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
94};
95
96/***************************************************************************/
4342f4ac 97
2f2c2679 98void hw_timer_init(void)
1da177e4 99{
0b7ac8e4 100 __raw_writew(MCFTIMER_TMR_DISABLE, TA(MCFTIMER_TMR));
a7f61fa4 101 mcftmr_cycles_per_jiffy = FREQ / HZ;
6c38d857
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102 /*
103 * The coldfire timer runs from 0 to TRR included, then 0
104 * again and so on. It counts thus actually TRR + 1 steps
105 * for 1 tick, not TRR. So if you want n cycles,
106 * initialize TRR with n - 1.
107 */
108 __raw_writetrr(mcftmr_cycles_per_jiffy - 1, TA(MCFTIMER_TRR));
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109 __raw_writew(MCFTIMER_TMR_ENORI | MCFTIMER_TMR_CLK16 |
110 MCFTIMER_TMR_RESTART | MCFTIMER_TMR_ENABLE, TA(MCFTIMER_TMR));
1da177e4 111
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112 mcftmr_clk.mult = clocksource_hz2mult(FREQ, mcftmr_clk.shift);
113 clocksource_register(&mcftmr_clk);
114
3945ca0f 115 setup_irq(MCF_IRQ_TIMER, &mcftmr_timer_irq);
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116
117#ifdef CONFIG_HIGHPROFILE
118 coldfire_profile_init();
119#endif
120}
121
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122/***************************************************************************/
123#ifdef CONFIG_HIGHPROFILE
124/***************************************************************************/
125
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126/*
127 * By default use timer2 as the profiler clock timer.
128 */
58f0ac98 129#define PA(a) (MCFTIMER_BASE2 + (a))
0b7ac8e4 130
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131/*
132 * Choose a reasonably fast profile timer. Make it an odd value to
d08df601 133 * try and get good coverage of kernel operations.
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134 */
135#define PROFILEHZ 1013
136
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137/*
138 * Use the other timer to provide high accuracy profiling info.
139 */
c051b011 140irqreturn_t coldfire_profile_tick(int irq, void *dummy)
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141{
142 /* Reset ColdFire timer2 */
0b7ac8e4 143 __raw_writeb(MCFTIMER_TER_CAP | MCFTIMER_TER_REF, PA(MCFTIMER_TER));
1da177e4 144 if (current->pid)
6ef1e567 145 profile_tick(CPU_PROFILING);
c051b011 146 return IRQ_HANDLED;
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147}
148
149/***************************************************************************/
150
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151static struct irqaction coldfire_profile_irq = {
152 .name = "profile timer",
153 .flags = IRQF_DISABLED | IRQF_TIMER,
154 .handler = coldfire_profile_tick,
155};
156
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157void coldfire_profile_init(void)
158{
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159 printk(KERN_INFO "PROFILE: lodging TIMER2 @ %dHz as profile timer\n",
160 PROFILEHZ);
161
1da177e4 162 /* Set up TIMER 2 as high speed profile clock */
0b7ac8e4 163 __raw_writew(MCFTIMER_TMR_DISABLE, PA(MCFTIMER_TMR));
1da177e4 164
6ef1e567 165 __raw_writetrr(((MCF_BUSCLK / 16) / PROFILEHZ), PA(MCFTIMER_TRR));
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166 __raw_writew(MCFTIMER_TMR_ENORI | MCFTIMER_TMR_CLK16 |
167 MCFTIMER_TMR_RESTART | MCFTIMER_TMR_ENABLE, PA(MCFTIMER_TMR));
1da177e4 168
3945ca0f 169 setup_irq(MCF_IRQ_PROFILER, &coldfire_profile_irq);
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170}
171
172/***************************************************************************/
173#endif /* CONFIG_HIGHPROFILE */
174/***************************************************************************/