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Commit | Line | Data |
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5633004c JH |
1 | choice |
2 | prompt "SoC Type" | |
3 | default META21_FPGA | |
4 | ||
5 | config META12_FPGA | |
6 | bool "Meta 1.2 FPGA" | |
7 | select METAG_META12 | |
8 | help | |
9 | This is a Meta 1.2 FPGA bitstream, just a bare CPU. | |
10 | ||
11 | config META21_FPGA | |
12 | bool "Meta 2.1 FPGA" | |
13 | select METAG_META21 | |
14 | help | |
15 | This is a Meta 2.1 FPGA bitstream, just a bare CPU. | |
16 | ||
c24d2976 JH |
17 | config SOC_TZ1090 |
18 | bool "Toumaz Xenif TZ1090 SoC (Comet)" | |
0a6923f1 | 19 | select IMGPDC_IRQ |
c24d2976 JH |
20 | select METAG_LNKGET_AROUND_CACHE |
21 | select METAG_META21 | |
22 | select METAG_SMP_WRITE_REORDERING | |
9630fa9f JH |
23 | select PINCTRL |
24 | select PINCTRL_TZ1090 | |
5a88130a | 25 | select PINCTRL_TZ1090_PDC |
c24d2976 JH |
26 | help |
27 | This is a Toumaz Technology Xenif TZ1090 (A.K.A. Comet) SoC containing | |
28 | a 2-threaded HTP. | |
29 | ||
5633004c JH |
30 | endchoice |
31 | ||
32 | menu "SoC configuration" | |
33 | ||
34 | if METAG_META21 | |
35 | ||
36 | # Meta 2.x specific options | |
37 | ||
38 | config METAG_META21_MMU | |
39 | bool "Meta 2.x MMU mode" | |
40 | default y | |
41 | help | |
42 | Use the Meta 2.x MMU in extended mode. | |
43 | ||
44 | config METAG_UNALIGNED | |
45 | bool "Meta 2.x unaligned access checking" | |
46 | default y | |
47 | help | |
48 | All memory accesses will be checked for alignment and an exception | |
49 | raised on unaligned accesses. This feature does cost performance | |
50 | but without it there will be no notification of this type of error. | |
51 | ||
52 | config METAG_USER_TCM | |
53 | bool "Meta on-chip memory support for userland" | |
54 | select GENERIC_ALLOCATOR | |
55 | default y | |
56 | help | |
57 | Allow the on-chip memories of Meta SoCs to be used by user | |
58 | applications. | |
59 | ||
60 | endif | |
61 | ||
62 | config METAG_HALT_ON_PANIC | |
63 | bool "Halt the core on panic" | |
64 | help | |
65 | Halt the core when a panic occurs. This is useful when running | |
66 | pre-production silicon or in an FPGA environment. | |
67 | ||
68 | endmenu |