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ccfe27d7 MS |
1 | /* |
2 | * Copyright (C) 2009-2010 PetaLogix | |
3 | * Copyright (C) 2006 Benjamin Herrenschmidt, IBM Corporation | |
4 | * | |
5 | * Provide default implementations of the DMA mapping callbacks for | |
6 | * directly mapped busses. | |
7 | */ | |
8 | ||
9 | #include <linux/device.h> | |
10 | #include <linux/dma-mapping.h> | |
5a0e3ad6 | 11 | #include <linux/gfp.h> |
ccfe27d7 | 12 | #include <linux/dma-debug.h> |
66421a64 | 13 | #include <linux/export.h> |
6bd55f0b | 14 | #include <linux/bug.h> |
ccfe27d7 | 15 | |
1be53e08 MS |
16 | #define NOT_COHERENT_CACHE |
17 | ||
18 | static void *dma_direct_alloc_coherent(struct device *dev, size_t size, | |
988624ec | 19 | dma_addr_t *dma_handle, gfp_t flag, |
00085f1e | 20 | unsigned long attrs) |
ccfe27d7 | 21 | { |
1be53e08 MS |
22 | #ifdef NOT_COHERENT_CACHE |
23 | return consistent_alloc(flag, size, dma_handle); | |
24 | #else | |
ccfe27d7 MS |
25 | void *ret; |
26 | struct page *page; | |
27 | int node = dev_to_node(dev); | |
28 | ||
29 | /* ignore region specifiers */ | |
30 | flag &= ~(__GFP_HIGHMEM); | |
31 | ||
32 | page = alloc_pages_node(node, flag, get_order(size)); | |
33 | if (page == NULL) | |
34 | return NULL; | |
35 | ret = page_address(page); | |
36 | memset(ret, 0, size); | |
193bca59 | 37 | *dma_handle = virt_to_phys(ret); |
ccfe27d7 MS |
38 | |
39 | return ret; | |
1be53e08 | 40 | #endif |
ccfe27d7 MS |
41 | } |
42 | ||
1be53e08 | 43 | static void dma_direct_free_coherent(struct device *dev, size_t size, |
988624ec | 44 | void *vaddr, dma_addr_t dma_handle, |
00085f1e | 45 | unsigned long attrs) |
ccfe27d7 | 46 | { |
1be53e08 | 47 | #ifdef NOT_COHERENT_CACHE |
f1525765 | 48 | consistent_free(size, vaddr); |
1be53e08 | 49 | #else |
ccfe27d7 | 50 | free_pages((unsigned long)vaddr, get_order(size)); |
1be53e08 | 51 | #endif |
ccfe27d7 MS |
52 | } |
53 | ||
54 | static int dma_direct_map_sg(struct device *dev, struct scatterlist *sgl, | |
55 | int nents, enum dma_data_direction direction, | |
00085f1e | 56 | unsigned long attrs) |
ccfe27d7 MS |
57 | { |
58 | struct scatterlist *sg; | |
59 | int i; | |
60 | ||
d79f3b06 | 61 | /* FIXME this part of code is untested */ |
ccfe27d7 | 62 | for_each_sg(sgl, sg, nents, i) { |
193bca59 | 63 | sg->dma_address = sg_phys(sg); |
98ac2fc2 AD |
64 | |
65 | if (attrs & DMA_ATTR_SKIP_CPU_SYNC) | |
66 | continue; | |
67 | ||
3e6110fd DW |
68 | __dma_sync(page_to_phys(sg_page(sg)) + sg->offset, |
69 | sg->length, direction); | |
ccfe27d7 MS |
70 | } |
71 | ||
72 | return nents; | |
73 | } | |
74 | ||
ccfe27d7 MS |
75 | static int dma_direct_dma_supported(struct device *dev, u64 mask) |
76 | { | |
77 | return 1; | |
78 | } | |
79 | ||
80 | static inline dma_addr_t dma_direct_map_page(struct device *dev, | |
81 | struct page *page, | |
82 | unsigned long offset, | |
83 | size_t size, | |
2549edd3 | 84 | enum dma_data_direction direction, |
00085f1e | 85 | unsigned long attrs) |
ccfe27d7 | 86 | { |
98ac2fc2 AD |
87 | if (!(attrs & DMA_ATTR_SKIP_CPU_SYNC)) |
88 | __dma_sync(page_to_phys(page) + offset, size, direction); | |
193bca59 | 89 | return page_to_phys(page) + offset; |
ccfe27d7 MS |
90 | } |
91 | ||
92 | static inline void dma_direct_unmap_page(struct device *dev, | |
93 | dma_addr_t dma_address, | |
94 | size_t size, | |
95 | enum dma_data_direction direction, | |
00085f1e | 96 | unsigned long attrs) |
ccfe27d7 | 97 | { |
d79f3b06 MS |
98 | /* There is not necessary to do cache cleanup |
99 | * | |
100 | * phys_to_virt is here because in __dma_sync_page is __virt_to_phys and | |
101 | * dma_address is physical address | |
102 | */ | |
98ac2fc2 AD |
103 | if (!(attrs & DMA_ATTR_SKIP_CPU_SYNC)) |
104 | __dma_sync(dma_address, size, direction); | |
ccfe27d7 MS |
105 | } |
106 | ||
0fb2a6f2 EB |
107 | static inline void |
108 | dma_direct_sync_single_for_cpu(struct device *dev, | |
109 | dma_addr_t dma_handle, size_t size, | |
110 | enum dma_data_direction direction) | |
111 | { | |
112 | /* | |
113 | * It's pointless to flush the cache as the memory segment | |
114 | * is given to the CPU | |
115 | */ | |
116 | ||
117 | if (direction == DMA_FROM_DEVICE) | |
118 | __dma_sync(dma_handle, size, direction); | |
119 | } | |
120 | ||
121 | static inline void | |
122 | dma_direct_sync_single_for_device(struct device *dev, | |
123 | dma_addr_t dma_handle, size_t size, | |
124 | enum dma_data_direction direction) | |
125 | { | |
126 | /* | |
127 | * It's pointless to invalidate the cache if the device isn't | |
128 | * supposed to write to the relevant region | |
129 | */ | |
130 | ||
131 | if (direction == DMA_TO_DEVICE) | |
132 | __dma_sync(dma_handle, size, direction); | |
133 | } | |
134 | ||
135 | static inline void | |
136 | dma_direct_sync_sg_for_cpu(struct device *dev, | |
137 | struct scatterlist *sgl, int nents, | |
138 | enum dma_data_direction direction) | |
139 | { | |
140 | struct scatterlist *sg; | |
141 | int i; | |
142 | ||
143 | /* FIXME this part of code is untested */ | |
144 | if (direction == DMA_FROM_DEVICE) | |
145 | for_each_sg(sgl, sg, nents, i) | |
146 | __dma_sync(sg->dma_address, sg->length, direction); | |
147 | } | |
148 | ||
149 | static inline void | |
150 | dma_direct_sync_sg_for_device(struct device *dev, | |
151 | struct scatterlist *sgl, int nents, | |
152 | enum dma_data_direction direction) | |
153 | { | |
154 | struct scatterlist *sg; | |
155 | int i; | |
156 | ||
157 | /* FIXME this part of code is untested */ | |
158 | if (direction == DMA_TO_DEVICE) | |
159 | for_each_sg(sgl, sg, nents, i) | |
160 | __dma_sync(sg->dma_address, sg->length, direction); | |
161 | } | |
162 | ||
55ae2f3b | 163 | static |
3a8e3265 LPC |
164 | int dma_direct_mmap_coherent(struct device *dev, struct vm_area_struct *vma, |
165 | void *cpu_addr, dma_addr_t handle, size_t size, | |
00085f1e | 166 | unsigned long attrs) |
3a8e3265 LPC |
167 | { |
168 | #ifdef CONFIG_MMU | |
169 | unsigned long user_count = (vma->vm_end - vma->vm_start) >> PAGE_SHIFT; | |
170 | unsigned long count = PAGE_ALIGN(size) >> PAGE_SHIFT; | |
171 | unsigned long off = vma->vm_pgoff; | |
172 | unsigned long pfn; | |
173 | ||
174 | if (off >= count || user_count > (count - off)) | |
175 | return -ENXIO; | |
176 | ||
177 | #ifdef NOT_COHERENT_CACHE | |
178 | vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); | |
179 | pfn = consistent_virt_to_pfn(cpu_addr); | |
180 | #else | |
181 | pfn = virt_to_pfn(cpu_addr); | |
182 | #endif | |
183 | return remap_pfn_range(vma, vma->vm_start, pfn + off, | |
184 | vma->vm_end - vma->vm_start, vma->vm_page_prot); | |
185 | #else | |
186 | return -ENXIO; | |
187 | #endif | |
188 | } | |
189 | ||
ccfe27d7 | 190 | struct dma_map_ops dma_direct_ops = { |
988624ec AP |
191 | .alloc = dma_direct_alloc_coherent, |
192 | .free = dma_direct_free_coherent, | |
3a8e3265 | 193 | .mmap = dma_direct_mmap_coherent, |
ccfe27d7 | 194 | .map_sg = dma_direct_map_sg, |
ccfe27d7 MS |
195 | .dma_supported = dma_direct_dma_supported, |
196 | .map_page = dma_direct_map_page, | |
197 | .unmap_page = dma_direct_unmap_page, | |
0fb2a6f2 EB |
198 | .sync_single_for_cpu = dma_direct_sync_single_for_cpu, |
199 | .sync_single_for_device = dma_direct_sync_single_for_device, | |
200 | .sync_sg_for_cpu = dma_direct_sync_sg_for_cpu, | |
201 | .sync_sg_for_device = dma_direct_sync_sg_for_device, | |
ccfe27d7 MS |
202 | }; |
203 | EXPORT_SYMBOL(dma_direct_ops); | |
204 | ||
205 | /* Number of entries preallocated for DMA-API debugging */ | |
206 | #define PREALLOC_DMA_DEBUG_ENTRIES (1 << 16) | |
207 | ||
208 | static int __init dma_init(void) | |
209 | { | |
6bd55f0b | 210 | dma_debug_init(PREALLOC_DMA_DEBUG_ENTRIES); |
ccfe27d7 | 211 | |
6bd55f0b | 212 | return 0; |
ccfe27d7 MS |
213 | } |
214 | fs_initcall(dma_init); |