[mirror_ubuntu-artful-kernel.git] / arch / microblaze / kernel / head.S

/*
 * Copyright (C) 2007-2009 Michal Simek <monstr@monstr.eu>
 * Copyright (C) 2007-2009 PetaLogix
 * Copyright (C) 2006 Atmark Techno, Inc.
 *
 * MMU code derived from arch/ppc/kernel/head_4xx.S:
 *    Copyright (c) 1995-1996 Gary Thomas <gdt@linuxppc.org>
 *      Initial PowerPC version.
 *    Copyright (c) 1996 Cort Dougan <cort@cs.nmt.edu>
 *      Rewritten for PReP
 *    Copyright (c) 1996 Paul Mackerras <paulus@cs.anu.edu.au>
 *      Low-level exception handers, MMU support, and rewrite.
 *    Copyright (c) 1997 Dan Malek <dmalek@jlc.net>
 *      PowerPC 8xx modifications.
 *    Copyright (c) 1998-1999 TiVo, Inc.
 *      PowerPC 403GCX modifications.
 *    Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu>
 *      PowerPC 403GCX/405GP modifications.
 *    Copyright 2000 MontaVista Software Inc.
 *	PPC405 modifications
 *      PowerPC 403GCX/405GP modifications.
 * 	Author: MontaVista Software, Inc.
 *         	frank_rowand@mvista.com or source@mvista.com
 * 	   	debbie_chu@mvista.com
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License. See the file "COPYING" in the main directory of this archive
 * for more details.
 */

#include <linux/init.h>
#include <linux/linkage.h>
#include <asm/thread_info.h>
#include <asm/page.h>
#include <linux/of_fdt.h>		/* for OF_DT_HEADER */

#ifdef CONFIG_MMU
#include <asm/setup.h> /* COMMAND_LINE_SIZE */
#include <asm/mmu.h>
#include <asm/processor.h>

.data
.global empty_zero_page
.align 12
empty_zero_page:
	.space	PAGE_SIZE
.global swapper_pg_dir
swapper_pg_dir:
	.space	PAGE_SIZE

#endif /* CONFIG_MMU */

	__HEAD
ENTRY(_start)
#if CONFIG_KERNEL_BASE_ADDR == 0
	brai	TOPHYS(real_start)
	.org	0x100
real_start:
#endif

	mfs	r1, rmsr
	andi	r1, r1, ~2
	mts	rmsr, r1
/*
 * According to Xilinx, msrclr instruction behaves like 'mfs rX,rpc'
 * if the msrclr instruction is not enabled. We use this to detect
 * if the opcode is available, by issuing msrclr and then testing the result.
 * r8 == 0 - msr instructions are implemented
 * r8 != 0 - msr instructions are not implemented
 */
	msrclr	r8, 0 /* clear nothing - just read msr for test */
	cmpu	r8, r8, r1 /* r1 must contain msr reg content */

/* r7 may point to an FDT, or there may be one linked in.
   if it's in r7, we've got to save it away ASAP.
   We ensure r7 points to a valid FDT, just in case the bootloader
   is broken or non-existent */
	beqi	r7, no_fdt_arg			/* NULL pointer?  don't copy */
/* Does r7 point to a valid FDT? Load HEADER magic number */
	/* Run time Big/Little endian platform */
	/* Save 1 as word and load byte - 0 - BIG, 1 - LITTLE */
	addik	r11, r0, 0x1 /* BIG/LITTLE checking value */
	/* __bss_start will be zeroed later - it is just temp location */
	swi	r11, r0, TOPHYS(__bss_start)
	lbui	r11, r0, TOPHYS(__bss_start)
	beqid	r11, big_endian /* DO NOT break delay stop dependency */
	lw	r11, r0, r7 /* Big endian load in delay slot */
	lwr	r11, r0, r7 /* Little endian load */
big_endian:
	rsubi	r11, r11, OF_DT_HEADER	/* Check FDT header */
	beqi	r11, _prepare_copy_fdt
	or	r7, r0, r0		/* clear R7 when not valid DTB */
	bnei	r11, no_fdt_arg			/* No - get out of here */
_prepare_copy_fdt:
	or	r11, r0, r0 /* incremment */
	ori	r4, r0, TOPHYS(_fdt_start)
	ori	r3, r0, (0x4000 - 4)
_copy_fdt:
	lw	r12, r7, r11 /* r12 = r7 + r11 */
	sw	r12, r4, r11 /* addr[r4 + r11] = r12 */
	addik	r11, r11, 4 /* increment counting */
	bgtid	r3, _copy_fdt /* loop for all entries */
	addik	r3, r3, -4 /* descrement loop */
no_fdt_arg:

#ifdef CONFIG_MMU

#ifndef CONFIG_CMDLINE_BOOL
/*
 * handling command line
 * copy command line to __init_end. There is space for storing command line.
 */
	or	r6, r0, r0		/* incremment */
	ori	r4, r0, __init_end	/* load address of command line */
	tophys(r4,r4)			/* convert to phys address */
	ori	r3, r0, COMMAND_LINE_SIZE - 1 /* number of loops */
_copy_command_line:
	lbu	r2, r5, r6 /* r2=r5+r6 - r5 contain pointer to command line */
	sb	r2, r4, r6		/* addr[r4+r6]= r2*/
	addik	r6, r6, 1		/* increment counting */
	bgtid	r3, _copy_command_line	/* loop for all entries       */
	addik	r3, r3, -1		/* descrement loop */
	addik	r5, r4, 0		/* add new space for command line */
	tovirt(r5,r5)
#endif /* CONFIG_CMDLINE_BOOL */

#ifdef NOT_COMPILE
/* save bram context */
	or	r6, r0, r0				/* incremment */
	ori	r4, r0, TOPHYS(_bram_load_start)	/* save bram context */
	ori	r3, r0, (LMB_SIZE - 4)
_copy_bram:
	lw	r7, r0, r6		/* r7 = r0 + r6 */
	sw	r7, r4, r6		/* addr[r4 + r6] = r7*/
	addik	r6, r6, 4		/* increment counting */
	bgtid	r3, _copy_bram		/* loop for all entries */
	addik	r3, r3, -4		/* descrement loop */
#endif
	/* We have to turn on the MMU right away. */

	/*
	 * Set up the initial MMU state so we can do the first level of
	 * kernel initialization.  This maps the first 16 MBytes of memory 1:1
	 * virtual to physical.
	 */
	nop
	addik	r3, r0, MICROBLAZE_TLB_SIZE -1	/* Invalidate all TLB entries */
_invalidate:
	mts	rtlbx, r3
	mts	rtlbhi, r0			/* flush: ensure V is clear   */
	bgtid	r3, _invalidate		/* loop for all entries       */
	addik	r3, r3, -1
	/* sync */

	/* Setup the kernel PID */
	mts	rpid,r0			/* Load the kernel PID */
	nop
	bri	4

	/*
	 * We should still be executing code at physical address area
	 * RAM_BASEADDR at this point. However, kernel code is at
	 * a virtual address. So, set up a TLB mapping to cover this once
	 * translation is enabled.
	 */

	addik	r3,r0, CONFIG_KERNEL_START /* Load the kernel virtual address */
	tophys(r4,r3)			/* Load the kernel physical address */

	/*
	 * Configure and load two entries into TLB slots 0 and 1.
	 * In case we are pinning TLBs, these are reserved in by the
	 * other TLB functions.  If not reserving, then it doesn't
	 * matter where they are loaded.
	 */
	andi	r4,r4,0xfffffc00	/* Mask off the real page number */
	ori	r4,r4,(TLB_WR | TLB_EX)	/* Set the write and execute bits */

	andi	r3,r3,0xfffffc00	/* Mask off the effective page number */
	ori	r3,r3,(TLB_VALID | TLB_PAGESZ(PAGESZ_16M))

	mts     rtlbx,r0		/* TLB slow 0 */

	mts	rtlblo,r4		/* Load the data portion of the entry */
	mts	rtlbhi,r3		/* Load the tag portion of the entry */

	addik	r4, r4, 0x01000000	/* Map next 16 M entries */
	addik	r3, r3, 0x01000000

	ori	r6,r0,1			/* TLB slot 1 */
	mts     rtlbx,r6

	mts	rtlblo,r4		/* Load the data portion of the entry */
	mts	rtlbhi,r3		/* Load the tag portion of the entry */

	/*
	 * Load a TLB entry for LMB, since we need access to
	 * the exception vectors, using a 4k real==virtual mapping.
	 */
	ori	r6,r0,3			/* TLB slot 3 */
	mts     rtlbx,r6

	ori	r4,r0,(TLB_WR | TLB_EX)
	ori	r3,r0,(TLB_VALID | TLB_PAGESZ(PAGESZ_4K))

	mts	rtlblo,r4		/* Load the data portion of the entry */
	mts	rtlbhi,r3		/* Load the tag portion of the entry */

	/*
	 * We now have the lower 16 Meg of RAM mapped into TLB entries, and the
	 * caches ready to work.
	 */
turn_on_mmu:
	ori	r15,r0,start_here
	ori	r4,r0,MSR_KERNEL_VMS
	mts	rmsr,r4
	nop
	rted	r15,0			/* enables MMU */
	nop

start_here:
#endif /* CONFIG_MMU */

	/* Initialize small data anchors */
	la	r13, r0, _KERNEL_SDA_BASE_
	la	r2, r0, _KERNEL_SDA2_BASE_

	/* Initialize stack pointer */
	la	r1, r0, init_thread_union + THREAD_SIZE - 4

	/* Initialize r31 with current task address */
	la	r31, r0, init_task

	/*
	 * Call platform dependent initialize function.
	 * Please see $(ARCH)/mach-$(SUBARCH)/setup.c for
	 * the function.
	 */
	la	r9, r0, machine_early_init
	brald	r15, r9
	nop

#ifndef CONFIG_MMU
	la	r15, r0, machine_halt
	braid	start_kernel
	nop
#else
	/*
	 * Initialize the MMU.
	 */
	bralid	r15, mmu_init
	nop

	/* Go back to running unmapped so we can load up new values
	 * and change to using our exception vectors.
	 * On the MicroBlaze, all we invalidate the used TLB entries to clear
	 * the old 16M byte TLB mappings.
	 */
	ori	r15,r0,TOPHYS(kernel_load_context)
	ori	r4,r0,MSR_KERNEL
	mts	rmsr,r4
	nop
	bri	4
	rted	r15,0
	nop

	/* Load up the kernel context */
kernel_load_context:
	# Keep entry 0 and 1 valid. Entry 3 mapped to LMB can go away.
	ori	r5,r0,3
	mts     rtlbx,r5
	nop
	mts	rtlbhi,r0
	nop
	addi	r15, r0, machine_halt
	ori	r17, r0, start_kernel
	ori	r4, r0, MSR_KERNEL_VMS
	mts	rmsr, r4
	nop
	rted	r17, 0		/* enable MMU and jump to start_kernel */
	nop
#endif /* CONFIG_MMU */
Commit	Line	Data
6d5af1a3 MS	1	/*
	2	* Copyright (C) 2007-2009 Michal Simek <monstr@monstr.eu>
	3	* Copyright (C) 2007-2009 PetaLogix
	4	* Copyright (C) 2006 Atmark Techno, Inc.
	5	*
5846cc60 MS	6	* MMU code derived from arch/ppc/kernel/head_4xx.S:
	7	* Copyright (c) 1995-1996 Gary Thomas <gdt@linuxppc.org>
	8	* Initial PowerPC version.
	9	* Copyright (c) 1996 Cort Dougan <cort@cs.nmt.edu>
	10	* Rewritten for PReP
	11	* Copyright (c) 1996 Paul Mackerras <paulus@cs.anu.edu.au>
	12	* Low-level exception handers, MMU support, and rewrite.
	13	* Copyright (c) 1997 Dan Malek <dmalek@jlc.net>
	14	* PowerPC 8xx modifications.
	15	* Copyright (c) 1998-1999 TiVo, Inc.
	16	* PowerPC 403GCX modifications.
	17	* Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu>
	18	* PowerPC 403GCX/405GP modifications.
	19	* Copyright 2000 MontaVista Software Inc.
	20	* PPC405 modifications
	21	* PowerPC 403GCX/405GP modifications.
	22	* Author: MontaVista Software, Inc.
	23	* frank_rowand@mvista.com or source@mvista.com
	24	* debbie_chu@mvista.com
	25	*
6d5af1a3 MS	26	* This file is subject to the terms and conditions of the GNU General Public
	27	* License. See the file "COPYING" in the main directory of this archive
	28	* for more details.
	29	*/
	30
7a0248e8	31	#include <linux/init.h>
6d5af1a3 MS	32	#include <linux/linkage.h>
	33	#include <asm/thread_info.h>
	34	#include <asm/page.h>
d8678b58	35	#include <linux/of_fdt.h> /* for OF_DT_HEADER */
6d5af1a3	36
5846cc60 MS	37	#ifdef CONFIG_MMU
	38	#include <asm/setup.h> /* COMMAND_LINE_SIZE */
	39	#include <asm/mmu.h>
	40	#include <asm/processor.h>
	41
	42	.data
	43	.global empty_zero_page
	44	.align 12
	45	empty_zero_page:
ba9c4f88	46	.space PAGE_SIZE
5846cc60 MS	47	.global swapper_pg_dir
5846cc60 MS	48	swapper_pg_dir:
ba9c4f88	49	.space PAGE_SIZE
5846cc60 MS	50
	51	#endif /* CONFIG_MMU */
	52
7a0248e8	53	__HEAD
6d5af1a3	54	ENTRY(_start)
ee68f174 MS	55	#if CONFIG_KERNEL_BASE_ADDR == 0
	56	brai TOPHYS(real_start)
	57	.org 0x100
	58	real_start:
	59	#endif
	60
6d5af1a3 MS	61	mfs r1, rmsr
	62	andi r1, r1, ~2
	63	mts rmsr, r1
2622434e	64	/*
0eb6aaf5 MS	65	* According to Xilinx, msrclr instruction behaves like 'mfs rX,rpc'
	66	* if the msrclr instruction is not enabled. We use this to detect
	67	* if the opcode is available, by issuing msrclr and then testing the result.
	68	* r8 == 0 - msr instructions are implemented
	69	* r8 != 0 - msr instructions are not implemented
2622434e	70	*/
0eb6aaf5 MS	71	msrclr r8, 0 /* clear nothing - just read msr for test */
0eb6aaf5 MS	72	cmpu r8, r8, r1 /* r1 must contain msr reg content */
2622434e	73
909964ec JW	74	/* r7 may point to an FDT, or there may be one linked in.
	75	if it's in r7, we've got to save it away ASAP.
	76	We ensure r7 points to a valid FDT, just in case the bootloader
	77	is broken or non-existent */
	78	beqi r7, no_fdt_arg /* NULL pointer? don't copy */
026a2078 MS	79	/* Does r7 point to a valid FDT? Load HEADER magic number */
	80	/* Run time Big/Little endian platform */
	81	/* Save 1 as word and load byte - 0 - BIG, 1 - LITTLE */
	82	addik r11, r0, 0x1 /* BIG/LITTLE checking value */
	83	/* __bss_start will be zeroed later - it is just temp location */
	84	swi r11, r0, TOPHYS(__bss_start)
	85	lbui r11, r0, TOPHYS(__bss_start)
	86	beqid r11, big_endian /* DO NOT break delay stop dependency */
	87	lw r11, r0, r7 /* Big endian load in delay slot */
	88	lwr r11, r0, r7 /* Little endian load */
	89	big_endian:
	90	rsubi r11, r11, OF_DT_HEADER /* Check FDT header */
ea3fd146 MS	91	beqi r11, _prepare_copy_fdt
ea3fd146 MS	92	or r7, r0, r0 /* clear R7 when not valid DTB */
909964ec	93	bnei r11, no_fdt_arg /* No - get out of here */
ea3fd146	94	_prepare_copy_fdt:
6d5af1a3	95	or r11, r0, r0 /* incremment */
909964ec	96	ori r4, r0, TOPHYS(_fdt_start)
6d5af1a3 MS	97	ori r3, r0, (0x4000 - 4)
	98	_copy_fdt:
	99	lw r12, r7, r11 /* r12 = r7 + r11 */
	100	sw r12, r4, r11 /* addr[r4 + r11] = r12 */
	101	addik r11, r11, 4 /* increment counting */
	102	bgtid r3, _copy_fdt /* loop for all entries */
	103	addik r3, r3, -4 /* descrement loop */
	104	no_fdt_arg:
	105
5846cc60 MS	106	#ifdef CONFIG_MMU
	107
	108	#ifndef CONFIG_CMDLINE_BOOL
	109	/*
	110	* handling command line
	111	* copy command line to __init_end. There is space for storing command line.
	112	*/
	113	or r6, r0, r0 /* incremment */
	114	ori r4, r0, __init_end /* load address of command line */
	115	tophys(r4,r4) /* convert to phys address */
	116	ori r3, r0, COMMAND_LINE_SIZE - 1 /* number of loops */
	117	_copy_command_line:
3f218935 MS	118	lbu r2, r5, r6 /* r2=r5+r6 - r5 contain pointer to command line */
3f218935 MS	119	sb r2, r4, r6 /* addr[r4+r6]= r2*/
5846cc60 MS	120	addik r6, r6, 1 /* increment counting */
	121	bgtid r3, _copy_command_line /* loop for all entries */
	122	addik r3, r3, -1 /* descrement loop */
	123	addik r5, r4, 0 /* add new space for command line */
	124	tovirt(r5,r5)
	125	#endif /* CONFIG_CMDLINE_BOOL */
	126
	127	#ifdef NOT_COMPILE
	128	/* save bram context */
	129	or r6, r0, r0 /* incremment */
	130	ori r4, r0, TOPHYS(_bram_load_start) /* save bram context */
	131	ori r3, r0, (LMB_SIZE - 4)
	132	_copy_bram:
	133	lw r7, r0, r6 /* r7 = r0 + r6 */
	134	sw r7, r4, r6 /* addr[r4 + r6] = r7*/
	135	addik r6, r6, 4 /* increment counting */
	136	bgtid r3, _copy_bram /* loop for all entries */
	137	addik r3, r3, -4 /* descrement loop */
	138	#endif
	139	/* We have to turn on the MMU right away. */
	140
	141	/*
	142	* Set up the initial MMU state so we can do the first level of
	143	* kernel initialization. This maps the first 16 MBytes of memory 1:1
	144	* virtual to physical.
	145	*/
	146	nop
0691c97d	147	addik r3, r0, MICROBLAZE_TLB_SIZE -1 /* Invalidate all TLB entries */
5846cc60 MS	148	_invalidate:
	149	mts rtlbx, r3
	150	mts rtlbhi, r0 /* flush: ensure V is clear */
	151	bgtid r3, _invalidate /* loop for all entries */
	152	addik r3, r3, -1
	153	/* sync */
	154
137d0795 MS	155	/* Setup the kernel PID */
	156	mts rpid,r0 /* Load the kernel PID */
	157	nop
	158	bri 4
	159
5846cc60 MS	160	/*
	161	* We should still be executing code at physical address area
	162	* RAM_BASEADDR at this point. However, kernel code is at
	163	* a virtual address. So, set up a TLB mapping to cover this once
	164	* translation is enabled.
	165	*/
	166
	167	addik r3,r0, CONFIG_KERNEL_START /* Load the kernel virtual address */
	168	tophys(r4,r3) /* Load the kernel physical address */
	169
5846cc60 MS	170	/*
	171	* Configure and load two entries into TLB slots 0 and 1.
	172	* In case we are pinning TLBs, these are reserved in by the
	173	* other TLB functions. If not reserving, then it doesn't
	174	* matter where they are loaded.
	175	*/
	176	andi r4,r4,0xfffffc00 /* Mask off the real page number */
	177	ori r4,r4,(TLB_WR \| TLB_EX) /* Set the write and execute bits */
	178
	179	andi r3,r3,0xfffffc00 /* Mask off the effective page number */
	180	ori r3,r3,(TLB_VALID \| TLB_PAGESZ(PAGESZ_16M))
	181
	182	mts rtlbx,r0 /* TLB slow 0 */
	183
	184	mts rtlblo,r4 /* Load the data portion of the entry */
	185	mts rtlbhi,r3 /* Load the tag portion of the entry */
	186
	187	addik r4, r4, 0x01000000 /* Map next 16 M entries */
	188	addik r3, r3, 0x01000000
	189
	190	ori r6,r0,1 /* TLB slot 1 */
	191	mts rtlbx,r6
	192
	193	mts rtlblo,r4 /* Load the data portion of the entry */
	194	mts rtlbhi,r3 /* Load the tag portion of the entry */
	195
	196	/*
	197	* Load a TLB entry for LMB, since we need access to
	198	* the exception vectors, using a 4k real==virtual mapping.
	199	*/
	200	ori r6,r0,3 /* TLB slot 3 */
	201	mts rtlbx,r6
	202
	203	ori r4,r0,(TLB_WR \| TLB_EX)
	204	ori r3,r0,(TLB_VALID \| TLB_PAGESZ(PAGESZ_4K))
	205
	206	mts rtlblo,r4 /* Load the data portion of the entry */
	207	mts rtlbhi,r3 /* Load the tag portion of the entry */
	208
	209	/*
	210	* We now have the lower 16 Meg of RAM mapped into TLB entries, and the
	211	* caches ready to work.
	212	*/
	213	turn_on_mmu:
	214	ori r15,r0,start_here
	215	ori r4,r0,MSR_KERNEL_VMS
	216	mts rmsr,r4
	217	nop
	218	rted r15,0 /* enables MMU */
	219	nop
	220
	221	start_here:
	222	#endif /* CONFIG_MMU */
	223
6d5af1a3 MS	224	/* Initialize small data anchors */
	225	la r13, r0, _KERNEL_SDA_BASE_
	226	la r2, r0, _KERNEL_SDA2_BASE_
	227
	228	/* Initialize stack pointer */
	229	la r1, r0, init_thread_union + THREAD_SIZE - 4
	230
	231	/* Initialize r31 with current task address */
	232	la r31, r0, init_task
	233
	234	/*
	235	* Call platform dependent initialize function.
	236	* Please see $(ARCH)/mach-$(SUBARCH)/setup.c for
	237	* the function.
	238	*/
2622434e MS	239	la r9, r0, machine_early_init
2622434e MS	240	brald r15, r9
6d5af1a3 MS	241	nop
6d5af1a3 MS	242
5846cc60	243	#ifndef CONFIG_MMU
6d5af1a3 MS	244	la r15, r0, machine_halt
	245	braid start_kernel
	246	nop
5846cc60 MS	247	#else
	248	/*
	249	* Initialize the MMU.
	250	*/
	251	bralid r15, mmu_init
	252	nop
	253
	254	/* Go back to running unmapped so we can load up new values
	255	* and change to using our exception vectors.
	256	* On the MicroBlaze, all we invalidate the used TLB entries to clear
	257	* the old 16M byte TLB mappings.
	258	*/
	259	ori r15,r0,TOPHYS(kernel_load_context)
	260	ori r4,r0,MSR_KERNEL
	261	mts rmsr,r4
	262	nop
	263	bri 4
	264	rted r15,0
	265	nop
	266
	267	/* Load up the kernel context */
	268	kernel_load_context:
	269	# Keep entry 0 and 1 valid. Entry 3 mapped to LMB can go away.
	270	ori r5,r0,3
	271	mts rtlbx,r5
	272	nop
	273	mts rtlbhi,r0
	274	nop
	275	addi r15, r0, machine_halt
	276	ori r17, r0, start_kernel
	277	ori r4, r0, MSR_KERNEL_VMS
	278	mts rmsr, r4
	279	nop
	280	rted r17, 0 /* enable MMU and jump to start_kernel */
	281	nop
	282	#endif /* CONFIG_MMU */