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1 | /* |
2 | * Copyright (C) 2007-2009 Michal Simek <monstr@monstr.eu> | |
3 | * Copyright (C) 2007-2009 PetaLogix | |
4 | * Copyright (C) 2006 Atmark Techno, Inc. | |
5 | * | |
6 | * This file is subject to the terms and conditions of the GNU General Public | |
7 | * License. See the file "COPYING" in the main directory of this archive | |
8 | * for more details. | |
9 | */ | |
10 | ||
11 | #include <linux/init.h> | |
12 | #include <linux/irq.h> | |
13 | #include <asm/page.h> | |
14 | #include <linux/io.h> | |
892ee92b | 15 | #include <linux/bug.h> |
eedbdab9 MS |
16 | |
17 | #include <asm/prom.h> | |
18 | #include <asm/irq.h> | |
19 | ||
20 | #ifdef CONFIG_SELFMOD_INTC | |
21 | #include <asm/selfmod.h> | |
22 | #define INTC_BASE BARRIER_BASE_ADDR | |
23 | #else | |
24 | static unsigned int intc_baseaddr; | |
25 | #define INTC_BASE intc_baseaddr | |
26 | #endif | |
27 | ||
28 | unsigned int nr_irq; | |
29 | ||
30 | /* No one else should require these constants, so define them locally here. */ | |
31 | #define ISR 0x00 /* Interrupt Status Register */ | |
32 | #define IPR 0x04 /* Interrupt Pending Register */ | |
33 | #define IER 0x08 /* Interrupt Enable Register */ | |
34 | #define IAR 0x0c /* Interrupt Acknowledge Register */ | |
35 | #define SIE 0x10 /* Set Interrupt Enable bits */ | |
36 | #define CIE 0x14 /* Clear Interrupt Enable bits */ | |
37 | #define IVR 0x18 /* Interrupt Vector Register */ | |
38 | #define MER 0x1c /* Master Enable Register */ | |
39 | ||
40 | #define MER_ME (1<<0) | |
41 | #define MER_HIE (1<<1) | |
42 | ||
6f205a4c | 43 | static void intc_enable_or_unmask(struct irq_data *d) |
eedbdab9 | 44 | { |
6f205a4c TG |
45 | unsigned long mask = 1 << d->irq; |
46 | pr_debug("enable_or_unmask: %d\n", d->irq); | |
33d9ff59 | 47 | out_be32(INTC_BASE + SIE, mask); |
48 | ||
49 | /* ack level irqs because they can't be acked during | |
50 | * ack function since the handle_level_irq function | |
51 | * acks the irq before calling the interrupt handler | |
52 | */ | |
6f205a4c | 53 | if (irq_to_desc(d->irq)->status & IRQ_LEVEL) |
33d9ff59 | 54 | out_be32(INTC_BASE + IAR, mask); |
eedbdab9 MS |
55 | } |
56 | ||
6f205a4c | 57 | static void intc_disable_or_mask(struct irq_data *d) |
eedbdab9 | 58 | { |
6f205a4c TG |
59 | pr_debug("disable: %d\n", d->irq); |
60 | out_be32(INTC_BASE + CIE, 1 << d->irq); | |
eedbdab9 MS |
61 | } |
62 | ||
6f205a4c | 63 | static void intc_ack(struct irq_data *d) |
eedbdab9 | 64 | { |
6f205a4c TG |
65 | pr_debug("ack: %d\n", d->irq); |
66 | out_be32(INTC_BASE + IAR, 1 << d->irq); | |
eedbdab9 MS |
67 | } |
68 | ||
6f205a4c | 69 | static void intc_mask_ack(struct irq_data *d) |
eedbdab9 | 70 | { |
6f205a4c TG |
71 | unsigned long mask = 1 << d->irq; |
72 | pr_debug("disable_and_ack: %d\n", d->irq); | |
eedbdab9 MS |
73 | out_be32(INTC_BASE + CIE, mask); |
74 | out_be32(INTC_BASE + IAR, mask); | |
75 | } | |
76 | ||
eedbdab9 MS |
77 | static struct irq_chip intc_dev = { |
78 | .name = "Xilinx INTC", | |
6f205a4c TG |
79 | .irq_unmask = intc_enable_or_unmask, |
80 | .irq_mask = intc_disable_or_mask, | |
81 | .irq_ack = intc_ack, | |
82 | .irq_mask_ack = intc_mask_ack, | |
eedbdab9 MS |
83 | }; |
84 | ||
85 | unsigned int get_irq(struct pt_regs *regs) | |
86 | { | |
87 | int irq; | |
88 | ||
89 | /* | |
90 | * NOTE: This function is the one that needs to be improved in | |
91 | * order to handle multiple interrupt controllers. It currently | |
92 | * is hardcoded to check for interrupts only on the first INTC. | |
93 | */ | |
94 | irq = in_be32(INTC_BASE + IVR); | |
95 | pr_debug("get_irq: %d\n", irq); | |
96 | ||
97 | return irq; | |
98 | } | |
99 | ||
100 | void __init init_IRQ(void) | |
101 | { | |
102 | u32 i, j, intr_type; | |
103 | struct device_node *intc = NULL; | |
104 | #ifdef CONFIG_SELFMOD_INTC | |
105 | unsigned int intc_baseaddr = 0; | |
106 | static int arr_func[] = { | |
107 | (int)&get_irq, | |
108 | (int)&intc_enable_or_unmask, | |
109 | (int)&intc_disable_or_mask, | |
110 | (int)&intc_mask_ack, | |
111 | (int)&intc_ack, | |
112 | (int)&intc_end, | |
113 | 0 | |
114 | }; | |
115 | #endif | |
92ee8bd4 | 116 | const char * const intc_list[] = { |
eedbdab9 | 117 | "xlnx,xps-intc-1.00.a", |
eedbdab9 MS |
118 | NULL |
119 | }; | |
120 | ||
121 | for (j = 0; intc_list[j] != NULL; j++) { | |
122 | intc = of_find_compatible_node(NULL, NULL, intc_list[j]); | |
123 | if (intc) | |
124 | break; | |
125 | } | |
892ee92b | 126 | BUG_ON(!intc); |
eedbdab9 | 127 | |
02b08045 MS |
128 | intc_baseaddr = be32_to_cpup(of_get_property(intc, |
129 | "reg", NULL)); | |
eedbdab9 | 130 | intc_baseaddr = (unsigned long) ioremap(intc_baseaddr, PAGE_SIZE); |
02b08045 MS |
131 | nr_irq = be32_to_cpup(of_get_property(intc, |
132 | "xlnx,num-intr-inputs", NULL)); | |
eedbdab9 MS |
133 | |
134 | intr_type = | |
02b08045 MS |
135 | be32_to_cpup(of_get_property(intc, |
136 | "xlnx,kind-of-intr", NULL)); | |
7b7210d7 MS |
137 | if (intr_type >= (1 << (nr_irq + 1))) |
138 | printk(KERN_INFO " ERROR: Mismatch in kind-of-intr param\n"); | |
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139 | |
140 | #ifdef CONFIG_SELFMOD_INTC | |
141 | selfmod_function((int *) arr_func, intc_baseaddr); | |
142 | #endif | |
143 | printk(KERN_INFO "%s #0 at 0x%08x, num_irq=%d, edge=0x%x\n", | |
144 | intc_list[j], intc_baseaddr, nr_irq, intr_type); | |
145 | ||
146 | /* | |
147 | * Disable all external interrupts until they are | |
148 | * explicity requested. | |
149 | */ | |
150 | out_be32(intc_baseaddr + IER, 0); | |
151 | ||
152 | /* Acknowledge any pending interrupts just in case. */ | |
153 | out_be32(intc_baseaddr + IAR, 0xffffffff); | |
154 | ||
155 | /* Turn on the Master Enable. */ | |
156 | out_be32(intc_baseaddr + MER, MER_HIE | MER_ME); | |
157 | ||
158 | for (i = 0; i < nr_irq; ++i) { | |
159 | if (intr_type & (0x00000001 << i)) { | |
160 | set_irq_chip_and_handler_name(i, &intc_dev, | |
161 | handle_edge_irq, intc_dev.name); | |
6f205a4c | 162 | irq_clear_status_flags(i, IRQ_LEVEL); |
eedbdab9 MS |
163 | } else { |
164 | set_irq_chip_and_handler_name(i, &intc_dev, | |
165 | handle_level_irq, intc_dev.name); | |
6f205a4c | 166 | irq_set_status_flags(i, IRQ_LEVEL); |
eedbdab9 MS |
167 | } |
168 | } | |
169 | } |