]> git.proxmox.com Git - mirror_ubuntu-bionic-kernel.git/blame - arch/microblaze/kernel/process.c
sched/headers: Prepare for new header dependencies before moving code to <linux/sched...
[mirror_ubuntu-bionic-kernel.git] / arch / microblaze / kernel / process.c
CommitLineData
6496a23a
MS
1/*
2 * Copyright (C) 2008-2009 Michal Simek <monstr@monstr.eu>
3 * Copyright (C) 2008-2009 PetaLogix
4 * Copyright (C) 2006 Atmark Techno, Inc.
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10
579907e6 11#include <linux/cpu.h>
d64af918 12#include <linux/export.h>
6496a23a 13#include <linux/sched.h>
b17b0153 14#include <linux/sched/debug.h>
29930025 15#include <linux/sched/task.h>
6496a23a
MS
16#include <linux/pm.h>
17#include <linux/tick.h>
18#include <linux/bitops.h>
f3268edb 19#include <linux/ptrace.h>
6496a23a 20#include <asm/pgalloc.h>
6bd55f0b 21#include <linux/uaccess.h> /* for USER_DS macros */
a1f55113 22#include <asm/cacheflush.h>
6496a23a
MS
23
24void show_regs(struct pt_regs *regs)
25{
a43cb95d
TH
26 show_regs_print_info(KERN_INFO);
27
6bd55f0b
MS
28 pr_info(" Registers dump: mode=%X\r\n", regs->pt_mode);
29 pr_info(" r1=%08lX, r2=%08lX, r3=%08lX, r4=%08lX\n",
6496a23a 30 regs->r1, regs->r2, regs->r3, regs->r4);
6bd55f0b 31 pr_info(" r5=%08lX, r6=%08lX, r7=%08lX, r8=%08lX\n",
6496a23a 32 regs->r5, regs->r6, regs->r7, regs->r8);
6bd55f0b 33 pr_info(" r9=%08lX, r10=%08lX, r11=%08lX, r12=%08lX\n",
6496a23a 34 regs->r9, regs->r10, regs->r11, regs->r12);
6bd55f0b 35 pr_info(" r13=%08lX, r14=%08lX, r15=%08lX, r16=%08lX\n",
6496a23a 36 regs->r13, regs->r14, regs->r15, regs->r16);
6bd55f0b 37 pr_info(" r17=%08lX, r18=%08lX, r19=%08lX, r20=%08lX\n",
6496a23a 38 regs->r17, regs->r18, regs->r19, regs->r20);
6bd55f0b 39 pr_info(" r21=%08lX, r22=%08lX, r23=%08lX, r24=%08lX\n",
6496a23a 40 regs->r21, regs->r22, regs->r23, regs->r24);
6bd55f0b 41 pr_info(" r25=%08lX, r26=%08lX, r27=%08lX, r28=%08lX\n",
6496a23a 42 regs->r25, regs->r26, regs->r27, regs->r28);
6bd55f0b 43 pr_info(" r29=%08lX, r30=%08lX, r31=%08lX, rPC=%08lX\n",
6496a23a 44 regs->r29, regs->r30, regs->r31, regs->pc);
6bd55f0b 45 pr_info(" msr=%08lX, ear=%08lX, esr=%08lX, fsr=%08lX\n",
6496a23a 46 regs->msr, regs->ear, regs->esr, regs->fsr);
6496a23a
MS
47}
48
6496a23a
MS
49void (*pm_power_off)(void) = NULL;
50EXPORT_SYMBOL(pm_power_off);
51
6496a23a
MS
52void flush_thread(void)
53{
54}
55
a8fb748e 56int copy_thread(unsigned long clone_flags, unsigned long usp,
afa86fc4 57 unsigned long arg, struct task_struct *p)
6496a23a
MS
58{
59 struct pt_regs *childregs = task_pt_regs(p);
60 struct thread_info *ti = task_thread_info(p);
61
2319295d
AV
62 if (unlikely(p->flags & PF_KTHREAD)) {
63 /* if we're creating a new kernel thread then just zeroing all
64 * the registers. That's OK for a brand new thread.*/
65 memset(childregs, 0, sizeof(struct pt_regs));
66 memset(&ti->cpu_context, 0, sizeof(struct cpu_context));
67 ti->cpu_context.r1 = (unsigned long)childregs;
68 ti->cpu_context.r20 = (unsigned long)usp; /* fn */
69 ti->cpu_context.r19 = (unsigned long)arg;
70 childregs->pt_mode = 1;
71 local_save_flags(childregs->msr);
72#ifdef CONFIG_MMU
73 ti->cpu_context.msr = childregs->msr & ~MSR_IE;
74#endif
75 ti->cpu_context.r15 = (unsigned long)ret_from_kernel_thread - 8;
76 return 0;
77 }
f3268edb
AV
78 *childregs = *current_pt_regs();
79 if (usp)
80 childregs->r1 = usp;
6496a23a
MS
81
82 memset(&ti->cpu_context, 0, sizeof(struct cpu_context));
83 ti->cpu_context.r1 = (unsigned long)childregs;
2319295d 84#ifndef CONFIG_MMU
6496a23a 85 ti->cpu_context.msr = (unsigned long)childregs->msr;
5233806d 86#else
2319295d 87 childregs->msr |= MSR_UMS;
5233806d 88
5233806d
MS
89 /* we should consider the fact that childregs is a copy of the parent
90 * regs which were saved immediately after entering the kernel state
91 * before enabling VM. This MSR will be restored in switch_to and
92 * RETURN() and we want to have the right machine state there
93 * specifically this state must have INTs disabled before and enabled
94 * after performing rtbd
95 * compose the right MSR for RETURN(). It will work for switch_to also
96 * excepting for VM and UMS
97 * don't touch UMS , CARRY and cache bits
98 * right now MSR is a copy of parent one */
5233806d
MS
99 childregs->msr &= ~MSR_EIP;
100 childregs->msr |= MSR_IE;
101 childregs->msr &= ~MSR_VM;
102 childregs->msr |= MSR_VMS;
103 childregs->msr |= MSR_EE; /* exceptions will be enabled*/
104
105 ti->cpu_context.msr = (childregs->msr|MSR_VM);
106 ti->cpu_context.msr &= ~MSR_UMS; /* switch_to to kernel mode */
84ac218f 107 ti->cpu_context.msr &= ~MSR_IE;
5233806d 108#endif
6496a23a
MS
109 ti->cpu_context.r15 = (unsigned long)ret_from_fork - 8;
110
d5c15f17
EI
111 /*
112 * r21 is the thread reg, r10 is 6th arg to clone
113 * which contains TLS area
114 */
6496a23a 115 if (clone_flags & CLONE_SETTLS)
d5c15f17 116 childregs->r21 = childregs->r10;
6496a23a
MS
117
118 return 0;
119}
120
5233806d 121#ifndef CONFIG_MMU
6496a23a
MS
122/*
123 * Return saved PC of a blocked thread.
124 */
125unsigned long thread_saved_pc(struct task_struct *tsk)
126{
127 struct cpu_context *ctx =
128 &(((struct thread_info *)(tsk->stack))->cpu_context);
129
130 /* Check whether the thread is blocked in resume() */
131 if (in_sched_functions(ctx->r15))
132 return (unsigned long)ctx->r15;
133 else
134 return ctx->r14;
135}
5233806d 136#endif
6496a23a 137
6496a23a
MS
138unsigned long get_wchan(struct task_struct *p)
139{
140/* TBD (used by procfs) */
141 return 0;
142}
e1c4bd08
MS
143
144/* Set up a thread for executing a new program */
145void start_thread(struct pt_regs *regs, unsigned long pc, unsigned long usp)
146{
e1c4bd08
MS
147 regs->pc = pc;
148 regs->r1 = usp;
149 regs->pt_mode = 0;
f1ae3f69 150#ifdef CONFIG_MMU
866d7229 151 regs->msr |= MSR_UMS;
99c59f60 152 regs->msr &= ~MSR_VM;
f1ae3f69 153#endif
e1c4bd08 154}
5233806d
MS
155
156#ifdef CONFIG_MMU
157#include <linux/elfcore.h>
158/*
159 * Set up a thread for executing a new program
160 */
161int dump_fpu(struct pt_regs *regs, elf_fpregset_t *fpregs)
162{
163 return 0; /* MicroBlaze has no separate FPU registers */
164}
165#endif /* CONFIG_MMU */
a047775e
MS
166
167void arch_cpu_idle(void)
168{
169 local_irq_enable();
170}