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d3afa58c MS |
1 | /* |
2 | * Contains common pci routines for ALL ppc platform | |
3 | * (based on pci_32.c and pci_64.c) | |
4 | * | |
5 | * Port for PPC64 David Engebretsen, IBM Corp. | |
6 | * Contains common pci routines for ppc64 platform, pSeries and iSeries brands. | |
7 | * | |
8 | * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM | |
9 | * Rework, based on alpha PCI code. | |
10 | * | |
11 | * Common pmac/prep/chrp pci routines. -- Cort | |
12 | * | |
13 | * This program is free software; you can redistribute it and/or | |
14 | * modify it under the terms of the GNU General Public License | |
15 | * as published by the Free Software Foundation; either version | |
16 | * 2 of the License, or (at your option) any later version. | |
17 | */ | |
18 | ||
19 | #include <linux/kernel.h> | |
20 | #include <linux/pci.h> | |
21 | #include <linux/string.h> | |
22 | #include <linux/init.h> | |
23 | #include <linux/bootmem.h> | |
24 | #include <linux/mm.h> | |
3a4f8a0b | 25 | #include <linux/shmem_fs.h> |
d3afa58c MS |
26 | #include <linux/list.h> |
27 | #include <linux/syscalls.h> | |
28 | #include <linux/irq.h> | |
29 | #include <linux/vmalloc.h> | |
5a0e3ad6 | 30 | #include <linux/slab.h> |
f1ca09b2 GL |
31 | #include <linux/of.h> |
32 | #include <linux/of_address.h> | |
5c9f303e | 33 | #include <linux/of_irq.h> |
04bea68b | 34 | #include <linux/of_pci.h> |
66421a64 | 35 | #include <linux/export.h> |
d3afa58c MS |
36 | |
37 | #include <asm/processor.h> | |
6bd55f0b | 38 | #include <linux/io.h> |
d3afa58c MS |
39 | #include <asm/pci-bridge.h> |
40 | #include <asm/byteorder.h> | |
41 | ||
42 | static DEFINE_SPINLOCK(hose_spinlock); | |
43 | LIST_HEAD(hose_list); | |
44 | ||
45 | /* XXX kill that some day ... */ | |
46 | static int global_phb_number; /* Global phb counter */ | |
47 | ||
48 | /* ISA Memory physical address */ | |
49 | resource_size_t isa_mem_base; | |
50 | ||
bf13a6fa | 51 | unsigned long isa_io_base; |
52e9e6e0 FW |
52 | EXPORT_SYMBOL(isa_io_base); |
53 | ||
bf13a6fa BH |
54 | static int pci_bus_count; |
55 | ||
d3afa58c MS |
56 | struct pci_controller *pcibios_alloc_controller(struct device_node *dev) |
57 | { | |
58 | struct pci_controller *phb; | |
59 | ||
60 | phb = zalloc_maybe_bootmem(sizeof(struct pci_controller), GFP_KERNEL); | |
61 | if (!phb) | |
62 | return NULL; | |
63 | spin_lock(&hose_spinlock); | |
64 | phb->global_number = global_phb_number++; | |
65 | list_add_tail(&phb->list_node, &hose_list); | |
66 | spin_unlock(&hose_spinlock); | |
67 | phb->dn = dev; | |
68 | phb->is_dynamic = mem_init_done; | |
69 | return phb; | |
70 | } | |
71 | ||
72 | void pcibios_free_controller(struct pci_controller *phb) | |
73 | { | |
74 | spin_lock(&hose_spinlock); | |
75 | list_del(&phb->list_node); | |
76 | spin_unlock(&hose_spinlock); | |
77 | ||
78 | if (phb->is_dynamic) | |
79 | kfree(phb); | |
80 | } | |
81 | ||
82 | static resource_size_t pcibios_io_size(const struct pci_controller *hose) | |
83 | { | |
28f65c11 | 84 | return resource_size(&hose->io_resource); |
d3afa58c MS |
85 | } |
86 | ||
87 | int pcibios_vaddr_is_ioport(void __iomem *address) | |
88 | { | |
89 | int ret = 0; | |
90 | struct pci_controller *hose; | |
91 | resource_size_t size; | |
92 | ||
93 | spin_lock(&hose_spinlock); | |
94 | list_for_each_entry(hose, &hose_list, list_node) { | |
95 | size = pcibios_io_size(hose); | |
96 | if (address >= hose->io_base_virt && | |
97 | address < (hose->io_base_virt + size)) { | |
98 | ret = 1; | |
99 | break; | |
100 | } | |
101 | } | |
102 | spin_unlock(&hose_spinlock); | |
103 | return ret; | |
104 | } | |
105 | ||
106 | unsigned long pci_address_to_pio(phys_addr_t address) | |
107 | { | |
108 | struct pci_controller *hose; | |
109 | resource_size_t size; | |
110 | unsigned long ret = ~0; | |
111 | ||
112 | spin_lock(&hose_spinlock); | |
113 | list_for_each_entry(hose, &hose_list, list_node) { | |
114 | size = pcibios_io_size(hose); | |
115 | if (address >= hose->io_base_phys && | |
116 | address < (hose->io_base_phys + size)) { | |
117 | unsigned long base = | |
118 | (unsigned long)hose->io_base_virt - _IO_BASE; | |
119 | ret = base + (address - hose->io_base_phys); | |
120 | break; | |
121 | } | |
122 | } | |
123 | spin_unlock(&hose_spinlock); | |
124 | ||
125 | return ret; | |
126 | } | |
127 | EXPORT_SYMBOL_GPL(pci_address_to_pio); | |
128 | ||
d3afa58c MS |
129 | /* This routine is meant to be used early during boot, when the |
130 | * PCI bus numbers have not yet been assigned, and you need to | |
131 | * issue PCI config cycles to an OF device. | |
132 | * It could also be used to "fix" RTAS config cycles if you want | |
133 | * to set pci_assign_all_buses to 1 and still use RTAS for PCI | |
134 | * config cycles. | |
135 | */ | |
136 | struct pci_controller *pci_find_hose_for_OF_device(struct device_node *node) | |
137 | { | |
138 | while (node) { | |
139 | struct pci_controller *hose, *tmp; | |
140 | list_for_each_entry_safe(hose, tmp, &hose_list, list_node) | |
141 | if (hose->dn == node) | |
142 | return hose; | |
143 | node = node->parent; | |
144 | } | |
145 | return NULL; | |
146 | } | |
147 | ||
b51d4a3e MS |
148 | void pcibios_set_master(struct pci_dev *dev) |
149 | { | |
150 | /* No special bus mastering setup handling */ | |
151 | } | |
152 | ||
d3afa58c MS |
153 | /* |
154 | * Platform support for /proc/bus/pci/X/Y mmap()s, | |
155 | * modelled on the sparc64 implementation by Dave Miller. | |
156 | * -- paulus. | |
157 | */ | |
158 | ||
159 | /* | |
160 | * Adjust vm_pgoff of VMA such that it is the physical page offset | |
161 | * corresponding to the 32-bit pci bus offset for DEV requested by the user. | |
162 | * | |
163 | * Basically, the user finds the base address for his device which he wishes | |
164 | * to mmap. They read the 32-bit value from the config space base register, | |
165 | * add whatever PAGE_SIZE multiple offset they wish, and feed this into the | |
166 | * offset parameter of mmap on /proc/bus/pci/XXX for that device. | |
167 | * | |
168 | * Returns negative error code on failure, zero on success. | |
169 | */ | |
170 | static struct resource *__pci_mmap_make_offset(struct pci_dev *dev, | |
171 | resource_size_t *offset, | |
172 | enum pci_mmap_state mmap_state) | |
173 | { | |
174 | struct pci_controller *hose = pci_bus_to_host(dev->bus); | |
175 | unsigned long io_offset = 0; | |
176 | int i, res_bit; | |
177 | ||
f7eaacc1 | 178 | if (!hose) |
d3afa58c MS |
179 | return NULL; /* should never happen */ |
180 | ||
181 | /* If memory, add on the PCI bridge address offset */ | |
182 | if (mmap_state == pci_mmap_mem) { | |
183 | #if 0 /* See comment in pci_resource_to_user() for why this is disabled */ | |
184 | *offset += hose->pci_mem_offset; | |
185 | #endif | |
186 | res_bit = IORESOURCE_MEM; | |
187 | } else { | |
188 | io_offset = (unsigned long)hose->io_base_virt - _IO_BASE; | |
189 | *offset += io_offset; | |
190 | res_bit = IORESOURCE_IO; | |
191 | } | |
192 | ||
193 | /* | |
194 | * Check that the offset requested corresponds to one of the | |
195 | * resources of the device. | |
196 | */ | |
197 | for (i = 0; i <= PCI_ROM_RESOURCE; i++) { | |
198 | struct resource *rp = &dev->resource[i]; | |
199 | int flags = rp->flags; | |
200 | ||
201 | /* treat ROM as memory (should be already) */ | |
202 | if (i == PCI_ROM_RESOURCE) | |
203 | flags |= IORESOURCE_MEM; | |
204 | ||
205 | /* Active and same type? */ | |
206 | if ((flags & res_bit) == 0) | |
207 | continue; | |
208 | ||
209 | /* In the range of this resource? */ | |
210 | if (*offset < (rp->start & PAGE_MASK) || *offset > rp->end) | |
211 | continue; | |
212 | ||
213 | /* found it! construct the final physical address */ | |
214 | if (mmap_state == pci_mmap_io) | |
215 | *offset += hose->io_base_phys - io_offset; | |
216 | return rp; | |
217 | } | |
218 | ||
219 | return NULL; | |
220 | } | |
221 | ||
d3afa58c MS |
222 | /* |
223 | * This one is used by /dev/mem and fbdev who have no clue about the | |
224 | * PCI device, it tries to find the PCI device first and calls the | |
225 | * above routine | |
226 | */ | |
227 | pgprot_t pci_phys_mem_access_prot(struct file *file, | |
228 | unsigned long pfn, | |
229 | unsigned long size, | |
230 | pgprot_t prot) | |
231 | { | |
232 | struct pci_dev *pdev = NULL; | |
233 | struct resource *found = NULL; | |
234 | resource_size_t offset = ((resource_size_t)pfn) << PAGE_SHIFT; | |
235 | int i; | |
236 | ||
237 | if (page_is_ram(pfn)) | |
238 | return prot; | |
239 | ||
240 | prot = pgprot_noncached(prot); | |
241 | for_each_pci_dev(pdev) { | |
242 | for (i = 0; i <= PCI_ROM_RESOURCE; i++) { | |
243 | struct resource *rp = &pdev->resource[i]; | |
244 | int flags = rp->flags; | |
245 | ||
246 | /* Active and same type? */ | |
247 | if ((flags & IORESOURCE_MEM) == 0) | |
248 | continue; | |
249 | /* In the range of this resource? */ | |
250 | if (offset < (rp->start & PAGE_MASK) || | |
251 | offset > rp->end) | |
252 | continue; | |
253 | found = rp; | |
254 | break; | |
255 | } | |
256 | if (found) | |
257 | break; | |
258 | } | |
259 | if (found) { | |
260 | if (found->flags & IORESOURCE_PREFETCH) | |
261 | prot = pgprot_noncached_wc(prot); | |
262 | pci_dev_put(pdev); | |
263 | } | |
264 | ||
265 | pr_debug("PCI: Non-PCI map for %llx, prot: %lx\n", | |
266 | (unsigned long long)offset, pgprot_val(prot)); | |
267 | ||
268 | return prot; | |
269 | } | |
270 | ||
271 | /* | |
272 | * Perform the actual remap of the pages for a PCI device mapping, as | |
273 | * appropriate for this architecture. The region in the process to map | |
274 | * is described by vm_start and vm_end members of VMA, the base physical | |
275 | * address is found in vm_pgoff. | |
276 | * The pci device structure is provided so that architectures may make mapping | |
277 | * decisions on a per-device or per-bus basis. | |
278 | * | |
279 | * Returns a negative error code on failure, zero on success. | |
280 | */ | |
281 | int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma, | |
282 | enum pci_mmap_state mmap_state, int write_combine) | |
283 | { | |
284 | resource_size_t offset = | |
285 | ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT; | |
286 | struct resource *rp; | |
287 | int ret; | |
288 | ||
289 | rp = __pci_mmap_make_offset(dev, &offset, mmap_state); | |
290 | if (rp == NULL) | |
291 | return -EINVAL; | |
292 | ||
293 | vma->vm_pgoff = offset >> PAGE_SHIFT; | |
c444a2be | 294 | vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); |
d3afa58c MS |
295 | |
296 | ret = remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, | |
297 | vma->vm_end - vma->vm_start, vma->vm_page_prot); | |
298 | ||
299 | return ret; | |
300 | } | |
301 | ||
302 | /* This provides legacy IO read access on a bus */ | |
303 | int pci_legacy_read(struct pci_bus *bus, loff_t port, u32 *val, size_t size) | |
304 | { | |
305 | unsigned long offset; | |
306 | struct pci_controller *hose = pci_bus_to_host(bus); | |
307 | struct resource *rp = &hose->io_resource; | |
308 | void __iomem *addr; | |
309 | ||
310 | /* Check if port can be supported by that bus. We only check | |
311 | * the ranges of the PHB though, not the bus itself as the rules | |
312 | * for forwarding legacy cycles down bridges are not our problem | |
313 | * here. So if the host bridge supports it, we do it. | |
314 | */ | |
315 | offset = (unsigned long)hose->io_base_virt - _IO_BASE; | |
316 | offset += port; | |
317 | ||
318 | if (!(rp->flags & IORESOURCE_IO)) | |
319 | return -ENXIO; | |
320 | if (offset < rp->start || (offset + size) > rp->end) | |
321 | return -ENXIO; | |
322 | addr = hose->io_base_virt + port; | |
323 | ||
324 | switch (size) { | |
325 | case 1: | |
326 | *((u8 *)val) = in_8(addr); | |
327 | return 1; | |
328 | case 2: | |
329 | if (port & 1) | |
330 | return -EINVAL; | |
331 | *((u16 *)val) = in_le16(addr); | |
332 | return 2; | |
333 | case 4: | |
334 | if (port & 3) | |
335 | return -EINVAL; | |
336 | *((u32 *)val) = in_le32(addr); | |
337 | return 4; | |
338 | } | |
339 | return -EINVAL; | |
340 | } | |
341 | ||
342 | /* This provides legacy IO write access on a bus */ | |
343 | int pci_legacy_write(struct pci_bus *bus, loff_t port, u32 val, size_t size) | |
344 | { | |
345 | unsigned long offset; | |
346 | struct pci_controller *hose = pci_bus_to_host(bus); | |
347 | struct resource *rp = &hose->io_resource; | |
348 | void __iomem *addr; | |
349 | ||
350 | /* Check if port can be supported by that bus. We only check | |
351 | * the ranges of the PHB though, not the bus itself as the rules | |
352 | * for forwarding legacy cycles down bridges are not our problem | |
353 | * here. So if the host bridge supports it, we do it. | |
354 | */ | |
355 | offset = (unsigned long)hose->io_base_virt - _IO_BASE; | |
356 | offset += port; | |
357 | ||
358 | if (!(rp->flags & IORESOURCE_IO)) | |
359 | return -ENXIO; | |
360 | if (offset < rp->start || (offset + size) > rp->end) | |
361 | return -ENXIO; | |
362 | addr = hose->io_base_virt + port; | |
363 | ||
364 | /* WARNING: The generic code is idiotic. It gets passed a pointer | |
365 | * to what can be a 1, 2 or 4 byte quantity and always reads that | |
366 | * as a u32, which means that we have to correct the location of | |
367 | * the data read within those 32 bits for size 1 and 2 | |
368 | */ | |
369 | switch (size) { | |
370 | case 1: | |
371 | out_8(addr, val >> 24); | |
372 | return 1; | |
373 | case 2: | |
374 | if (port & 1) | |
375 | return -EINVAL; | |
376 | out_le16(addr, val >> 16); | |
377 | return 2; | |
378 | case 4: | |
379 | if (port & 3) | |
380 | return -EINVAL; | |
381 | out_le32(addr, val); | |
382 | return 4; | |
383 | } | |
384 | return -EINVAL; | |
385 | } | |
386 | ||
387 | /* This provides legacy IO or memory mmap access on a bus */ | |
388 | int pci_mmap_legacy_page_range(struct pci_bus *bus, | |
389 | struct vm_area_struct *vma, | |
390 | enum pci_mmap_state mmap_state) | |
391 | { | |
392 | struct pci_controller *hose = pci_bus_to_host(bus); | |
393 | resource_size_t offset = | |
394 | ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT; | |
395 | resource_size_t size = vma->vm_end - vma->vm_start; | |
396 | struct resource *rp; | |
397 | ||
398 | pr_debug("pci_mmap_legacy_page_range(%04x:%02x, %s @%llx..%llx)\n", | |
399 | pci_domain_nr(bus), bus->number, | |
400 | mmap_state == pci_mmap_mem ? "MEM" : "IO", | |
401 | (unsigned long long)offset, | |
402 | (unsigned long long)(offset + size - 1)); | |
403 | ||
404 | if (mmap_state == pci_mmap_mem) { | |
405 | /* Hack alert ! | |
406 | * | |
407 | * Because X is lame and can fail starting if it gets an error | |
408 | * trying to mmap legacy_mem (instead of just moving on without | |
409 | * legacy memory access) we fake it here by giving it anonymous | |
410 | * memory, effectively behaving just like /dev/zero | |
411 | */ | |
412 | if ((offset + size) > hose->isa_mem_size) { | |
79bf3a13 | 413 | #ifdef CONFIG_MMU |
6bd55f0b MS |
414 | pr_debug("Process %s (pid:%d) mapped non-existing PCI", |
415 | current->comm, current->pid); | |
416 | pr_debug("legacy memory for 0%04x:%02x\n", | |
417 | pci_domain_nr(bus), bus->number); | |
79bf3a13 | 418 | #endif |
d3afa58c MS |
419 | if (vma->vm_flags & VM_SHARED) |
420 | return shmem_zero_setup(vma); | |
421 | return 0; | |
422 | } | |
423 | offset += hose->isa_mem_phys; | |
424 | } else { | |
6bd55f0b | 425 | unsigned long io_offset = (unsigned long)hose->io_base_virt - |
d3afa58c MS |
426 | _IO_BASE; |
427 | unsigned long roffset = offset + io_offset; | |
428 | rp = &hose->io_resource; | |
429 | if (!(rp->flags & IORESOURCE_IO)) | |
430 | return -ENXIO; | |
431 | if (roffset < rp->start || (roffset + size) > rp->end) | |
432 | return -ENXIO; | |
433 | offset += hose->io_base_phys; | |
434 | } | |
435 | pr_debug(" -> mapping phys %llx\n", (unsigned long long)offset); | |
436 | ||
437 | vma->vm_pgoff = offset >> PAGE_SHIFT; | |
438 | vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); | |
439 | return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, | |
440 | vma->vm_end - vma->vm_start, | |
441 | vma->vm_page_prot); | |
442 | } | |
443 | ||
444 | void pci_resource_to_user(const struct pci_dev *dev, int bar, | |
445 | const struct resource *rsrc, | |
446 | resource_size_t *start, resource_size_t *end) | |
447 | { | |
0ad8f06d | 448 | struct pci_bus_region region; |
d3afa58c | 449 | |
0ad8f06d BH |
450 | if (rsrc->flags & IORESOURCE_IO) { |
451 | pcibios_resource_to_bus(dev->bus, ®ion, | |
452 | (struct resource *) rsrc); | |
453 | *start = region.start; | |
454 | *end = region.end; | |
d3afa58c | 455 | return; |
0ad8f06d | 456 | } |
d3afa58c | 457 | |
0ad8f06d BH |
458 | /* We pass a CPU physical address to userland for MMIO instead of a |
459 | * BAR value because X is lame and expects to be able to use that | |
460 | * to pass to /dev/mem! | |
d3afa58c | 461 | * |
0ad8f06d BH |
462 | * That means we may have 64-bit values where some apps only expect |
463 | * 32 (like X itself since it thinks only Sparc has 64-bit MMIO). | |
d3afa58c | 464 | */ |
0ad8f06d BH |
465 | *start = rsrc->start; |
466 | *end = rsrc->end; | |
d3afa58c MS |
467 | } |
468 | ||
469 | /** | |
470 | * pci_process_bridge_OF_ranges - Parse PCI bridge resources from device tree | |
471 | * @hose: newly allocated pci_controller to be setup | |
472 | * @dev: device node of the host bridge | |
473 | * @primary: set if primary bus (32 bits only, soon to be deprecated) | |
474 | * | |
475 | * This function will parse the "ranges" property of a PCI host bridge device | |
476 | * node and setup the resource mapping of a pci controller based on its | |
477 | * content. | |
478 | * | |
479 | * Life would be boring if it wasn't for a few issues that we have to deal | |
480 | * with here: | |
481 | * | |
482 | * - We can only cope with one IO space range and up to 3 Memory space | |
483 | * ranges. However, some machines (thanks Apple !) tend to split their | |
484 | * space into lots of small contiguous ranges. So we have to coalesce. | |
485 | * | |
486 | * - We can only cope with all memory ranges having the same offset | |
487 | * between CPU addresses and PCI addresses. Unfortunately, some bridges | |
488 | * are setup for a large 1:1 mapping along with a small "window" which | |
489 | * maps PCI address 0 to some arbitrary high address of the CPU space in | |
490 | * order to give access to the ISA memory hole. | |
491 | * The way out of here that I've chosen for now is to always set the | |
492 | * offset based on the first resource found, then override it if we | |
493 | * have a different offset and the previous was set by an ISA hole. | |
494 | * | |
495 | * - Some busses have IO space not starting at 0, which causes trouble with | |
496 | * the way we do our IO resource renumbering. The code somewhat deals with | |
497 | * it for 64 bits but I would expect problems on 32 bits. | |
498 | * | |
499 | * - Some 32 bits platforms such as 4xx can have physical space larger than | |
500 | * 32 bits so we need to use 64 bits values for the parsing | |
501 | */ | |
b881bc46 GKH |
502 | void pci_process_bridge_OF_ranges(struct pci_controller *hose, |
503 | struct device_node *dev, int primary) | |
d3afa58c | 504 | { |
d3afa58c | 505 | int memno = 0, isa_hole = -1; |
d3afa58c MS |
506 | unsigned long long isa_mb = 0; |
507 | struct resource *res; | |
4f7b6de4 AM |
508 | struct of_pci_range range; |
509 | struct of_pci_range_parser parser; | |
d3afa58c | 510 | |
6bd55f0b | 511 | pr_info("PCI host bridge %s %s ranges:\n", |
d3afa58c MS |
512 | dev->full_name, primary ? "(primary)" : ""); |
513 | ||
4f7b6de4 AM |
514 | /* Check for ranges property */ |
515 | if (of_pci_range_parser_init(&parser, dev)) | |
d3afa58c MS |
516 | return; |
517 | ||
d3afa58c | 518 | pr_debug("Parsing ranges property...\n"); |
4f7b6de4 | 519 | for_each_of_pci_range(&parser, &range) { |
d3afa58c | 520 | /* Read next ranges element */ |
6bd55f0b | 521 | pr_debug("pci_space: 0x%08x pci_addr:0x%016llx ", |
4f7b6de4 | 522 | range.pci_space, range.pci_addr); |
6bd55f0b | 523 | pr_debug("cpu_addr:0x%016llx size:0x%016llx\n", |
4f7b6de4 | 524 | range.cpu_addr, range.size); |
d3afa58c MS |
525 | |
526 | /* If we failed translation or got a zero-sized region | |
527 | * (some FW try to feed us with non sensical zero sized regions | |
528 | * such as power3 which look like some kind of attempt | |
529 | * at exposing the VGA memory hole) | |
530 | */ | |
4f7b6de4 | 531 | if (range.cpu_addr == OF_BAD_ADDR || range.size == 0) |
d3afa58c MS |
532 | continue; |
533 | ||
d3afa58c MS |
534 | /* Act based on address space type */ |
535 | res = NULL; | |
4f7b6de4 AM |
536 | switch (range.flags & IORESOURCE_TYPE_BITS) { |
537 | case IORESOURCE_IO: | |
6bd55f0b | 538 | pr_info(" IO 0x%016llx..0x%016llx -> 0x%016llx\n", |
4f7b6de4 AM |
539 | range.cpu_addr, range.cpu_addr + range.size - 1, |
540 | range.pci_addr); | |
d3afa58c MS |
541 | |
542 | /* We support only one IO range */ | |
543 | if (hose->pci_io_size) { | |
6bd55f0b | 544 | pr_info(" \\--> Skipped (too many) !\n"); |
d3afa58c MS |
545 | continue; |
546 | } | |
547 | /* On 32 bits, limit I/O space to 16MB */ | |
4f7b6de4 AM |
548 | if (range.size > 0x01000000) |
549 | range.size = 0x01000000; | |
d3afa58c MS |
550 | |
551 | /* 32 bits needs to map IOs here */ | |
4f7b6de4 AM |
552 | hose->io_base_virt = ioremap(range.cpu_addr, |
553 | range.size); | |
d3afa58c MS |
554 | |
555 | /* Expect trouble if pci_addr is not 0 */ | |
556 | if (primary) | |
557 | isa_io_base = | |
558 | (unsigned long)hose->io_base_virt; | |
559 | /* pci_io_size and io_base_phys always represent IO | |
560 | * space starting at 0 so we factor in pci_addr | |
561 | */ | |
4f7b6de4 AM |
562 | hose->pci_io_size = range.pci_addr + range.size; |
563 | hose->io_base_phys = range.cpu_addr - range.pci_addr; | |
d3afa58c MS |
564 | |
565 | /* Build resource */ | |
566 | res = &hose->io_resource; | |
4f7b6de4 AM |
567 | range.cpu_addr = range.pci_addr; |
568 | ||
d3afa58c | 569 | break; |
4f7b6de4 | 570 | case IORESOURCE_MEM: |
6bd55f0b | 571 | pr_info(" MEM 0x%016llx..0x%016llx -> 0x%016llx %s\n", |
4f7b6de4 AM |
572 | range.cpu_addr, range.cpu_addr + range.size - 1, |
573 | range.pci_addr, | |
574 | (range.pci_space & 0x40000000) ? | |
575 | "Prefetch" : ""); | |
d3afa58c MS |
576 | |
577 | /* We support only 3 memory ranges */ | |
578 | if (memno >= 3) { | |
6bd55f0b | 579 | pr_info(" \\--> Skipped (too many) !\n"); |
d3afa58c MS |
580 | continue; |
581 | } | |
582 | /* Handles ISA memory hole space here */ | |
4f7b6de4 AM |
583 | if (range.pci_addr == 0) { |
584 | isa_mb = range.cpu_addr; | |
d3afa58c MS |
585 | isa_hole = memno; |
586 | if (primary || isa_mem_base == 0) | |
4f7b6de4 AM |
587 | isa_mem_base = range.cpu_addr; |
588 | hose->isa_mem_phys = range.cpu_addr; | |
589 | hose->isa_mem_size = range.size; | |
d3afa58c MS |
590 | } |
591 | ||
592 | /* We get the PCI/Mem offset from the first range or | |
593 | * the, current one if the offset came from an ISA | |
594 | * hole. If they don't match, bugger. | |
595 | */ | |
596 | if (memno == 0 || | |
4f7b6de4 | 597 | (isa_hole >= 0 && range.pci_addr != 0 && |
d3afa58c | 598 | hose->pci_mem_offset == isa_mb)) |
4f7b6de4 AM |
599 | hose->pci_mem_offset = range.cpu_addr - |
600 | range.pci_addr; | |
601 | else if (range.pci_addr != 0 && | |
602 | hose->pci_mem_offset != range.cpu_addr - | |
603 | range.pci_addr) { | |
6bd55f0b | 604 | pr_info(" \\--> Skipped (offset mismatch) !\n"); |
d3afa58c MS |
605 | continue; |
606 | } | |
607 | ||
608 | /* Build resource */ | |
609 | res = &hose->mem_resources[memno++]; | |
d3afa58c MS |
610 | break; |
611 | } | |
70dcd942 MS |
612 | if (res != NULL) { |
613 | res->name = dev->full_name; | |
614 | res->flags = range.flags; | |
615 | res->start = range.cpu_addr; | |
616 | res->end = range.cpu_addr + range.size - 1; | |
617 | res->parent = res->child = res->sibling = NULL; | |
618 | } | |
d3afa58c MS |
619 | } |
620 | ||
621 | /* If there's an ISA hole and the pci_mem_offset is -not- matching | |
622 | * the ISA hole offset, then we need to remove the ISA hole from | |
623 | * the resource list for that brige | |
624 | */ | |
625 | if (isa_hole >= 0 && hose->pci_mem_offset != isa_mb) { | |
626 | unsigned int next = isa_hole + 1; | |
6bd55f0b | 627 | pr_info(" Removing ISA hole at 0x%016llx\n", isa_mb); |
d3afa58c MS |
628 | if (next < memno) |
629 | memmove(&hose->mem_resources[isa_hole], | |
630 | &hose->mem_resources[next], | |
631 | sizeof(struct resource) * (memno - next)); | |
632 | hose->mem_resources[--memno].flags = 0; | |
633 | } | |
634 | } | |
635 | ||
9413d968 | 636 | /* Display the domain number in /proc */ |
d3afa58c MS |
637 | int pci_proc_domain(struct pci_bus *bus) |
638 | { | |
9413d968 | 639 | return pci_domain_nr(bus); |
d3afa58c MS |
640 | } |
641 | ||
d3afa58c MS |
642 | /* This header fixup will do the resource fixup for all devices as they are |
643 | * probed, but not for bridge ranges | |
644 | */ | |
b881bc46 | 645 | static void pcibios_fixup_resources(struct pci_dev *dev) |
d3afa58c MS |
646 | { |
647 | struct pci_controller *hose = pci_bus_to_host(dev->bus); | |
648 | int i; | |
649 | ||
650 | if (!hose) { | |
6bd55f0b | 651 | pr_err("No host bridge for PCI dev %s !\n", |
d3afa58c MS |
652 | pci_name(dev)); |
653 | return; | |
654 | } | |
655 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { | |
656 | struct resource *res = dev->resource + i; | |
657 | if (!res->flags) | |
658 | continue; | |
e5b36841 | 659 | if (res->start == 0) { |
6bd55f0b | 660 | pr_debug("PCI:%s Resource %d %016llx-%016llx [%x]", |
d3afa58c MS |
661 | pci_name(dev), i, |
662 | (unsigned long long)res->start, | |
663 | (unsigned long long)res->end, | |
664 | (unsigned int)res->flags); | |
6bd55f0b | 665 | pr_debug("is unassigned\n"); |
d3afa58c MS |
666 | res->end -= res->start; |
667 | res->start = 0; | |
668 | res->flags |= IORESOURCE_UNSET; | |
669 | continue; | |
670 | } | |
671 | ||
aa23bdc0 | 672 | pr_debug("PCI:%s Resource %d %016llx-%016llx [%x]\n", |
d3afa58c | 673 | pci_name(dev), i, |
6bd55f0b | 674 | (unsigned long long)res->start, |
d3afa58c MS |
675 | (unsigned long long)res->end, |
676 | (unsigned int)res->flags); | |
d3afa58c MS |
677 | } |
678 | } | |
679 | DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_resources); | |
680 | ||
681 | /* This function tries to figure out if a bridge resource has been initialized | |
682 | * by the firmware or not. It doesn't have to be absolutely bullet proof, but | |
683 | * things go more smoothly when it gets it right. It should covers cases such | |
684 | * as Apple "closed" bridge resources and bare-metal pSeries unassigned bridges | |
685 | */ | |
b881bc46 GKH |
686 | static int pcibios_uninitialized_bridge_resource(struct pci_bus *bus, |
687 | struct resource *res) | |
d3afa58c MS |
688 | { |
689 | struct pci_controller *hose = pci_bus_to_host(bus); | |
690 | struct pci_dev *dev = bus->self; | |
691 | resource_size_t offset; | |
692 | u16 command; | |
693 | int i; | |
694 | ||
d3afa58c MS |
695 | /* Job is a bit different between memory and IO */ |
696 | if (res->flags & IORESOURCE_MEM) { | |
697 | /* If the BAR is non-0 (res != pci_mem_offset) then it's | |
698 | * probably been initialized by somebody | |
699 | */ | |
700 | if (res->start != hose->pci_mem_offset) | |
701 | return 0; | |
702 | ||
703 | /* The BAR is 0, let's check if memory decoding is enabled on | |
704 | * the bridge. If not, we consider it unassigned | |
705 | */ | |
706 | pci_read_config_word(dev, PCI_COMMAND, &command); | |
707 | if ((command & PCI_COMMAND_MEMORY) == 0) | |
708 | return 1; | |
709 | ||
710 | /* Memory decoding is enabled and the BAR is 0. If any of | |
711 | * the bridge resources covers that starting address (0 then | |
712 | * it's good enough for us for memory | |
713 | */ | |
714 | for (i = 0; i < 3; i++) { | |
715 | if ((hose->mem_resources[i].flags & IORESOURCE_MEM) && | |
716 | hose->mem_resources[i].start == hose->pci_mem_offset) | |
717 | return 0; | |
718 | } | |
719 | ||
720 | /* Well, it starts at 0 and we know it will collide so we may as | |
721 | * well consider it as unassigned. That covers the Apple case. | |
722 | */ | |
723 | return 1; | |
724 | } else { | |
725 | /* If the BAR is non-0, then we consider it assigned */ | |
726 | offset = (unsigned long)hose->io_base_virt - _IO_BASE; | |
727 | if (((res->start - offset) & 0xfffffffful) != 0) | |
728 | return 0; | |
729 | ||
730 | /* Here, we are a bit different than memory as typically IO | |
731 | * space starting at low addresses -is- valid. What we do | |
732 | * instead if that we consider as unassigned anything that | |
733 | * doesn't have IO enabled in the PCI command register, | |
734 | * and that's it. | |
735 | */ | |
736 | pci_read_config_word(dev, PCI_COMMAND, &command); | |
737 | if (command & PCI_COMMAND_IO) | |
738 | return 0; | |
739 | ||
740 | /* It's starting at 0 and IO is disabled in the bridge, consider | |
741 | * it unassigned | |
742 | */ | |
743 | return 1; | |
744 | } | |
745 | } | |
746 | ||
747 | /* Fixup resources of a PCI<->PCI bridge */ | |
b881bc46 | 748 | static void pcibios_fixup_bridge(struct pci_bus *bus) |
d3afa58c MS |
749 | { |
750 | struct resource *res; | |
751 | int i; | |
752 | ||
753 | struct pci_dev *dev = bus->self; | |
754 | ||
8a66da71 | 755 | pci_bus_for_each_resource(bus, res, i) { |
d3afa58c MS |
756 | if (!res) |
757 | continue; | |
758 | if (!res->flags) | |
759 | continue; | |
760 | if (i >= 3 && bus->self->transparent) | |
761 | continue; | |
762 | ||
763 | pr_debug("PCI:%s Bus rsrc %d %016llx-%016llx [%x] fixup...\n", | |
764 | pci_name(dev), i, | |
6bd55f0b | 765 | (unsigned long long)res->start, |
d3afa58c MS |
766 | (unsigned long long)res->end, |
767 | (unsigned int)res->flags); | |
768 | ||
d3afa58c MS |
769 | /* Try to detect uninitialized P2P bridge resources, |
770 | * and clear them out so they get re-assigned later | |
771 | */ | |
772 | if (pcibios_uninitialized_bridge_resource(bus, res)) { | |
773 | res->flags = 0; | |
774 | pr_debug("PCI:%s (unassigned)\n", | |
775 | pci_name(dev)); | |
776 | } else { | |
777 | pr_debug("PCI:%s %016llx-%016llx\n", | |
778 | pci_name(dev), | |
779 | (unsigned long long)res->start, | |
780 | (unsigned long long)res->end); | |
781 | } | |
782 | } | |
783 | } | |
784 | ||
b881bc46 | 785 | void pcibios_setup_bus_self(struct pci_bus *bus) |
d3afa58c MS |
786 | { |
787 | /* Fix up the bus resources for P2P bridges */ | |
788 | if (bus->self != NULL) | |
789 | pcibios_fixup_bridge(bus); | |
790 | } | |
791 | ||
b881bc46 | 792 | void pcibios_setup_bus_devices(struct pci_bus *bus) |
d3afa58c MS |
793 | { |
794 | struct pci_dev *dev; | |
795 | ||
796 | pr_debug("PCI: Fixup bus devices %d (%s)\n", | |
797 | bus->number, bus->self ? pci_name(bus->self) : "PHB"); | |
798 | ||
799 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
d3afa58c | 800 | /* Setup OF node pointer in archdata */ |
088ab302 | 801 | dev->dev.of_node = pci_device_to_OF_node(dev); |
d3afa58c MS |
802 | |
803 | /* Fixup NUMA node as it may not be setup yet by the generic | |
804 | * code and is needed by the DMA init | |
805 | */ | |
806 | set_dev_node(&dev->dev, pcibus_to_node(dev->bus)); | |
807 | ||
d3afa58c | 808 | /* Read default IRQs and fixup if necessary */ |
f27446c3 | 809 | dev->irq = of_irq_parse_and_map_pci(dev, 0, 0); |
d3afa58c MS |
810 | } |
811 | } | |
812 | ||
b881bc46 | 813 | void pcibios_fixup_bus(struct pci_bus *bus) |
d3afa58c | 814 | { |
01cf9d52 | 815 | /* nothing to do */ |
d3afa58c MS |
816 | } |
817 | EXPORT_SYMBOL(pcibios_fixup_bus); | |
818 | ||
d3afa58c MS |
819 | /* |
820 | * We need to avoid collisions with `mirrored' VGA ports | |
821 | * and other strange ISA hardware, so we always want the | |
822 | * addresses to be allocated in the 0x000-0x0ff region | |
823 | * modulo 0x400. | |
824 | * | |
825 | * Why? Because some silly external IO cards only decode | |
826 | * the low 10 bits of the IO address. The 0x00-0xff region | |
827 | * is reserved for motherboard devices that decode all 16 | |
828 | * bits, so it's ok to allocate at, say, 0x2800-0x28ff, | |
829 | * but we want to try to avoid allocating at 0x2900-0x2bff | |
830 | * which might have be mirrored at 0x0100-0x03ff.. | |
831 | */ | |
c86fac43 | 832 | resource_size_t pcibios_align_resource(void *data, const struct resource *res, |
d3afa58c MS |
833 | resource_size_t size, resource_size_t align) |
834 | { | |
01cf9d52 | 835 | return res->start; |
d3afa58c MS |
836 | } |
837 | EXPORT_SYMBOL(pcibios_align_resource); | |
838 | ||
01cf9d52 BKG |
839 | int pcibios_add_device(struct pci_dev *dev) |
840 | { | |
841 | dev->irq = of_irq_parse_and_map_pci(dev, 0, 0); | |
842 | ||
843 | return 0; | |
844 | } | |
845 | EXPORT_SYMBOL(pcibios_add_device); | |
846 | ||
d3afa58c MS |
847 | /* |
848 | * Reparent resource children of pr that conflict with res | |
849 | * under res, and make res replace those children. | |
850 | */ | |
851 | static int __init reparent_resources(struct resource *parent, | |
852 | struct resource *res) | |
853 | { | |
854 | struct resource *p, **pp; | |
855 | struct resource **firstpp = NULL; | |
856 | ||
857 | for (pp = &parent->child; (p = *pp) != NULL; pp = &p->sibling) { | |
858 | if (p->end < res->start) | |
859 | continue; | |
860 | if (res->end < p->start) | |
861 | break; | |
862 | if (p->start < res->start || p->end > res->end) | |
863 | return -1; /* not completely contained */ | |
864 | if (firstpp == NULL) | |
865 | firstpp = pp; | |
866 | } | |
867 | if (firstpp == NULL) | |
868 | return -1; /* didn't find any conflicting entries? */ | |
869 | res->parent = parent; | |
870 | res->child = *firstpp; | |
871 | res->sibling = *pp; | |
872 | *firstpp = res; | |
873 | *pp = NULL; | |
874 | for (p = res->child; p != NULL; p = p->sibling) { | |
875 | p->parent = res; | |
876 | pr_debug("PCI: Reparented %s [%llx..%llx] under %s\n", | |
877 | p->name, | |
878 | (unsigned long long)p->start, | |
879 | (unsigned long long)p->end, res->name); | |
880 | } | |
881 | return 0; | |
882 | } | |
883 | ||
884 | /* | |
885 | * Handle resources of PCI devices. If the world were perfect, we could | |
886 | * just allocate all the resource regions and do nothing more. It isn't. | |
887 | * On the other hand, we cannot just re-allocate all devices, as it would | |
888 | * require us to know lots of host bridge internals. So we attempt to | |
889 | * keep as much of the original configuration as possible, but tweak it | |
890 | * when it's found to be wrong. | |
891 | * | |
892 | * Known BIOS problems we have to work around: | |
893 | * - I/O or memory regions not configured | |
894 | * - regions configured, but not enabled in the command register | |
895 | * - bogus I/O addresses above 64K used | |
896 | * - expansion ROMs left enabled (this may sound harmless, but given | |
897 | * the fact the PCI specs explicitly allow address decoders to be | |
898 | * shared between expansion ROMs and other resource regions, it's | |
899 | * at least dangerous) | |
900 | * | |
901 | * Our solution: | |
902 | * (1) Allocate resources for all buses behind PCI-to-PCI bridges. | |
903 | * This gives us fixed barriers on where we can allocate. | |
904 | * (2) Allocate resources for all enabled devices. If there is | |
905 | * a collision, just mark the resource as unallocated. Also | |
906 | * disable expansion ROMs during this step. | |
907 | * (3) Try to allocate resources for disabled devices. If the | |
908 | * resources were assigned correctly, everything goes well, | |
909 | * if they weren't, they won't disturb allocation of other | |
910 | * resources. | |
911 | * (4) Assign new addresses to resources which were either | |
912 | * not configured at all or misconfigured. If explicitly | |
913 | * requested by the user, configure expansion ROM address | |
914 | * as well. | |
915 | */ | |
916 | ||
f7eaacc1 | 917 | static void pcibios_allocate_bus_resources(struct pci_bus *bus) |
d3afa58c MS |
918 | { |
919 | struct pci_bus *b; | |
920 | int i; | |
921 | struct resource *res, *pr; | |
922 | ||
923 | pr_debug("PCI: Allocating bus resources for %04x:%02x...\n", | |
924 | pci_domain_nr(bus), bus->number); | |
925 | ||
8a66da71 | 926 | pci_bus_for_each_resource(bus, res, i) { |
d3afa58c MS |
927 | if (!res || !res->flags |
928 | || res->start > res->end || res->parent) | |
929 | continue; | |
930 | if (bus->parent == NULL) | |
931 | pr = (res->flags & IORESOURCE_IO) ? | |
932 | &ioport_resource : &iomem_resource; | |
933 | else { | |
934 | /* Don't bother with non-root busses when | |
935 | * re-assigning all resources. We clear the | |
936 | * resource flags as if they were colliding | |
937 | * and as such ensure proper re-allocation | |
938 | * later. | |
939 | */ | |
d3afa58c MS |
940 | pr = pci_find_parent_resource(bus->self, res); |
941 | if (pr == res) { | |
942 | /* this happens when the generic PCI | |
943 | * code (wrongly) decides that this | |
944 | * bridge is transparent -- paulus | |
945 | */ | |
946 | continue; | |
947 | } | |
948 | } | |
949 | ||
6bd55f0b | 950 | pr_debug("PCI: %s (bus %d) bridge rsrc %d: %016llx-%016llx ", |
d3afa58c MS |
951 | bus->self ? pci_name(bus->self) : "PHB", |
952 | bus->number, i, | |
953 | (unsigned long long)res->start, | |
6bd55f0b MS |
954 | (unsigned long long)res->end); |
955 | pr_debug("[0x%x], parent %p (%s)\n", | |
d3afa58c MS |
956 | (unsigned int)res->flags, |
957 | pr, (pr && pr->name) ? pr->name : "nil"); | |
958 | ||
959 | if (pr && !(pr->flags & IORESOURCE_UNSET)) { | |
576e4385 YL |
960 | struct pci_dev *dev = bus->self; |
961 | ||
d3afa58c MS |
962 | if (request_resource(pr, res) == 0) |
963 | continue; | |
964 | /* | |
965 | * Must be a conflict with an existing entry. | |
966 | * Move that entry (or entries) under the | |
967 | * bridge resource and try again. | |
968 | */ | |
969 | if (reparent_resources(pr, res) == 0) | |
970 | continue; | |
576e4385 YL |
971 | |
972 | if (dev && i < PCI_BRIDGE_RESOURCE_NUM && | |
973 | pci_claim_bridge_resource(dev, | |
974 | i + PCI_BRIDGE_RESOURCES) == 0) | |
975 | continue; | |
976 | ||
d3afa58c | 977 | } |
6bd55f0b MS |
978 | pr_warn("PCI: Cannot allocate resource region "); |
979 | pr_cont("%d of PCI bridge %d, will remap\n", i, bus->number); | |
837c4ef1 | 980 | res->start = res->end = 0; |
d3afa58c MS |
981 | res->flags = 0; |
982 | } | |
983 | ||
984 | list_for_each_entry(b, &bus->children, node) | |
985 | pcibios_allocate_bus_resources(b); | |
986 | } | |
987 | ||
b881bc46 | 988 | static inline void alloc_resource(struct pci_dev *dev, int idx) |
d3afa58c MS |
989 | { |
990 | struct resource *pr, *r = &dev->resource[idx]; | |
991 | ||
992 | pr_debug("PCI: Allocating %s: Resource %d: %016llx..%016llx [%x]\n", | |
993 | pci_name(dev), idx, | |
994 | (unsigned long long)r->start, | |
995 | (unsigned long long)r->end, | |
996 | (unsigned int)r->flags); | |
997 | ||
998 | pr = pci_find_parent_resource(dev, r); | |
999 | if (!pr || (pr->flags & IORESOURCE_UNSET) || | |
1000 | request_resource(pr, r) < 0) { | |
6bd55f0b MS |
1001 | pr_warn("PCI: Cannot allocate resource region %d ", idx); |
1002 | pr_cont("of device %s, will remap\n", pci_name(dev)); | |
d3afa58c MS |
1003 | if (pr) |
1004 | pr_debug("PCI: parent is %p: %016llx-%016llx [%x]\n", | |
1005 | pr, | |
1006 | (unsigned long long)pr->start, | |
1007 | (unsigned long long)pr->end, | |
1008 | (unsigned int)pr->flags); | |
1009 | /* We'll assign a new address later */ | |
1010 | r->flags |= IORESOURCE_UNSET; | |
1011 | r->end -= r->start; | |
1012 | r->start = 0; | |
1013 | } | |
1014 | } | |
1015 | ||
1016 | static void __init pcibios_allocate_resources(int pass) | |
1017 | { | |
1018 | struct pci_dev *dev = NULL; | |
1019 | int idx, disabled; | |
1020 | u16 command; | |
1021 | struct resource *r; | |
1022 | ||
1023 | for_each_pci_dev(dev) { | |
1024 | pci_read_config_word(dev, PCI_COMMAND, &command); | |
1025 | for (idx = 0; idx <= PCI_ROM_RESOURCE; idx++) { | |
1026 | r = &dev->resource[idx]; | |
1027 | if (r->parent) /* Already allocated */ | |
1028 | continue; | |
1029 | if (!r->flags || (r->flags & IORESOURCE_UNSET)) | |
1030 | continue; /* Not assigned at all */ | |
1031 | /* We only allocate ROMs on pass 1 just in case they | |
1032 | * have been screwed up by firmware | |
1033 | */ | |
1034 | if (idx == PCI_ROM_RESOURCE) | |
1035 | disabled = 1; | |
1036 | if (r->flags & IORESOURCE_IO) | |
1037 | disabled = !(command & PCI_COMMAND_IO); | |
1038 | else | |
1039 | disabled = !(command & PCI_COMMAND_MEMORY); | |
1040 | if (pass == disabled) | |
1041 | alloc_resource(dev, idx); | |
1042 | } | |
1043 | if (pass) | |
1044 | continue; | |
1045 | r = &dev->resource[PCI_ROM_RESOURCE]; | |
1046 | if (r->flags) { | |
1047 | /* Turn the ROM off, leave the resource region, | |
1048 | * but keep it unregistered. | |
1049 | */ | |
1050 | u32 reg; | |
1051 | pci_read_config_dword(dev, dev->rom_base_reg, ®); | |
1052 | if (reg & PCI_ROM_ADDRESS_ENABLE) { | |
1053 | pr_debug("PCI: Switching off ROM of %s\n", | |
1054 | pci_name(dev)); | |
1055 | r->flags &= ~IORESOURCE_ROM_ENABLE; | |
1056 | pci_write_config_dword(dev, dev->rom_base_reg, | |
1057 | reg & ~PCI_ROM_ADDRESS_ENABLE); | |
1058 | } | |
1059 | } | |
1060 | } | |
1061 | } | |
1062 | ||
1063 | static void __init pcibios_reserve_legacy_regions(struct pci_bus *bus) | |
1064 | { | |
1065 | struct pci_controller *hose = pci_bus_to_host(bus); | |
1066 | resource_size_t offset; | |
1067 | struct resource *res, *pres; | |
1068 | int i; | |
1069 | ||
1070 | pr_debug("Reserving legacy ranges for domain %04x\n", | |
1071 | pci_domain_nr(bus)); | |
1072 | ||
1073 | /* Check for IO */ | |
1074 | if (!(hose->io_resource.flags & IORESOURCE_IO)) | |
1075 | goto no_io; | |
1076 | offset = (unsigned long)hose->io_base_virt - _IO_BASE; | |
1077 | res = kzalloc(sizeof(struct resource), GFP_KERNEL); | |
1078 | BUG_ON(res == NULL); | |
1079 | res->name = "Legacy IO"; | |
1080 | res->flags = IORESOURCE_IO; | |
1081 | res->start = offset; | |
1082 | res->end = (offset + 0xfff) & 0xfffffffful; | |
1083 | pr_debug("Candidate legacy IO: %pR\n", res); | |
1084 | if (request_resource(&hose->io_resource, res)) { | |
6bd55f0b | 1085 | pr_debug("PCI %04x:%02x Cannot reserve Legacy IO %pR\n", |
d3afa58c MS |
1086 | pci_domain_nr(bus), bus->number, res); |
1087 | kfree(res); | |
1088 | } | |
1089 | ||
1090 | no_io: | |
1091 | /* Check for memory */ | |
1092 | offset = hose->pci_mem_offset; | |
1093 | pr_debug("hose mem offset: %016llx\n", (unsigned long long)offset); | |
1094 | for (i = 0; i < 3; i++) { | |
1095 | pres = &hose->mem_resources[i]; | |
1096 | if (!(pres->flags & IORESOURCE_MEM)) | |
1097 | continue; | |
1098 | pr_debug("hose mem res: %pR\n", pres); | |
1099 | if ((pres->start - offset) <= 0xa0000 && | |
1100 | (pres->end - offset) >= 0xbffff) | |
1101 | break; | |
1102 | } | |
1103 | if (i >= 3) | |
1104 | return; | |
1105 | res = kzalloc(sizeof(struct resource), GFP_KERNEL); | |
1106 | BUG_ON(res == NULL); | |
1107 | res->name = "Legacy VGA memory"; | |
1108 | res->flags = IORESOURCE_MEM; | |
1109 | res->start = 0xa0000 + offset; | |
1110 | res->end = 0xbffff + offset; | |
1111 | pr_debug("Candidate VGA memory: %pR\n", res); | |
1112 | if (request_resource(pres, res)) { | |
6bd55f0b | 1113 | pr_debug("PCI %04x:%02x Cannot reserve VGA memory %pR\n", |
d3afa58c MS |
1114 | pci_domain_nr(bus), bus->number, res); |
1115 | kfree(res); | |
1116 | } | |
1117 | } | |
1118 | ||
1119 | void __init pcibios_resource_survey(void) | |
1120 | { | |
1121 | struct pci_bus *b; | |
1122 | ||
1123 | /* Allocate and assign resources. If we re-assign everything, then | |
1124 | * we skip the allocate phase | |
1125 | */ | |
1126 | list_for_each_entry(b, &pci_root_buses, node) | |
1127 | pcibios_allocate_bus_resources(b); | |
1128 | ||
e5b36841 BH |
1129 | pcibios_allocate_resources(0); |
1130 | pcibios_allocate_resources(1); | |
d3afa58c MS |
1131 | |
1132 | /* Before we start assigning unassigned resource, we try to reserve | |
1133 | * the low IO area and the VGA memory area if they intersect the | |
1134 | * bus available resources to avoid allocating things on top of them | |
1135 | */ | |
e5b36841 BH |
1136 | list_for_each_entry(b, &pci_root_buses, node) |
1137 | pcibios_reserve_legacy_regions(b); | |
d3afa58c | 1138 | |
e5b36841 BH |
1139 | /* Now proceed to assigning things that were left unassigned */ |
1140 | pr_debug("PCI: Assigning unassigned resources...\n"); | |
1141 | pci_assign_unassigned_resources(); | |
d3afa58c MS |
1142 | } |
1143 | ||
d3afa58c MS |
1144 | /* This is used by the PCI hotplug driver to allocate resource |
1145 | * of newly plugged busses. We can try to consolidate with the | |
1146 | * rest of the code later, for now, keep it as-is as our main | |
1147 | * resource allocation function doesn't deal with sub-trees yet. | |
1148 | */ | |
b881bc46 | 1149 | void pcibios_claim_one_bus(struct pci_bus *bus) |
d3afa58c MS |
1150 | { |
1151 | struct pci_dev *dev; | |
1152 | struct pci_bus *child_bus; | |
1153 | ||
1154 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
1155 | int i; | |
1156 | ||
1157 | for (i = 0; i < PCI_NUM_RESOURCES; i++) { | |
1158 | struct resource *r = &dev->resource[i]; | |
1159 | ||
1160 | if (r->parent || !r->start || !r->flags) | |
1161 | continue; | |
1162 | ||
6bd55f0b MS |
1163 | pr_debug("PCI: Claiming %s: ", pci_name(dev)); |
1164 | pr_debug("Resource %d: %016llx..%016llx [%x]\n", | |
1165 | i, (unsigned long long)r->start, | |
d3afa58c MS |
1166 | (unsigned long long)r->end, |
1167 | (unsigned int)r->flags); | |
1168 | ||
576e4385 YL |
1169 | if (pci_claim_resource(dev, i) == 0) |
1170 | continue; | |
1171 | ||
1172 | pci_claim_bridge_resource(dev, i); | |
d3afa58c MS |
1173 | } |
1174 | } | |
1175 | ||
1176 | list_for_each_entry(child_bus, &bus->children, node) | |
1177 | pcibios_claim_one_bus(child_bus); | |
1178 | } | |
1179 | EXPORT_SYMBOL_GPL(pcibios_claim_one_bus); | |
1180 | ||
1181 | ||
1182 | /* pcibios_finish_adding_to_bus | |
1183 | * | |
1184 | * This is to be called by the hotplug code after devices have been | |
1185 | * added to a bus, this include calling it for a PHB that is just | |
1186 | * being added | |
1187 | */ | |
1188 | void pcibios_finish_adding_to_bus(struct pci_bus *bus) | |
1189 | { | |
1190 | pr_debug("PCI: Finishing adding to hotplug bus %04x:%02x\n", | |
1191 | pci_domain_nr(bus), bus->number); | |
1192 | ||
1193 | /* Allocate bus and devices resources */ | |
1194 | pcibios_allocate_bus_resources(bus); | |
1195 | pcibios_claim_one_bus(bus); | |
1196 | ||
1197 | /* Add new devices to global lists. Register in proc, sysfs. */ | |
1198 | pci_bus_add_devices(bus); | |
1199 | ||
1200 | /* Fixup EEH */ | |
1ce2470a | 1201 | /* eeh_add_device_tree_late(bus); */ |
d3afa58c MS |
1202 | } |
1203 | EXPORT_SYMBOL_GPL(pcibios_finish_adding_to_bus); | |
1204 | ||
b881bc46 GKH |
1205 | static void pcibios_setup_phb_resources(struct pci_controller *hose, |
1206 | struct list_head *resources) | |
d3afa58c | 1207 | { |
5420e46d | 1208 | unsigned long io_offset; |
d3afa58c MS |
1209 | struct resource *res; |
1210 | int i; | |
1211 | ||
1212 | /* Hookup PHB IO resource */ | |
58de74b8 BH |
1213 | res = &hose->io_resource; |
1214 | ||
1215 | /* Fixup IO space offset */ | |
1216 | io_offset = (unsigned long)hose->io_base_virt - isa_io_base; | |
1217 | res->start = (res->start + io_offset) & 0xffffffffu; | |
1218 | res->end = (res->end + io_offset) & 0xffffffffu; | |
d3afa58c MS |
1219 | |
1220 | if (!res->flags) { | |
6bd55f0b MS |
1221 | pr_warn("PCI: I/O resource not set for host "); |
1222 | pr_cont("bridge %s (domain %d)\n", | |
1223 | hose->dn->full_name, hose->global_number); | |
d3afa58c MS |
1224 | /* Workaround for lack of IO resource only on 32-bit */ |
1225 | res->start = (unsigned long)hose->io_base_virt - isa_io_base; | |
1226 | res->end = res->start + IO_SPACE_LIMIT; | |
1227 | res->flags = IORESOURCE_IO; | |
1228 | } | |
f7eaacc1 MS |
1229 | pci_add_resource_offset(resources, res, |
1230 | (__force resource_size_t)(hose->io_base_virt - _IO_BASE)); | |
d3afa58c MS |
1231 | |
1232 | pr_debug("PCI: PHB IO resource = %016llx-%016llx [%lx]\n", | |
1233 | (unsigned long long)res->start, | |
1234 | (unsigned long long)res->end, | |
1235 | (unsigned long)res->flags); | |
1236 | ||
1237 | /* Hookup PHB Memory resources */ | |
1238 | for (i = 0; i < 3; ++i) { | |
1239 | res = &hose->mem_resources[i]; | |
1240 | if (!res->flags) { | |
1241 | if (i > 0) | |
1242 | continue; | |
6bd55f0b MS |
1243 | pr_err("PCI: Memory resource 0 not set for "); |
1244 | pr_cont("host bridge %s (domain %d)\n", | |
1245 | hose->dn->full_name, hose->global_number); | |
d3afa58c MS |
1246 | |
1247 | /* Workaround for lack of MEM resource only on 32-bit */ | |
1248 | res->start = hose->pci_mem_offset; | |
1249 | res->end = (resource_size_t)-1LL; | |
1250 | res->flags = IORESOURCE_MEM; | |
1251 | ||
1252 | } | |
aa23bdc0 | 1253 | pci_add_resource_offset(resources, res, hose->pci_mem_offset); |
d3afa58c MS |
1254 | |
1255 | pr_debug("PCI: PHB MEM resource %d = %016llx-%016llx [%lx]\n", | |
1256 | i, (unsigned long long)res->start, | |
1257 | (unsigned long long)res->end, | |
1258 | (unsigned long)res->flags); | |
1259 | } | |
1260 | ||
1261 | pr_debug("PCI: PHB MEM offset = %016llx\n", | |
1262 | (unsigned long long)hose->pci_mem_offset); | |
1263 | pr_debug("PCI: PHB IO offset = %08lx\n", | |
1264 | (unsigned long)hose->io_base_virt - _IO_BASE); | |
1265 | } | |
1266 | ||
b881bc46 | 1267 | static void pcibios_scan_phb(struct pci_controller *hose) |
bf13a6fa | 1268 | { |
58de74b8 | 1269 | LIST_HEAD(resources); |
bf13a6fa BH |
1270 | struct pci_bus *bus; |
1271 | struct device_node *node = hose->dn; | |
bf13a6fa | 1272 | |
74a7f084 | 1273 | pr_debug("PCI: Scanning PHB %s\n", of_node_full_name(node)); |
bf13a6fa | 1274 | |
58de74b8 BH |
1275 | pcibios_setup_phb_resources(hose, &resources); |
1276 | ||
4723b984 BH |
1277 | bus = pci_scan_root_bus(hose->parent, hose->first_busno, |
1278 | hose->ops, hose, &resources); | |
bf13a6fa | 1279 | if (bus == NULL) { |
6bd55f0b | 1280 | pr_err("Failed to create bus for PCI domain %04x\n", |
bf13a6fa | 1281 | hose->global_number); |
58de74b8 | 1282 | pci_free_resource_list(&resources); |
bf13a6fa BH |
1283 | return; |
1284 | } | |
b918c62e | 1285 | bus->busn_res.start = hose->first_busno; |
bf13a6fa BH |
1286 | hose->bus = bus; |
1287 | ||
b918c62e | 1288 | hose->last_busno = bus->busn_res.end; |
bf13a6fa BH |
1289 | } |
1290 | ||
1291 | static int __init pcibios_init(void) | |
1292 | { | |
1293 | struct pci_controller *hose, *tmp; | |
1294 | int next_busno = 0; | |
1295 | ||
6bd55f0b | 1296 | pr_info("PCI: Probing PCI hardware\n"); |
bf13a6fa BH |
1297 | |
1298 | /* Scan all of the recorded PCI controllers. */ | |
1299 | list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { | |
1300 | hose->last_busno = 0xff; | |
1301 | pcibios_scan_phb(hose); | |
bf13a6fa BH |
1302 | if (next_busno <= hose->last_busno) |
1303 | next_busno = hose->last_busno + 1; | |
1304 | } | |
1305 | pci_bus_count = next_busno; | |
1306 | ||
1307 | /* Call common code to handle resource allocation */ | |
1308 | pcibios_resource_survey(); | |
b97ea289 YW |
1309 | list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { |
1310 | if (hose->bus) | |
1311 | pci_bus_add_devices(hose->bus); | |
1312 | } | |
bf13a6fa BH |
1313 | |
1314 | return 0; | |
1315 | } | |
1316 | ||
1317 | subsys_initcall(pcibios_init); | |
1318 | ||
1319 | static struct pci_controller *pci_bus_to_hose(int bus) | |
1320 | { | |
1321 | struct pci_controller *hose, *tmp; | |
1322 | ||
1323 | list_for_each_entry_safe(hose, tmp, &hose_list, list_node) | |
1324 | if (bus >= hose->first_busno && bus <= hose->last_busno) | |
1325 | return hose; | |
1326 | return NULL; | |
1327 | } | |
1328 | ||
1329 | /* Provide information on locations of various I/O regions in physical | |
1330 | * memory. Do this on a per-card basis so that we choose the right | |
1331 | * root bridge. | |
1332 | * Note that the returned IO or memory base is a physical address | |
1333 | */ | |
1334 | ||
1335 | long sys_pciconfig_iobase(long which, unsigned long bus, unsigned long devfn) | |
1336 | { | |
1337 | struct pci_controller *hose; | |
1338 | long result = -EOPNOTSUPP; | |
1339 | ||
1340 | hose = pci_bus_to_hose(bus); | |
1341 | if (!hose) | |
1342 | return -ENODEV; | |
1343 | ||
1344 | switch (which) { | |
1345 | case IOBASE_BRIDGE_NUMBER: | |
1346 | return (long)hose->first_busno; | |
1347 | case IOBASE_MEMORY: | |
1348 | return (long)hose->pci_mem_offset; | |
1349 | case IOBASE_IO: | |
1350 | return (long)hose->io_base_phys; | |
1351 | case IOBASE_ISA_IO: | |
1352 | return (long)isa_io_base; | |
1353 | case IOBASE_ISA_MEM: | |
1354 | return (long)isa_mem_base; | |
1355 | } | |
1356 | ||
1357 | return result; | |
1358 | } | |
1359 | ||
d3afa58c MS |
1360 | /* |
1361 | * Null PCI config access functions, for the case when we can't | |
1362 | * find a hose. | |
1363 | */ | |
1364 | #define NULL_PCI_OP(rw, size, type) \ | |
1365 | static int \ | |
1366 | null_##rw##_config_##size(struct pci_dev *dev, int offset, type val) \ | |
1367 | { \ | |
1368 | return PCIBIOS_DEVICE_NOT_FOUND; \ | |
1369 | } | |
1370 | ||
1371 | static int | |
1372 | null_read_config(struct pci_bus *bus, unsigned int devfn, int offset, | |
1373 | int len, u32 *val) | |
1374 | { | |
1375 | return PCIBIOS_DEVICE_NOT_FOUND; | |
1376 | } | |
1377 | ||
1378 | static int | |
1379 | null_write_config(struct pci_bus *bus, unsigned int devfn, int offset, | |
1380 | int len, u32 val) | |
1381 | { | |
1382 | return PCIBIOS_DEVICE_NOT_FOUND; | |
1383 | } | |
1384 | ||
1385 | static struct pci_ops null_pci_ops = { | |
1386 | .read = null_read_config, | |
1387 | .write = null_write_config, | |
1388 | }; | |
1389 | ||
1390 | /* | |
1391 | * These functions are used early on before PCI scanning is done | |
1392 | * and all of the pci_dev and pci_bus structures have been created. | |
1393 | */ | |
1394 | static struct pci_bus * | |
1395 | fake_pci_bus(struct pci_controller *hose, int busnr) | |
1396 | { | |
1397 | static struct pci_bus bus; | |
1398 | ||
1399 | if (!hose) | |
6bd55f0b | 1400 | pr_err("Can't find hose for PCI bus %d!\n", busnr); |
d3afa58c MS |
1401 | |
1402 | bus.number = busnr; | |
1403 | bus.sysdata = hose; | |
1404 | bus.ops = hose ? hose->ops : &null_pci_ops; | |
1405 | return &bus; | |
1406 | } | |
1407 | ||
1408 | #define EARLY_PCI_OP(rw, size, type) \ | |
1409 | int early_##rw##_config_##size(struct pci_controller *hose, int bus, \ | |
1410 | int devfn, int offset, type value) \ | |
1411 | { \ | |
1412 | return pci_bus_##rw##_config_##size(fake_pci_bus(hose, bus), \ | |
1413 | devfn, offset, value); \ | |
1414 | } | |
1415 | ||
1416 | EARLY_PCI_OP(read, byte, u8 *) | |
1417 | EARLY_PCI_OP(read, word, u16 *) | |
1418 | EARLY_PCI_OP(read, dword, u32 *) | |
1419 | EARLY_PCI_OP(write, byte, u8) | |
1420 | EARLY_PCI_OP(write, word, u16) | |
1421 | EARLY_PCI_OP(write, dword, u32) | |
1422 | ||
1423 | int early_find_capability(struct pci_controller *hose, int bus, int devfn, | |
1424 | int cap) | |
1425 | { | |
1426 | return pci_bus_find_capability(fake_pci_bus(hose, bus), devfn, cap); | |
1427 | } | |
bf13a6fa | 1428 |