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1da177e4 LT |
1 | /* |
2 | * | |
3 | * BRIEF MODULE DESCRIPTION | |
4 | * The Descriptor Based DMA channel manager that first appeared | |
5 | * on the Au1550. I started with dma.c, but I think all that is | |
6 | * left is this initial comment :-) | |
7 | * | |
8 | * Copyright 2004 Embedded Edge, LLC | |
9 | * dan@embeddededge.com | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify it | |
12 | * under the terms of the GNU General Public License as published by the | |
13 | * Free Software Foundation; either version 2 of the License, or (at your | |
14 | * option) any later version. | |
15 | * | |
16 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED | |
17 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | |
18 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN | |
19 | * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, | |
20 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT | |
21 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF | |
22 | * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON | |
23 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
24 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | |
25 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
26 | * | |
27 | * You should have received a copy of the GNU General Public License along | |
28 | * with this program; if not, write to the Free Software Foundation, Inc., | |
29 | * 675 Mass Ave, Cambridge, MA 02139, USA. | |
30 | * | |
31 | */ | |
e3ad1c23 | 32 | |
1da177e4 | 33 | #include <linux/kernel.h> |
1da177e4 LT |
34 | #include <linux/slab.h> |
35 | #include <linux/spinlock.h> | |
1da177e4 | 36 | #include <linux/interrupt.h> |
2d32ffa4 | 37 | #include <linux/module.h> |
1da177e4 LT |
38 | #include <asm/mach-au1x00/au1000.h> |
39 | #include <asm/mach-au1x00/au1xxx_dbdma.h> | |
e3ad1c23 | 40 | |
1da177e4 LT |
41 | #if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200) |
42 | ||
43 | /* | |
44 | * The Descriptor Based DMA supports up to 16 channels. | |
45 | * | |
46 | * There are 32 devices defined. We keep an internal structure | |
47 | * of devices using these channels, along with additional | |
48 | * information. | |
49 | * | |
50 | * We allocate the descriptors and allow access to them through various | |
51 | * functions. The drivers allocate the data buffers and assign them | |
52 | * to the descriptors. | |
53 | */ | |
2f69ddcc | 54 | static DEFINE_SPINLOCK(au1xxx_dbdma_spin_lock); |
1da177e4 | 55 | |
c1dcb14e | 56 | /* I couldn't find a macro that did this... */ |
1da177e4 LT |
57 | #define ALIGN_ADDR(x, a) ((((u32)(x)) + (a-1)) & ~(a-1)) |
58 | ||
e3ad1c23 | 59 | static dbdma_global_t *dbdma_gptr = (dbdma_global_t *)DDMA_GLOBAL_BASE; |
c1dcb14e | 60 | static int dbdma_initialized; |
1da177e4 LT |
61 | static void au1xxx_dbdma_init(void); |
62 | ||
1da177e4 LT |
63 | static dbdev_tab_t dbdev_tab[] = { |
64 | #ifdef CONFIG_SOC_AU1550 | |
65 | /* UARTS */ | |
66 | { DSCR_CMD0_UART0_TX, DEV_FLAGS_OUT, 0, 8, 0x11100004, 0, 0 }, | |
67 | { DSCR_CMD0_UART0_RX, DEV_FLAGS_IN, 0, 8, 0x11100000, 0, 0 }, | |
68 | { DSCR_CMD0_UART3_TX, DEV_FLAGS_OUT, 0, 8, 0x11400004, 0, 0 }, | |
69 | { DSCR_CMD0_UART3_RX, DEV_FLAGS_IN, 0, 8, 0x11400000, 0, 0 }, | |
70 | ||
71 | /* EXT DMA */ | |
72 | { DSCR_CMD0_DMA_REQ0, 0, 0, 0, 0x00000000, 0, 0 }, | |
73 | { DSCR_CMD0_DMA_REQ1, 0, 0, 0, 0x00000000, 0, 0 }, | |
74 | { DSCR_CMD0_DMA_REQ2, 0, 0, 0, 0x00000000, 0, 0 }, | |
75 | { DSCR_CMD0_DMA_REQ3, 0, 0, 0, 0x00000000, 0, 0 }, | |
76 | ||
77 | /* USB DEV */ | |
78 | { DSCR_CMD0_USBDEV_RX0, DEV_FLAGS_IN, 4, 8, 0x10200000, 0, 0 }, | |
79 | { DSCR_CMD0_USBDEV_TX0, DEV_FLAGS_OUT, 4, 8, 0x10200004, 0, 0 }, | |
80 | { DSCR_CMD0_USBDEV_TX1, DEV_FLAGS_OUT, 4, 8, 0x10200008, 0, 0 }, | |
81 | { DSCR_CMD0_USBDEV_TX2, DEV_FLAGS_OUT, 4, 8, 0x1020000c, 0, 0 }, | |
82 | { DSCR_CMD0_USBDEV_RX3, DEV_FLAGS_IN, 4, 8, 0x10200010, 0, 0 }, | |
83 | { DSCR_CMD0_USBDEV_RX4, DEV_FLAGS_IN, 4, 8, 0x10200014, 0, 0 }, | |
84 | ||
85 | /* PSC 0 */ | |
86 | { DSCR_CMD0_PSC0_TX, DEV_FLAGS_OUT, 0, 0, 0x11a0001c, 0, 0 }, | |
87 | { DSCR_CMD0_PSC0_RX, DEV_FLAGS_IN, 0, 0, 0x11a0001c, 0, 0 }, | |
88 | ||
89 | /* PSC 1 */ | |
90 | { DSCR_CMD0_PSC1_TX, DEV_FLAGS_OUT, 0, 0, 0x11b0001c, 0, 0 }, | |
91 | { DSCR_CMD0_PSC1_RX, DEV_FLAGS_IN, 0, 0, 0x11b0001c, 0, 0 }, | |
92 | ||
93 | /* PSC 2 */ | |
94 | { DSCR_CMD0_PSC2_TX, DEV_FLAGS_OUT, 0, 0, 0x10a0001c, 0, 0 }, | |
95 | { DSCR_CMD0_PSC2_RX, DEV_FLAGS_IN, 0, 0, 0x10a0001c, 0, 0 }, | |
96 | ||
97 | /* PSC 3 */ | |
98 | { DSCR_CMD0_PSC3_TX, DEV_FLAGS_OUT, 0, 0, 0x10b0001c, 0, 0 }, | |
99 | { DSCR_CMD0_PSC3_RX, DEV_FLAGS_IN, 0, 0, 0x10b0001c, 0, 0 }, | |
100 | ||
101 | { DSCR_CMD0_PCI_WRITE, 0, 0, 0, 0x00000000, 0, 0 }, /* PCI */ | |
102 | { DSCR_CMD0_NAND_FLASH, 0, 0, 0, 0x00000000, 0, 0 }, /* NAND */ | |
103 | ||
104 | /* MAC 0 */ | |
105 | { DSCR_CMD0_MAC0_RX, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 }, | |
106 | { DSCR_CMD0_MAC0_TX, DEV_FLAGS_OUT, 0, 0, 0x00000000, 0, 0 }, | |
107 | ||
108 | /* MAC 1 */ | |
109 | { DSCR_CMD0_MAC1_RX, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 }, | |
110 | { DSCR_CMD0_MAC1_TX, DEV_FLAGS_OUT, 0, 0, 0x00000000, 0, 0 }, | |
111 | ||
112 | #endif /* CONFIG_SOC_AU1550 */ | |
113 | ||
114 | #ifdef CONFIG_SOC_AU1200 | |
115 | { DSCR_CMD0_UART0_TX, DEV_FLAGS_OUT, 0, 8, 0x11100004, 0, 0 }, | |
116 | { DSCR_CMD0_UART0_RX, DEV_FLAGS_IN, 0, 8, 0x11100000, 0, 0 }, | |
117 | { DSCR_CMD0_UART1_TX, DEV_FLAGS_OUT, 0, 8, 0x11200004, 0, 0 }, | |
118 | { DSCR_CMD0_UART1_RX, DEV_FLAGS_IN, 0, 8, 0x11200000, 0, 0 }, | |
119 | ||
120 | { DSCR_CMD0_DMA_REQ0, 0, 0, 0, 0x00000000, 0, 0 }, | |
121 | { DSCR_CMD0_DMA_REQ1, 0, 0, 0, 0x00000000, 0, 0 }, | |
122 | ||
123 | { DSCR_CMD0_MAE_BE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, | |
124 | { DSCR_CMD0_MAE_FE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, | |
125 | { DSCR_CMD0_MAE_BOTH, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, | |
126 | { DSCR_CMD0_LCD, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, | |
127 | ||
e3ad1c23 PP |
128 | { DSCR_CMD0_SDMS_TX0, DEV_FLAGS_OUT, 4, 8, 0x10600000, 0, 0 }, |
129 | { DSCR_CMD0_SDMS_RX0, DEV_FLAGS_IN, 4, 8, 0x10600004, 0, 0 }, | |
130 | { DSCR_CMD0_SDMS_TX1, DEV_FLAGS_OUT, 4, 8, 0x10680000, 0, 0 }, | |
131 | { DSCR_CMD0_SDMS_RX1, DEV_FLAGS_IN, 4, 8, 0x10680004, 0, 0 }, | |
1da177e4 | 132 | |
e3ad1c23 PP |
133 | { DSCR_CMD0_AES_RX, DEV_FLAGS_IN , 4, 32, 0x10300008, 0, 0 }, |
134 | { DSCR_CMD0_AES_TX, DEV_FLAGS_OUT, 4, 32, 0x10300004, 0, 0 }, | |
1da177e4 | 135 | |
13bb199f PP |
136 | { DSCR_CMD0_PSC0_TX, DEV_FLAGS_OUT, 0, 16, 0x11a0001c, 0, 0 }, |
137 | { DSCR_CMD0_PSC0_RX, DEV_FLAGS_IN, 0, 16, 0x11a0001c, 0, 0 }, | |
1da177e4 LT |
138 | { DSCR_CMD0_PSC0_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, |
139 | ||
13bb199f PP |
140 | { DSCR_CMD0_PSC1_TX, DEV_FLAGS_OUT, 0, 16, 0x11b0001c, 0, 0 }, |
141 | { DSCR_CMD0_PSC1_RX, DEV_FLAGS_IN, 0, 16, 0x11b0001c, 0, 0 }, | |
1da177e4 LT |
142 | { DSCR_CMD0_PSC1_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, |
143 | ||
e3ad1c23 PP |
144 | { DSCR_CMD0_CIM_RXA, DEV_FLAGS_IN, 0, 32, 0x14004020, 0, 0 }, |
145 | { DSCR_CMD0_CIM_RXB, DEV_FLAGS_IN, 0, 32, 0x14004040, 0, 0 }, | |
146 | { DSCR_CMD0_CIM_RXC, DEV_FLAGS_IN, 0, 32, 0x14004060, 0, 0 }, | |
1da177e4 LT |
147 | { DSCR_CMD0_CIM_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, |
148 | ||
149 | { DSCR_CMD0_NAND_FLASH, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 }, | |
150 | ||
c1dcb14e | 151 | #endif /* CONFIG_SOC_AU1200 */ |
1da177e4 LT |
152 | |
153 | { DSCR_CMD0_THROTTLE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, | |
154 | { DSCR_CMD0_ALWAYS, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, | |
e3ad1c23 PP |
155 | |
156 | /* Provide 16 user definable device types */ | |
0ec734c2 WO |
157 | { ~0, 0, 0, 0, 0, 0, 0 }, |
158 | { ~0, 0, 0, 0, 0, 0, 0 }, | |
159 | { ~0, 0, 0, 0, 0, 0, 0 }, | |
160 | { ~0, 0, 0, 0, 0, 0, 0 }, | |
161 | { ~0, 0, 0, 0, 0, 0, 0 }, | |
162 | { ~0, 0, 0, 0, 0, 0, 0 }, | |
163 | { ~0, 0, 0, 0, 0, 0, 0 }, | |
164 | { ~0, 0, 0, 0, 0, 0, 0 }, | |
165 | { ~0, 0, 0, 0, 0, 0, 0 }, | |
166 | { ~0, 0, 0, 0, 0, 0, 0 }, | |
167 | { ~0, 0, 0, 0, 0, 0, 0 }, | |
168 | { ~0, 0, 0, 0, 0, 0, 0 }, | |
169 | { ~0, 0, 0, 0, 0, 0, 0 }, | |
170 | { ~0, 0, 0, 0, 0, 0, 0 }, | |
171 | { ~0, 0, 0, 0, 0, 0, 0 }, | |
172 | { ~0, 0, 0, 0, 0, 0, 0 }, | |
1da177e4 LT |
173 | }; |
174 | ||
2b22c034 | 175 | #define DBDEV_TAB_SIZE ARRAY_SIZE(dbdev_tab) |
1da177e4 | 176 | |
ac15dad0 | 177 | #ifdef CONFIG_PM |
c2e32149 | 178 | static u32 au1xxx_dbdma_pm_regs[NUM_DBDMA_CHANS + 1][6]; |
ac15dad0 ML |
179 | #endif |
180 | ||
181 | ||
1da177e4 LT |
182 | static chan_tab_t *chan_tab_ptr[NUM_DBDMA_CHANS]; |
183 | ||
c1dcb14e | 184 | static dbdev_tab_t *find_dbdev_id(u32 id) |
1da177e4 LT |
185 | { |
186 | int i; | |
187 | dbdev_tab_t *p; | |
188 | for (i = 0; i < DBDEV_TAB_SIZE; ++i) { | |
189 | p = &dbdev_tab[i]; | |
190 | if (p->dev_id == id) | |
191 | return p; | |
192 | } | |
193 | return NULL; | |
194 | } | |
195 | ||
c1dcb14e | 196 | void *au1xxx_ddma_get_nextptr_virt(au1x_ddma_desc_t *dp) |
26a940e2 | 197 | { |
c1dcb14e | 198 | return phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr)); |
26a940e2 PP |
199 | } |
200 | EXPORT_SYMBOL(au1xxx_ddma_get_nextptr_virt); | |
201 | ||
c1dcb14e | 202 | u32 au1xxx_ddma_add_device(dbdev_tab_t *dev) |
e3ad1c23 PP |
203 | { |
204 | u32 ret = 0; | |
c1dcb14e SS |
205 | dbdev_tab_t *p; |
206 | static u16 new_id = 0x1000; | |
e3ad1c23 | 207 | |
0ec734c2 | 208 | p = find_dbdev_id(~0); |
c1dcb14e | 209 | if (NULL != p) { |
e3ad1c23 | 210 | memcpy(p, dev, sizeof(dbdev_tab_t)); |
21a151d8 | 211 | p->dev_id = DSCR_DEV2CUSTOM_ID(new_id, dev->dev_id); |
e3ad1c23 PP |
212 | ret = p->dev_id; |
213 | new_id++; | |
214 | #if 0 | |
c1dcb14e SS |
215 | printk(KERN_DEBUG "add_device: id:%x flags:%x padd:%x\n", |
216 | p->dev_id, p->dev_flags, p->dev_physaddr); | |
e3ad1c23 PP |
217 | #endif |
218 | } | |
219 | ||
220 | return ret; | |
221 | } | |
222 | EXPORT_SYMBOL(au1xxx_ddma_add_device); | |
223 | ||
ccdb0034 ML |
224 | void au1xxx_ddma_del_device(u32 devid) |
225 | { | |
226 | dbdev_tab_t *p = find_dbdev_id(devid); | |
227 | ||
228 | if (p != NULL) { | |
229 | memset(p, 0, sizeof(dbdev_tab_t)); | |
230 | p->dev_id = ~0; | |
231 | } | |
232 | } | |
233 | EXPORT_SYMBOL(au1xxx_ddma_del_device); | |
234 | ||
c1dcb14e SS |
235 | /* Allocate a channel and return a non-zero descriptor if successful. */ |
236 | u32 au1xxx_dbdma_chan_alloc(u32 srcid, u32 destid, | |
53e62d3a | 237 | void (*callback)(int, void *), void *callparam) |
1da177e4 LT |
238 | { |
239 | unsigned long flags; | |
240 | u32 used, chan, rv; | |
241 | u32 dcp; | |
242 | int i; | |
243 | dbdev_tab_t *stp, *dtp; | |
244 | chan_tab_t *ctp; | |
e3ad1c23 | 245 | au1x_dma_chan_t *cp; |
1da177e4 | 246 | |
c1dcb14e SS |
247 | /* |
248 | * We do the intialization on the first channel allocation. | |
1da177e4 LT |
249 | * We have to wait because of the interrupt handler initialization |
250 | * which can't be done successfully during board set up. | |
251 | */ | |
252 | if (!dbdma_initialized) | |
253 | au1xxx_dbdma_init(); | |
254 | dbdma_initialized = 1; | |
255 | ||
c1dcb14e SS |
256 | stp = find_dbdev_id(srcid); |
257 | if (stp == NULL) | |
53e62d3a | 258 | return 0; |
c1dcb14e SS |
259 | dtp = find_dbdev_id(destid); |
260 | if (dtp == NULL) | |
53e62d3a | 261 | return 0; |
1da177e4 LT |
262 | |
263 | used = 0; | |
264 | rv = 0; | |
265 | ||
c1dcb14e | 266 | /* Check to see if we can get both channels. */ |
1da177e4 LT |
267 | spin_lock_irqsave(&au1xxx_dbdma_spin_lock, flags); |
268 | if (!(stp->dev_flags & DEV_FLAGS_INUSE) || | |
269 | (stp->dev_flags & DEV_FLAGS_ANYUSE)) { | |
a3dddd56 | 270 | /* Got source */ |
1da177e4 LT |
271 | stp->dev_flags |= DEV_FLAGS_INUSE; |
272 | if (!(dtp->dev_flags & DEV_FLAGS_INUSE) || | |
273 | (dtp->dev_flags & DEV_FLAGS_ANYUSE)) { | |
274 | /* Got destination */ | |
275 | dtp->dev_flags |= DEV_FLAGS_INUSE; | |
c1dcb14e SS |
276 | } else { |
277 | /* Can't get dest. Release src. */ | |
1da177e4 LT |
278 | stp->dev_flags &= ~DEV_FLAGS_INUSE; |
279 | used++; | |
280 | } | |
c1dcb14e | 281 | } else |
1da177e4 | 282 | used++; |
1da177e4 LT |
283 | spin_unlock_irqrestore(&au1xxx_dbdma_spin_lock, flags); |
284 | ||
285 | if (!used) { | |
c1dcb14e | 286 | /* Let's see if we can allocate a channel for it. */ |
1da177e4 LT |
287 | ctp = NULL; |
288 | chan = 0; | |
289 | spin_lock_irqsave(&au1xxx_dbdma_spin_lock, flags); | |
c1dcb14e | 290 | for (i = 0; i < NUM_DBDMA_CHANS; i++) |
1da177e4 | 291 | if (chan_tab_ptr[i] == NULL) { |
c1dcb14e SS |
292 | /* |
293 | * If kmalloc fails, it is caught below same | |
1da177e4 LT |
294 | * as a channel not available. |
295 | */ | |
c0613894 | 296 | ctp = kmalloc(sizeof(chan_tab_t), GFP_ATOMIC); |
1da177e4 | 297 | chan_tab_ptr[i] = ctp; |
1da177e4 LT |
298 | break; |
299 | } | |
1da177e4 LT |
300 | spin_unlock_irqrestore(&au1xxx_dbdma_spin_lock, flags); |
301 | ||
302 | if (ctp != NULL) { | |
303 | memset(ctp, 0, sizeof(chan_tab_t)); | |
e3ad1c23 | 304 | ctp->chan_index = chan = i; |
1da177e4 LT |
305 | dcp = DDMA_CHANNEL_BASE; |
306 | dcp += (0x0100 * chan); | |
307 | ctp->chan_ptr = (au1x_dma_chan_t *)dcp; | |
e3ad1c23 | 308 | cp = (au1x_dma_chan_t *)dcp; |
1da177e4 LT |
309 | ctp->chan_src = stp; |
310 | ctp->chan_dest = dtp; | |
311 | ctp->chan_callback = callback; | |
312 | ctp->chan_callparam = callparam; | |
313 | ||
c1dcb14e | 314 | /* Initialize channel configuration. */ |
1da177e4 LT |
315 | i = 0; |
316 | if (stp->dev_intlevel) | |
317 | i |= DDMA_CFG_SED; | |
318 | if (stp->dev_intpolarity) | |
319 | i |= DDMA_CFG_SP; | |
320 | if (dtp->dev_intlevel) | |
321 | i |= DDMA_CFG_DED; | |
322 | if (dtp->dev_intpolarity) | |
323 | i |= DDMA_CFG_DP; | |
e3ad1c23 PP |
324 | if ((stp->dev_flags & DEV_FLAGS_SYNC) || |
325 | (dtp->dev_flags & DEV_FLAGS_SYNC)) | |
326 | i |= DDMA_CFG_SYNC; | |
1da177e4 LT |
327 | cp->ddma_cfg = i; |
328 | au_sync(); | |
329 | ||
330 | /* Return a non-zero value that can be used to | |
331 | * find the channel information in subsequent | |
332 | * operations. | |
333 | */ | |
334 | rv = (u32)(&chan_tab_ptr[chan]); | |
c1dcb14e | 335 | } else { |
e3ad1c23 | 336 | /* Release devices */ |
1da177e4 LT |
337 | stp->dev_flags &= ~DEV_FLAGS_INUSE; |
338 | dtp->dev_flags &= ~DEV_FLAGS_INUSE; | |
339 | } | |
340 | } | |
341 | return rv; | |
342 | } | |
e3ad1c23 | 343 | EXPORT_SYMBOL(au1xxx_dbdma_chan_alloc); |
1da177e4 | 344 | |
c1dcb14e SS |
345 | /* |
346 | * Set the device width if source or destination is a FIFO. | |
1da177e4 LT |
347 | * Should be 8, 16, or 32 bits. |
348 | */ | |
c1dcb14e | 349 | u32 au1xxx_dbdma_set_devwidth(u32 chanid, int bits) |
1da177e4 LT |
350 | { |
351 | u32 rv; | |
352 | chan_tab_t *ctp; | |
353 | dbdev_tab_t *stp, *dtp; | |
354 | ||
355 | ctp = *((chan_tab_t **)chanid); | |
356 | stp = ctp->chan_src; | |
357 | dtp = ctp->chan_dest; | |
358 | rv = 0; | |
359 | ||
360 | if (stp->dev_flags & DEV_FLAGS_IN) { /* Source in fifo */ | |
361 | rv = stp->dev_devwidth; | |
362 | stp->dev_devwidth = bits; | |
363 | } | |
364 | if (dtp->dev_flags & DEV_FLAGS_OUT) { /* Destination out fifo */ | |
365 | rv = dtp->dev_devwidth; | |
366 | dtp->dev_devwidth = bits; | |
367 | } | |
368 | ||
369 | return rv; | |
370 | } | |
e3ad1c23 | 371 | EXPORT_SYMBOL(au1xxx_dbdma_set_devwidth); |
1da177e4 | 372 | |
c1dcb14e SS |
373 | /* Allocate a descriptor ring, initializing as much as possible. */ |
374 | u32 au1xxx_dbdma_ring_alloc(u32 chanid, int entries) | |
1da177e4 LT |
375 | { |
376 | int i; | |
377 | u32 desc_base, srcid, destid; | |
378 | u32 cmd0, cmd1, src1, dest1; | |
379 | u32 src0, dest0; | |
380 | chan_tab_t *ctp; | |
381 | dbdev_tab_t *stp, *dtp; | |
382 | au1x_ddma_desc_t *dp; | |
383 | ||
c1dcb14e SS |
384 | /* |
385 | * I guess we could check this to be within the | |
1da177e4 LT |
386 | * range of the table...... |
387 | */ | |
388 | ctp = *((chan_tab_t **)chanid); | |
389 | stp = ctp->chan_src; | |
390 | dtp = ctp->chan_dest; | |
391 | ||
c1dcb14e SS |
392 | /* |
393 | * The descriptors must be 32-byte aligned. There is a | |
1da177e4 LT |
394 | * possibility the allocation will give us such an address, |
395 | * and if we try that first we are likely to not waste larger | |
396 | * slabs of memory. | |
397 | */ | |
e3ad1c23 | 398 | desc_base = (u32)kmalloc(entries * sizeof(au1x_ddma_desc_t), |
c1dcb14e | 399 | GFP_KERNEL|GFP_DMA); |
1da177e4 LT |
400 | if (desc_base == 0) |
401 | return 0; | |
402 | ||
403 | if (desc_base & 0x1f) { | |
c1dcb14e SS |
404 | /* |
405 | * Lost....do it again, allocate extra, and round | |
1da177e4 LT |
406 | * the address base. |
407 | */ | |
408 | kfree((const void *)desc_base); | |
409 | i = entries * sizeof(au1x_ddma_desc_t); | |
410 | i += (sizeof(au1x_ddma_desc_t) - 1); | |
c1dcb14e SS |
411 | desc_base = (u32)kmalloc(i, GFP_KERNEL|GFP_DMA); |
412 | if (desc_base == 0) | |
1da177e4 LT |
413 | return 0; |
414 | ||
22f4bb68 | 415 | ctp->cdb_membase = desc_base; |
1da177e4 | 416 | desc_base = ALIGN_ADDR(desc_base, sizeof(au1x_ddma_desc_t)); |
22f4bb68 ML |
417 | } else |
418 | ctp->cdb_membase = desc_base; | |
419 | ||
1da177e4 LT |
420 | dp = (au1x_ddma_desc_t *)desc_base; |
421 | ||
c1dcb14e | 422 | /* Keep track of the base descriptor. */ |
1da177e4 LT |
423 | ctp->chan_desc_base = dp; |
424 | ||
c1dcb14e | 425 | /* Initialize the rings with as much information as we know. */ |
1da177e4 LT |
426 | srcid = stp->dev_id; |
427 | destid = dtp->dev_id; | |
428 | ||
429 | cmd0 = cmd1 = src1 = dest1 = 0; | |
430 | src0 = dest0 = 0; | |
431 | ||
432 | cmd0 |= DSCR_CMD0_SID(srcid); | |
433 | cmd0 |= DSCR_CMD0_DID(destid); | |
434 | cmd0 |= DSCR_CMD0_IE | DSCR_CMD0_CV; | |
13bb199f PP |
435 | cmd0 |= DSCR_CMD0_ST(DSCR_CMD0_ST_NOCHANGE); |
436 | ||
c1dcb14e SS |
437 | /* Is it mem to mem transfer? */ |
438 | if (((DSCR_CUSTOM2DEV_ID(srcid) == DSCR_CMD0_THROTTLE) || | |
439 | (DSCR_CUSTOM2DEV_ID(srcid) == DSCR_CMD0_ALWAYS)) && | |
440 | ((DSCR_CUSTOM2DEV_ID(destid) == DSCR_CMD0_THROTTLE) || | |
441 | (DSCR_CUSTOM2DEV_ID(destid) == DSCR_CMD0_ALWAYS))) | |
442 | cmd0 |= DSCR_CMD0_MEM; | |
1da177e4 LT |
443 | |
444 | switch (stp->dev_devwidth) { | |
445 | case 8: | |
446 | cmd0 |= DSCR_CMD0_SW(DSCR_CMD0_BYTE); | |
447 | break; | |
448 | case 16: | |
449 | cmd0 |= DSCR_CMD0_SW(DSCR_CMD0_HALFWORD); | |
450 | break; | |
451 | case 32: | |
452 | default: | |
453 | cmd0 |= DSCR_CMD0_SW(DSCR_CMD0_WORD); | |
454 | break; | |
455 | } | |
456 | ||
457 | switch (dtp->dev_devwidth) { | |
458 | case 8: | |
459 | cmd0 |= DSCR_CMD0_DW(DSCR_CMD0_BYTE); | |
460 | break; | |
461 | case 16: | |
462 | cmd0 |= DSCR_CMD0_DW(DSCR_CMD0_HALFWORD); | |
463 | break; | |
464 | case 32: | |
465 | default: | |
466 | cmd0 |= DSCR_CMD0_DW(DSCR_CMD0_WORD); | |
467 | break; | |
468 | } | |
469 | ||
c1dcb14e SS |
470 | /* |
471 | * If the device is marked as an in/out FIFO, ensure it is | |
1da177e4 LT |
472 | * set non-coherent. |
473 | */ | |
474 | if (stp->dev_flags & DEV_FLAGS_IN) | |
c1dcb14e | 475 | cmd0 |= DSCR_CMD0_SN; /* Source in FIFO */ |
1da177e4 | 476 | if (dtp->dev_flags & DEV_FLAGS_OUT) |
c1dcb14e | 477 | cmd0 |= DSCR_CMD0_DN; /* Destination out FIFO */ |
1da177e4 | 478 | |
c1dcb14e SS |
479 | /* |
480 | * Set up source1. For now, assume no stride and increment. | |
1da177e4 LT |
481 | * A channel attribute update can change this later. |
482 | */ | |
483 | switch (stp->dev_tsize) { | |
484 | case 1: | |
485 | src1 |= DSCR_SRC1_STS(DSCR_xTS_SIZE1); | |
486 | break; | |
487 | case 2: | |
488 | src1 |= DSCR_SRC1_STS(DSCR_xTS_SIZE2); | |
489 | break; | |
490 | case 4: | |
491 | src1 |= DSCR_SRC1_STS(DSCR_xTS_SIZE4); | |
492 | break; | |
493 | case 8: | |
494 | default: | |
495 | src1 |= DSCR_SRC1_STS(DSCR_xTS_SIZE8); | |
496 | break; | |
497 | } | |
498 | ||
c1dcb14e | 499 | /* If source input is FIFO, set static address. */ |
1da177e4 | 500 | if (stp->dev_flags & DEV_FLAGS_IN) { |
c1dcb14e | 501 | if (stp->dev_flags & DEV_FLAGS_BURSTABLE) |
e3ad1c23 PP |
502 | src1 |= DSCR_SRC1_SAM(DSCR_xAM_BURST); |
503 | else | |
c1dcb14e | 504 | src1 |= DSCR_SRC1_SAM(DSCR_xAM_STATIC); |
1da177e4 | 505 | } |
c1dcb14e | 506 | |
e3ad1c23 PP |
507 | if (stp->dev_physaddr) |
508 | src0 = stp->dev_physaddr; | |
1da177e4 | 509 | |
c1dcb14e SS |
510 | /* |
511 | * Set up dest1. For now, assume no stride and increment. | |
1da177e4 LT |
512 | * A channel attribute update can change this later. |
513 | */ | |
514 | switch (dtp->dev_tsize) { | |
515 | case 1: | |
516 | dest1 |= DSCR_DEST1_DTS(DSCR_xTS_SIZE1); | |
517 | break; | |
518 | case 2: | |
519 | dest1 |= DSCR_DEST1_DTS(DSCR_xTS_SIZE2); | |
520 | break; | |
521 | case 4: | |
522 | dest1 |= DSCR_DEST1_DTS(DSCR_xTS_SIZE4); | |
523 | break; | |
524 | case 8: | |
525 | default: | |
526 | dest1 |= DSCR_DEST1_DTS(DSCR_xTS_SIZE8); | |
527 | break; | |
528 | } | |
529 | ||
c1dcb14e | 530 | /* If destination output is FIFO, set static address. */ |
1da177e4 | 531 | if (dtp->dev_flags & DEV_FLAGS_OUT) { |
c1dcb14e SS |
532 | if (dtp->dev_flags & DEV_FLAGS_BURSTABLE) |
533 | dest1 |= DSCR_DEST1_DAM(DSCR_xAM_BURST); | |
534 | else | |
535 | dest1 |= DSCR_DEST1_DAM(DSCR_xAM_STATIC); | |
1da177e4 | 536 | } |
c1dcb14e | 537 | |
e3ad1c23 PP |
538 | if (dtp->dev_physaddr) |
539 | dest0 = dtp->dev_physaddr; | |
1da177e4 | 540 | |
e3ad1c23 | 541 | #if 0 |
c1dcb14e SS |
542 | printk(KERN_DEBUG "did:%x sid:%x cmd0:%x cmd1:%x source0:%x " |
543 | "source1:%x dest0:%x dest1:%x\n", | |
544 | dtp->dev_id, stp->dev_id, cmd0, cmd1, src0, | |
545 | src1, dest0, dest1); | |
e3ad1c23 | 546 | #endif |
c1dcb14e | 547 | for (i = 0; i < entries; i++) { |
1da177e4 LT |
548 | dp->dscr_cmd0 = cmd0; |
549 | dp->dscr_cmd1 = cmd1; | |
550 | dp->dscr_source0 = src0; | |
551 | dp->dscr_source1 = src1; | |
552 | dp->dscr_dest0 = dest0; | |
553 | dp->dscr_dest1 = dest1; | |
554 | dp->dscr_stat = 0; | |
13bb199f PP |
555 | dp->sw_context = 0; |
556 | dp->sw_status = 0; | |
1da177e4 LT |
557 | dp->dscr_nxtptr = DSCR_NXTPTR(virt_to_phys(dp + 1)); |
558 | dp++; | |
559 | } | |
560 | ||
c1dcb14e | 561 | /* Make last descrptor point to the first. */ |
1da177e4 LT |
562 | dp--; |
563 | dp->dscr_nxtptr = DSCR_NXTPTR(virt_to_phys(ctp->chan_desc_base)); | |
564 | ctp->get_ptr = ctp->put_ptr = ctp->cur_ptr = ctp->chan_desc_base; | |
565 | ||
c1dcb14e | 566 | return (u32)ctp->chan_desc_base; |
1da177e4 | 567 | } |
e3ad1c23 | 568 | EXPORT_SYMBOL(au1xxx_dbdma_ring_alloc); |
1da177e4 | 569 | |
c1dcb14e SS |
570 | /* |
571 | * Put a source buffer into the DMA ring. | |
1da177e4 LT |
572 | * This updates the source pointer and byte count. Normally used |
573 | * for memory to fifo transfers. | |
574 | */ | |
c1dcb14e | 575 | u32 _au1xxx_dbdma_put_source(u32 chanid, void *buf, int nbytes, u32 flags) |
1da177e4 LT |
576 | { |
577 | chan_tab_t *ctp; | |
578 | au1x_ddma_desc_t *dp; | |
579 | ||
c1dcb14e SS |
580 | /* |
581 | * I guess we could check this to be within the | |
1da177e4 LT |
582 | * range of the table...... |
583 | */ | |
c1dcb14e | 584 | ctp = *(chan_tab_t **)chanid; |
1da177e4 | 585 | |
c1dcb14e SS |
586 | /* |
587 | * We should have multiple callers for a particular channel, | |
1da177e4 LT |
588 | * an interrupt doesn't affect this pointer nor the descriptor, |
589 | * so no locking should be needed. | |
590 | */ | |
591 | dp = ctp->put_ptr; | |
592 | ||
c1dcb14e SS |
593 | /* |
594 | * If the descriptor is valid, we are way ahead of the DMA | |
1da177e4 LT |
595 | * engine, so just return an error condition. |
596 | */ | |
c1dcb14e | 597 | if (dp->dscr_cmd0 & DSCR_CMD0_V) |
1da177e4 | 598 | return 0; |
1da177e4 | 599 | |
c1dcb14e | 600 | /* Load up buffer address and byte count. */ |
1da177e4 LT |
601 | dp->dscr_source0 = virt_to_phys(buf); |
602 | dp->dscr_cmd1 = nbytes; | |
c1dcb14e | 603 | /* Check flags */ |
e3ad1c23 PP |
604 | if (flags & DDMA_FLAGS_IE) |
605 | dp->dscr_cmd0 |= DSCR_CMD0_IE; | |
606 | if (flags & DDMA_FLAGS_NOIE) | |
607 | dp->dscr_cmd0 &= ~DSCR_CMD0_IE; | |
1da177e4 | 608 | |
e3ad1c23 PP |
609 | /* |
610 | * There is an errata on the Au1200/Au1550 parts that could result | |
c1dcb14e SS |
611 | * in "stale" data being DMA'ed. It has to do with the snoop logic on |
612 | * the cache eviction buffer. DMA_NONCOHERENT is on by default for | |
613 | * these parts. If it is fixed in the future, these dma_cache_inv will | |
e3ad1c23 | 614 | * just be nothing more than empty macros. See io.h. |
c1dcb14e | 615 | */ |
2d32ffa4 | 616 | dma_cache_wback_inv((unsigned long)buf, nbytes); |
c1dcb14e | 617 | dp->dscr_cmd0 |= DSCR_CMD0_V; /* Let it rip */ |
e3ad1c23 | 618 | au_sync(); |
42ecda1a | 619 | dma_cache_wback_inv((unsigned long)dp, sizeof(*dp)); |
c1dcb14e | 620 | ctp->chan_ptr->ddma_dbell = 0; |
e3ad1c23 | 621 | |
c1dcb14e | 622 | /* Get next descriptor pointer. */ |
13bb199f PP |
623 | ctp->put_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr)); |
624 | ||
c1dcb14e | 625 | /* Return something non-zero. */ |
1da177e4 LT |
626 | return nbytes; |
627 | } | |
e3ad1c23 | 628 | EXPORT_SYMBOL(_au1xxx_dbdma_put_source); |
1da177e4 LT |
629 | |
630 | /* Put a destination buffer into the DMA ring. | |
631 | * This updates the destination pointer and byte count. Normally used | |
632 | * to place an empty buffer into the ring for fifo to memory transfers. | |
633 | */ | |
634 | u32 | |
e3ad1c23 | 635 | _au1xxx_dbdma_put_dest(u32 chanid, void *buf, int nbytes, u32 flags) |
1da177e4 LT |
636 | { |
637 | chan_tab_t *ctp; | |
638 | au1x_ddma_desc_t *dp; | |
639 | ||
640 | /* I guess we could check this to be within the | |
641 | * range of the table...... | |
642 | */ | |
643 | ctp = *((chan_tab_t **)chanid); | |
644 | ||
645 | /* We should have multiple callers for a particular channel, | |
646 | * an interrupt doesn't affect this pointer nor the descriptor, | |
647 | * so no locking should be needed. | |
648 | */ | |
649 | dp = ctp->put_ptr; | |
650 | ||
651 | /* If the descriptor is valid, we are way ahead of the DMA | |
652 | * engine, so just return an error condition. | |
653 | */ | |
654 | if (dp->dscr_cmd0 & DSCR_CMD0_V) | |
655 | return 0; | |
656 | ||
e3ad1c23 PP |
657 | /* Load up buffer address and byte count */ |
658 | ||
659 | /* Check flags */ | |
660 | if (flags & DDMA_FLAGS_IE) | |
661 | dp->dscr_cmd0 |= DSCR_CMD0_IE; | |
662 | if (flags & DDMA_FLAGS_NOIE) | |
663 | dp->dscr_cmd0 &= ~DSCR_CMD0_IE; | |
664 | ||
1da177e4 LT |
665 | dp->dscr_dest0 = virt_to_phys(buf); |
666 | dp->dscr_cmd1 = nbytes; | |
e3ad1c23 | 667 | #if 0 |
c1dcb14e SS |
668 | printk(KERN_DEBUG "cmd0:%x cmd1:%x source0:%x source1:%x dest0:%x dest1:%x\n", |
669 | dp->dscr_cmd0, dp->dscr_cmd1, dp->dscr_source0, | |
670 | dp->dscr_source1, dp->dscr_dest0, dp->dscr_dest1); | |
e3ad1c23 PP |
671 | #endif |
672 | /* | |
673 | * There is an errata on the Au1200/Au1550 parts that could result in | |
c1dcb14e SS |
674 | * "stale" data being DMA'ed. It has to do with the snoop logic on the |
675 | * cache eviction buffer. DMA_NONCOHERENT is on by default for these | |
676 | * parts. If it is fixed in the future, these dma_cache_inv will just | |
e3ad1c23 | 677 | * be nothing more than empty macros. See io.h. |
c1dcb14e | 678 | */ |
21a151d8 | 679 | dma_cache_inv((unsigned long)buf, nbytes); |
1da177e4 | 680 | dp->dscr_cmd0 |= DSCR_CMD0_V; /* Let it rip */ |
e3ad1c23 | 681 | au_sync(); |
42ecda1a | 682 | dma_cache_wback_inv((unsigned long)dp, sizeof(*dp)); |
c1dcb14e | 683 | ctp->chan_ptr->ddma_dbell = 0; |
1da177e4 | 684 | |
c1dcb14e | 685 | /* Get next descriptor pointer. */ |
1da177e4 LT |
686 | ctp->put_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr)); |
687 | ||
c1dcb14e | 688 | /* Return something non-zero. */ |
1da177e4 LT |
689 | return nbytes; |
690 | } | |
e3ad1c23 | 691 | EXPORT_SYMBOL(_au1xxx_dbdma_put_dest); |
1da177e4 | 692 | |
c1dcb14e SS |
693 | /* |
694 | * Get a destination buffer into the DMA ring. | |
1da177e4 LT |
695 | * Normally used to get a full buffer from the ring during fifo |
696 | * to memory transfers. This does not set the valid bit, you will | |
697 | * have to put another destination buffer to keep the DMA going. | |
698 | */ | |
c1dcb14e | 699 | u32 au1xxx_dbdma_get_dest(u32 chanid, void **buf, int *nbytes) |
1da177e4 LT |
700 | { |
701 | chan_tab_t *ctp; | |
702 | au1x_ddma_desc_t *dp; | |
703 | u32 rv; | |
704 | ||
c1dcb14e SS |
705 | /* |
706 | * I guess we could check this to be within the | |
1da177e4 LT |
707 | * range of the table...... |
708 | */ | |
709 | ctp = *((chan_tab_t **)chanid); | |
710 | ||
c1dcb14e SS |
711 | /* |
712 | * We should have multiple callers for a particular channel, | |
1da177e4 LT |
713 | * an interrupt doesn't affect this pointer nor the descriptor, |
714 | * so no locking should be needed. | |
715 | */ | |
716 | dp = ctp->get_ptr; | |
717 | ||
c1dcb14e SS |
718 | /* |
719 | * If the descriptor is valid, we are way ahead of the DMA | |
1da177e4 LT |
720 | * engine, so just return an error condition. |
721 | */ | |
722 | if (dp->dscr_cmd0 & DSCR_CMD0_V) | |
723 | return 0; | |
724 | ||
c1dcb14e | 725 | /* Return buffer address and byte count. */ |
1da177e4 LT |
726 | *buf = (void *)(phys_to_virt(dp->dscr_dest0)); |
727 | *nbytes = dp->dscr_cmd1; | |
728 | rv = dp->dscr_stat; | |
729 | ||
c1dcb14e | 730 | /* Get next descriptor pointer. */ |
1da177e4 LT |
731 | ctp->get_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr)); |
732 | ||
c1dcb14e | 733 | /* Return something non-zero. */ |
1da177e4 LT |
734 | return rv; |
735 | } | |
3e2c6ef3 DP |
736 | EXPORT_SYMBOL_GPL(au1xxx_dbdma_get_dest); |
737 | ||
c1dcb14e | 738 | void au1xxx_dbdma_stop(u32 chanid) |
1da177e4 LT |
739 | { |
740 | chan_tab_t *ctp; | |
e3ad1c23 | 741 | au1x_dma_chan_t *cp; |
1da177e4 LT |
742 | int halt_timeout = 0; |
743 | ||
744 | ctp = *((chan_tab_t **)chanid); | |
745 | ||
746 | cp = ctp->chan_ptr; | |
747 | cp->ddma_cfg &= ~DDMA_CFG_EN; /* Disable channel */ | |
748 | au_sync(); | |
749 | while (!(cp->ddma_stat & DDMA_STAT_H)) { | |
750 | udelay(1); | |
751 | halt_timeout++; | |
752 | if (halt_timeout > 100) { | |
c1dcb14e | 753 | printk(KERN_WARNING "warning: DMA channel won't halt\n"); |
1da177e4 LT |
754 | break; |
755 | } | |
756 | } | |
757 | /* clear current desc valid and doorbell */ | |
758 | cp->ddma_stat |= (DDMA_STAT_DB | DDMA_STAT_V); | |
759 | au_sync(); | |
760 | } | |
e3ad1c23 | 761 | EXPORT_SYMBOL(au1xxx_dbdma_stop); |
1da177e4 | 762 | |
c1dcb14e SS |
763 | /* |
764 | * Start using the current descriptor pointer. If the DBDMA encounters | |
765 | * a non-valid descriptor, it will stop. In this case, we can just | |
1da177e4 LT |
766 | * continue by adding a buffer to the list and starting again. |
767 | */ | |
c1dcb14e | 768 | void au1xxx_dbdma_start(u32 chanid) |
1da177e4 LT |
769 | { |
770 | chan_tab_t *ctp; | |
e3ad1c23 | 771 | au1x_dma_chan_t *cp; |
1da177e4 LT |
772 | |
773 | ctp = *((chan_tab_t **)chanid); | |
1da177e4 LT |
774 | cp = ctp->chan_ptr; |
775 | cp->ddma_desptr = virt_to_phys(ctp->cur_ptr); | |
776 | cp->ddma_cfg |= DDMA_CFG_EN; /* Enable channel */ | |
777 | au_sync(); | |
e3ad1c23 | 778 | cp->ddma_dbell = 0; |
1da177e4 LT |
779 | au_sync(); |
780 | } | |
e3ad1c23 | 781 | EXPORT_SYMBOL(au1xxx_dbdma_start); |
1da177e4 | 782 | |
c1dcb14e | 783 | void au1xxx_dbdma_reset(u32 chanid) |
1da177e4 LT |
784 | { |
785 | chan_tab_t *ctp; | |
786 | au1x_ddma_desc_t *dp; | |
787 | ||
788 | au1xxx_dbdma_stop(chanid); | |
789 | ||
790 | ctp = *((chan_tab_t **)chanid); | |
791 | ctp->get_ptr = ctp->put_ptr = ctp->cur_ptr = ctp->chan_desc_base; | |
792 | ||
c1dcb14e | 793 | /* Run through the descriptors and reset the valid indicator. */ |
1da177e4 LT |
794 | dp = ctp->chan_desc_base; |
795 | ||
796 | do { | |
797 | dp->dscr_cmd0 &= ~DSCR_CMD0_V; | |
c1dcb14e SS |
798 | /* |
799 | * Reset our software status -- this is used to determine | |
800 | * if a descriptor is in use by upper level software. Since | |
e3ad1c23 PP |
801 | * posting can reset 'V' bit. |
802 | */ | |
803 | dp->sw_status = 0; | |
1da177e4 LT |
804 | dp = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr)); |
805 | } while (dp != ctp->chan_desc_base); | |
806 | } | |
e3ad1c23 | 807 | EXPORT_SYMBOL(au1xxx_dbdma_reset); |
1da177e4 | 808 | |
c1dcb14e | 809 | u32 au1xxx_get_dma_residue(u32 chanid) |
1da177e4 LT |
810 | { |
811 | chan_tab_t *ctp; | |
e3ad1c23 | 812 | au1x_dma_chan_t *cp; |
1da177e4 LT |
813 | u32 rv; |
814 | ||
815 | ctp = *((chan_tab_t **)chanid); | |
816 | cp = ctp->chan_ptr; | |
817 | ||
c1dcb14e | 818 | /* This is only valid if the channel is stopped. */ |
1da177e4 LT |
819 | rv = cp->ddma_bytecnt; |
820 | au_sync(); | |
821 | ||
822 | return rv; | |
823 | } | |
3e2c6ef3 DP |
824 | EXPORT_SYMBOL_GPL(au1xxx_get_dma_residue); |
825 | ||
c1dcb14e | 826 | void au1xxx_dbdma_chan_free(u32 chanid) |
1da177e4 LT |
827 | { |
828 | chan_tab_t *ctp; | |
829 | dbdev_tab_t *stp, *dtp; | |
830 | ||
831 | ctp = *((chan_tab_t **)chanid); | |
832 | stp = ctp->chan_src; | |
833 | dtp = ctp->chan_dest; | |
834 | ||
835 | au1xxx_dbdma_stop(chanid); | |
836 | ||
22f4bb68 | 837 | kfree((void *)ctp->cdb_membase); |
1da177e4 LT |
838 | |
839 | stp->dev_flags &= ~DEV_FLAGS_INUSE; | |
840 | dtp->dev_flags &= ~DEV_FLAGS_INUSE; | |
841 | chan_tab_ptr[ctp->chan_index] = NULL; | |
842 | ||
843 | kfree(ctp); | |
844 | } | |
e3ad1c23 | 845 | EXPORT_SYMBOL(au1xxx_dbdma_chan_free); |
1da177e4 | 846 | |
c1dcb14e | 847 | static irqreturn_t dbdma_interrupt(int irq, void *dev_id) |
1da177e4 | 848 | { |
2d32ffa4 PP |
849 | u32 intstat; |
850 | u32 chan_index; | |
1da177e4 LT |
851 | chan_tab_t *ctp; |
852 | au1x_ddma_desc_t *dp; | |
e3ad1c23 | 853 | au1x_dma_chan_t *cp; |
1da177e4 LT |
854 | |
855 | intstat = dbdma_gptr->ddma_intstat; | |
856 | au_sync(); | |
4b366732 | 857 | chan_index = __ffs(intstat); |
1da177e4 LT |
858 | |
859 | ctp = chan_tab_ptr[chan_index]; | |
860 | cp = ctp->chan_ptr; | |
861 | dp = ctp->cur_ptr; | |
862 | ||
c1dcb14e | 863 | /* Reset interrupt. */ |
1da177e4 LT |
864 | cp->ddma_irq = 0; |
865 | au_sync(); | |
866 | ||
867 | if (ctp->chan_callback) | |
c1dcb14e | 868 | ctp->chan_callback(irq, ctp->chan_callparam); |
1da177e4 LT |
869 | |
870 | ctp->cur_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr)); | |
2d32ffa4 | 871 | return IRQ_RETVAL(1); |
1da177e4 LT |
872 | } |
873 | ||
e3ad1c23 | 874 | static void au1xxx_dbdma_init(void) |
1da177e4 | 875 | { |
e3ad1c23 PP |
876 | int irq_nr; |
877 | ||
1da177e4 LT |
878 | dbdma_gptr->ddma_config = 0; |
879 | dbdma_gptr->ddma_throttle = 0; | |
880 | dbdma_gptr->ddma_inten = 0xffff; | |
881 | au_sync(); | |
882 | ||
e3ad1c23 PP |
883 | #if defined(CONFIG_SOC_AU1550) |
884 | irq_nr = AU1550_DDMA_INT; | |
885 | #elif defined(CONFIG_SOC_AU1200) | |
886 | irq_nr = AU1200_DDMA_INT; | |
887 | #else | |
888 | #error Unknown Au1x00 SOC | |
889 | #endif | |
890 | ||
f40298fd | 891 | if (request_irq(irq_nr, dbdma_interrupt, IRQF_DISABLED, |
1da177e4 | 892 | "Au1xxx dbdma", (void *)dbdma_gptr)) |
c1dcb14e | 893 | printk(KERN_ERR "Can't get 1550 dbdma irq"); |
1da177e4 LT |
894 | } |
895 | ||
c1dcb14e | 896 | void au1xxx_dbdma_dump(u32 chanid) |
1da177e4 | 897 | { |
c1dcb14e SS |
898 | chan_tab_t *ctp; |
899 | au1x_ddma_desc_t *dp; | |
900 | dbdev_tab_t *stp, *dtp; | |
901 | au1x_dma_chan_t *cp; | |
902 | u32 i = 0; | |
1da177e4 LT |
903 | |
904 | ctp = *((chan_tab_t **)chanid); | |
905 | stp = ctp->chan_src; | |
906 | dtp = ctp->chan_dest; | |
907 | cp = ctp->chan_ptr; | |
908 | ||
c1dcb14e SS |
909 | printk(KERN_DEBUG "Chan %x, stp %x (dev %d) dtp %x (dev %d) \n", |
910 | (u32)ctp, (u32)stp, stp - dbdev_tab, (u32)dtp, | |
911 | dtp - dbdev_tab); | |
912 | printk(KERN_DEBUG "desc base %x, get %x, put %x, cur %x\n", | |
913 | (u32)(ctp->chan_desc_base), (u32)(ctp->get_ptr), | |
914 | (u32)(ctp->put_ptr), (u32)(ctp->cur_ptr)); | |
915 | ||
916 | printk(KERN_DEBUG "dbdma chan %x\n", (u32)cp); | |
917 | printk(KERN_DEBUG "cfg %08x, desptr %08x, statptr %08x\n", | |
918 | cp->ddma_cfg, cp->ddma_desptr, cp->ddma_statptr); | |
919 | printk(KERN_DEBUG "dbell %08x, irq %08x, stat %08x, bytecnt %08x\n", | |
920 | cp->ddma_dbell, cp->ddma_irq, cp->ddma_stat, | |
921 | cp->ddma_bytecnt); | |
922 | ||
923 | /* Run through the descriptors */ | |
1da177e4 LT |
924 | dp = ctp->chan_desc_base; |
925 | ||
926 | do { | |
c1dcb14e SS |
927 | printk(KERN_DEBUG "Dp[%d]= %08x, cmd0 %08x, cmd1 %08x\n", |
928 | i++, (u32)dp, dp->dscr_cmd0, dp->dscr_cmd1); | |
929 | printk(KERN_DEBUG "src0 %08x, src1 %08x, dest0 %08x, dest1 %08x\n", | |
930 | dp->dscr_source0, dp->dscr_source1, | |
931 | dp->dscr_dest0, dp->dscr_dest1); | |
932 | printk(KERN_DEBUG "stat %08x, nxtptr %08x\n", | |
933 | dp->dscr_stat, dp->dscr_nxtptr); | |
1da177e4 LT |
934 | dp = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr)); |
935 | } while (dp != ctp->chan_desc_base); | |
936 | } | |
937 | ||
e3ad1c23 PP |
938 | /* Put a descriptor into the DMA ring. |
939 | * This updates the source/destination pointers and byte count. | |
940 | */ | |
c1dcb14e | 941 | u32 au1xxx_dbdma_put_dscr(u32 chanid, au1x_ddma_desc_t *dscr) |
e3ad1c23 PP |
942 | { |
943 | chan_tab_t *ctp; | |
944 | au1x_ddma_desc_t *dp; | |
c1dcb14e | 945 | u32 nbytes = 0; |
e3ad1c23 | 946 | |
c1dcb14e SS |
947 | /* |
948 | * I guess we could check this to be within the | |
949 | * range of the table...... | |
950 | */ | |
e3ad1c23 PP |
951 | ctp = *((chan_tab_t **)chanid); |
952 | ||
c1dcb14e SS |
953 | /* |
954 | * We should have multiple callers for a particular channel, | |
955 | * an interrupt doesn't affect this pointer nor the descriptor, | |
956 | * so no locking should be needed. | |
957 | */ | |
e3ad1c23 PP |
958 | dp = ctp->put_ptr; |
959 | ||
c1dcb14e SS |
960 | /* |
961 | * If the descriptor is valid, we are way ahead of the DMA | |
962 | * engine, so just return an error condition. | |
963 | */ | |
e3ad1c23 PP |
964 | if (dp->dscr_cmd0 & DSCR_CMD0_V) |
965 | return 0; | |
966 | ||
c1dcb14e | 967 | /* Load up buffer addresses and byte count. */ |
e3ad1c23 PP |
968 | dp->dscr_dest0 = dscr->dscr_dest0; |
969 | dp->dscr_source0 = dscr->dscr_source0; | |
970 | dp->dscr_dest1 = dscr->dscr_dest1; | |
971 | dp->dscr_source1 = dscr->dscr_source1; | |
972 | dp->dscr_cmd1 = dscr->dscr_cmd1; | |
973 | nbytes = dscr->dscr_cmd1; | |
974 | /* Allow the caller to specifiy if an interrupt is generated */ | |
975 | dp->dscr_cmd0 &= ~DSCR_CMD0_IE; | |
976 | dp->dscr_cmd0 |= dscr->dscr_cmd0 | DSCR_CMD0_V; | |
977 | ctp->chan_ptr->ddma_dbell = 0; | |
978 | ||
c1dcb14e | 979 | /* Get next descriptor pointer. */ |
e3ad1c23 PP |
980 | ctp->put_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr)); |
981 | ||
c1dcb14e | 982 | /* Return something non-zero. */ |
e3ad1c23 PP |
983 | return nbytes; |
984 | } | |
985 | ||
ac15dad0 ML |
986 | #ifdef CONFIG_PM |
987 | void au1xxx_dbdma_suspend(void) | |
988 | { | |
989 | int i; | |
990 | u32 addr; | |
991 | ||
992 | addr = DDMA_GLOBAL_BASE; | |
993 | au1xxx_dbdma_pm_regs[0][0] = au_readl(addr + 0x00); | |
994 | au1xxx_dbdma_pm_regs[0][1] = au_readl(addr + 0x04); | |
995 | au1xxx_dbdma_pm_regs[0][2] = au_readl(addr + 0x08); | |
996 | au1xxx_dbdma_pm_regs[0][3] = au_readl(addr + 0x0c); | |
997 | ||
998 | /* save channel configurations */ | |
c2e32149 | 999 | for (i = 1, addr = DDMA_CHANNEL_BASE; i <= NUM_DBDMA_CHANS; i++) { |
ac15dad0 ML |
1000 | au1xxx_dbdma_pm_regs[i][0] = au_readl(addr + 0x00); |
1001 | au1xxx_dbdma_pm_regs[i][1] = au_readl(addr + 0x04); | |
1002 | au1xxx_dbdma_pm_regs[i][2] = au_readl(addr + 0x08); | |
1003 | au1xxx_dbdma_pm_regs[i][3] = au_readl(addr + 0x0c); | |
1004 | au1xxx_dbdma_pm_regs[i][4] = au_readl(addr + 0x10); | |
1005 | au1xxx_dbdma_pm_regs[i][5] = au_readl(addr + 0x14); | |
ac15dad0 ML |
1006 | |
1007 | /* halt channel */ | |
1008 | au_writel(au1xxx_dbdma_pm_regs[i][0] & ~1, addr + 0x00); | |
1009 | au_sync(); | |
1010 | while (!(au_readl(addr + 0x14) & 1)) | |
1011 | au_sync(); | |
1012 | ||
1013 | addr += 0x100; /* next channel base */ | |
1014 | } | |
1015 | /* disable channel interrupts */ | |
1016 | au_writel(0, DDMA_GLOBAL_BASE + 0x0c); | |
1017 | au_sync(); | |
1018 | } | |
1019 | ||
1020 | void au1xxx_dbdma_resume(void) | |
1021 | { | |
1022 | int i; | |
1023 | u32 addr; | |
1024 | ||
1025 | addr = DDMA_GLOBAL_BASE; | |
1026 | au_writel(au1xxx_dbdma_pm_regs[0][0], addr + 0x00); | |
1027 | au_writel(au1xxx_dbdma_pm_regs[0][1], addr + 0x04); | |
1028 | au_writel(au1xxx_dbdma_pm_regs[0][2], addr + 0x08); | |
1029 | au_writel(au1xxx_dbdma_pm_regs[0][3], addr + 0x0c); | |
1030 | ||
1031 | /* restore channel configurations */ | |
c2e32149 | 1032 | for (i = 1, addr = DDMA_CHANNEL_BASE; i <= NUM_DBDMA_CHANS; i++) { |
ac15dad0 ML |
1033 | au_writel(au1xxx_dbdma_pm_regs[i][0], addr + 0x00); |
1034 | au_writel(au1xxx_dbdma_pm_regs[i][1], addr + 0x04); | |
1035 | au_writel(au1xxx_dbdma_pm_regs[i][2], addr + 0x08); | |
1036 | au_writel(au1xxx_dbdma_pm_regs[i][3], addr + 0x0c); | |
1037 | au_writel(au1xxx_dbdma_pm_regs[i][4], addr + 0x10); | |
1038 | au_writel(au1xxx_dbdma_pm_regs[i][5], addr + 0x14); | |
ac15dad0 ML |
1039 | au_sync(); |
1040 | addr += 0x100; /* next channel base */ | |
1041 | } | |
1042 | } | |
1043 | #endif /* CONFIG_PM */ | |
1da177e4 | 1044 | #endif /* defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200) */ |