[mirror_ubuntu-artful-kernel.git] / arch / mips / alchemy / common / gpio.c

/*
 *  Copyright (C) 2007-2009, OpenWrt.org, Florian Fainelli <florian@openwrt.org>
 *  	Architecture specific GPIO support
 *
 *  This program is free software; you can redistribute	 it and/or modify it
 *  under  the terms of	 the GNU General  Public License as published by the
 *  Free Software Foundation;  either version 2 of the	License, or (at your
 *  option) any later version.
 *
 *  THIS  SOFTWARE  IS PROVIDED	  ``AS	IS'' AND   ANY	EXPRESS OR IMPLIED
 *  WARRANTIES,	  INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
 *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
 *  NO	EVENT  SHALL   THE AUTHOR  BE	 LIABLE FOR ANY	  DIRECT, INDIRECT,
 *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 *  NOT LIMITED	  TO, PROCUREMENT OF  SUBSTITUTE GOODS	OR SERVICES; LOSS OF
 *  USE, DATA,	OR PROFITS; OR	BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
 *  ANY THEORY OF LIABILITY, WHETHER IN	 CONTRACT, STRICT LIABILITY, OR TORT
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 *  You should have received a copy of the  GNU General Public License along
 *  with this program; if not, write  to the Free Software Foundation, Inc.,
 *  675 Mass Ave, Cambridge, MA 02139, USA.
 *
 *  Notes :
 * 	au1000 SoC have only one GPIO line : GPIO1
 * 	others have a second one : GPIO2
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/types.h>
#include <linux/platform_device.h>
#include <linux/gpio.h>

#include <asm/mach-au1x00/au1000.h>
#include <asm/gpio.h>

struct au1000_gpio_chip {
	struct gpio_chip	chip;
	void __iomem		*regbase;
};

#if !defined(CONFIG_SOC_AU1000)
static int au1000_gpio2_get(struct gpio_chip *chip, unsigned offset)
{
	u32 mask = 1 << offset;
	struct au1000_gpio_chip *gpch;

	gpch = container_of(chip, struct au1000_gpio_chip, chip);
	return readl(gpch->regbase + AU1000_GPIO2_ST) & mask;
}

static void au1000_gpio2_set(struct gpio_chip *chip,
				unsigned offset, int value)
{
	u32 mask = ((GPIO2_OUT_EN_MASK << offset) | (!!value << offset));
	struct au1000_gpio_chip *gpch;
	unsigned long flags;

	gpch = container_of(chip, struct au1000_gpio_chip, chip);

	local_irq_save(flags);
	writel(mask, gpch->regbase + AU1000_GPIO2_OUT);
	local_irq_restore(flags);
}

static int au1000_gpio2_direction_input(struct gpio_chip *chip, unsigned offset)
{
	u32 mask = 1 << offset;
	u32 tmp;
	struct au1000_gpio_chip *gpch;
	unsigned long flags;

	gpch = container_of(chip, struct au1000_gpio_chip, chip);

	local_irq_save(flags);
	tmp = readl(gpch->regbase + AU1000_GPIO2_DIR);
	tmp &= ~mask;
	writel(tmp, gpch->regbase + AU1000_GPIO2_DIR);
	local_irq_restore(flags);

	return 0;
}

static int au1000_gpio2_direction_output(struct gpio_chip *chip,
					unsigned offset, int value)
{
	u32 mask = 1 << offset;
	u32 out_mask = ((GPIO2_OUT_EN_MASK << offset) | (!!value << offset));
	u32 tmp;
	struct au1000_gpio_chip *gpch;
	unsigned long flags;

	gpch = container_of(chip, struct au1000_gpio_chip, chip);

	local_irq_save(flags);
	tmp = readl(gpch->regbase + AU1000_GPIO2_DIR);
	tmp |= mask;
	writel(tmp, gpch->regbase + AU1000_GPIO2_DIR);
	writel(out_mask, gpch->regbase + AU1000_GPIO2_OUT);
	local_irq_restore(flags);

	return 0;
}
#endif /* !defined(CONFIG_SOC_AU1000) */

static int au1000_gpio1_get(struct gpio_chip *chip, unsigned offset)
{
	u32 mask = 1 << offset;
	struct au1000_gpio_chip *gpch;

	gpch = container_of(chip, struct au1000_gpio_chip, chip);
	return readl(gpch->regbase + AU1000_GPIO1_ST) & mask;
}

static void au1000_gpio1_set(struct gpio_chip *chip,
				unsigned offset, int value)
{
	u32 mask = 1 << offset;
	u32 reg_offset;
	struct au1000_gpio_chip *gpch;
	unsigned long flags;

	gpch = container_of(chip, struct au1000_gpio_chip, chip);

	if (value)
		reg_offset = AU1000_GPIO1_OUT;
	else
		reg_offset = AU1000_GPIO1_CLR;

	local_irq_save(flags);
	writel(mask, gpch->regbase + reg_offset);
	local_irq_restore(flags);
}

static int au1000_gpio1_direction_input(struct gpio_chip *chip, unsigned offset)
{
	u32 mask = 1 << offset;
	struct au1000_gpio_chip *gpch;

	gpch = container_of(chip, struct au1000_gpio_chip, chip);
	writel(mask, gpch->regbase + AU1000_GPIO1_ST);

	return 0;
}

static int au1000_gpio1_direction_output(struct gpio_chip *chip,
					unsigned offset, int value)
{
	u32 mask = 1 << offset;
	struct au1000_gpio_chip *gpch;

	gpch = container_of(chip, struct au1000_gpio_chip, chip);

	writel(mask, gpch->regbase + AU1000_GPIO1_TRI_OUT);
	au1000_gpio1_set(chip, offset, value);

	return 0;
}

struct au1000_gpio_chip au1000_gpio_chip[] = {
	[0] = {
		.regbase			= (void __iomem *)SYS_BASE,
		.chip = {
			.label			= "au1000-gpio1",
			.direction_input	= au1000_gpio1_direction_input,
			.direction_output	= au1000_gpio1_direction_output,
			.get			= au1000_gpio1_get,
			.set			= au1000_gpio1_set,
			.base			= 0,
			.ngpio			= 32,
		},
	},
#if !defined(CONFIG_SOC_AU1000)
	[1] = {
		.regbase                        = (void __iomem *)GPIO2_BASE,
		.chip = {
			.label                  = "au1000-gpio2",
			.direction_input        = au1000_gpio2_direction_input,
			.direction_output       = au1000_gpio2_direction_output,
			.get                    = au1000_gpio2_get,
			.set                    = au1000_gpio2_set,
			.base                   = AU1XXX_GPIO_BASE,
			.ngpio                  = 32,
		},
	},
#endif
};

static int __init au1000_gpio_init(void)
{
	gpiochip_add(&au1000_gpio_chip[0].chip);
#if !defined(CONFIG_SOC_AU1000)
	gpiochip_add(&au1000_gpio_chip[1].chip);
#endif

	return 0;
}
arch_initcall(au1000_gpio_init);
Commit	Line	Data
2cce8263	1	/*
47c969ee	2	* Copyright (C) 2007-2009, OpenWrt.org, Florian Fainelli <florian@openwrt.org>
4ead1681 FF	3	* Architecture specific GPIO support
4ead1681 FF	4	*
2cce8263 PP	5	* This program is free software; you can redistribute it and/or modify it
	6	* under the terms of the GNU General Public License as published by the
	7	* Free Software Foundation; either version 2 of the License, or (at your
	8	* option) any later version.
	9	*
	10	* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
	11	* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
	12	* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
	13	* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
	14	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
	15	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
	16	* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
	17	* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
	18	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
	19	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	20	*
	21	* You should have received a copy of the GNU General Public License along
	22	* with this program; if not, write to the Free Software Foundation, Inc.,
	23	* 675 Mass Ave, Cambridge, MA 02139, USA.
4ead1681 FF	24	*
	25	* Notes :
	26	* au1000 SoC have only one GPIO line : GPIO1
	27	* others have a second one : GPIO2
2cce8263	28	*/
4ead1681	29
47c969ee	30	#include <linux/kernel.h>
2cce8263	31	#include <linux/module.h>
47c969ee FF	32	#include <linux/types.h>
	33	#include <linux/platform_device.h>
	34	#include <linux/gpio.h>
4ead1681	35
4ead1681 FF	36	#include <asm/mach-au1x00/au1000.h>
4ead1681 FF	37	#include <asm/gpio.h>
2cce8263	38
47c969ee FF	39	struct au1000_gpio_chip {
	40	struct gpio_chip chip;
	41	void __iomem *regbase;
	42	};
2cce8263	43
47c969ee FF	44	#if !defined(CONFIG_SOC_AU1000)
47c969ee FF	45	static int au1000_gpio2_get(struct gpio_chip *chip, unsigned offset)
2cce8263	46	{
47c969ee FF	47	u32 mask = 1 << offset;
	48	struct au1000_gpio_chip *gpch;
	49
	50	gpch = container_of(chip, struct au1000_gpio_chip, chip);
	51	return readl(gpch->regbase + AU1000_GPIO2_ST) & mask;
2cce8263 PP	52	}
2cce8263 PP	53
47c969ee FF	54	static void au1000_gpio2_set(struct gpio_chip *chip,
47c969ee FF	55	unsigned offset, int value)
2cce8263	56	{
47c969ee FF	57	u32 mask = ((GPIO2_OUT_EN_MASK << offset) \| (!!value << offset));
	58	struct au1000_gpio_chip *gpch;
	59	unsigned long flags;
	60
	61	gpch = container_of(chip, struct au1000_gpio_chip, chip);
2cce8263	62
47c969ee FF	63	local_irq_save(flags);
	64	writel(mask, gpch->regbase + AU1000_GPIO2_OUT);
	65	local_irq_restore(flags);
2cce8263 PP	66	}
2cce8263 PP	67
47c969ee	68	static int au1000_gpio2_direction_input(struct gpio_chip *chip, unsigned offset)
2cce8263	69	{
47c969ee FF	70	u32 mask = 1 << offset;
	71	u32 tmp;
	72	struct au1000_gpio_chip *gpch;
	73	unsigned long flags;
	74
	75	gpch = container_of(chip, struct au1000_gpio_chip, chip);
	76
	77	local_irq_save(flags);
	78	tmp = readl(gpch->regbase + AU1000_GPIO2_DIR);
	79	tmp &= ~mask;
	80	writel(tmp, gpch->regbase + AU1000_GPIO2_DIR);
	81	local_irq_restore(flags);
	82
4ead1681	83	return 0;
2cce8263	84	}
2cce8263	85
47c969ee FF	86	static int au1000_gpio2_direction_output(struct gpio_chip *chip,
47c969ee FF	87	unsigned offset, int value)
4ead1681	88	{
47c969ee FF	89	u32 mask = 1 << offset;
	90	u32 out_mask = ((GPIO2_OUT_EN_MASK << offset) \| (!!value << offset));
	91	u32 tmp;
	92	struct au1000_gpio_chip *gpch;
	93	unsigned long flags;
	94
	95	gpch = container_of(chip, struct au1000_gpio_chip, chip);
	96
	97	local_irq_save(flags);
	98	tmp = readl(gpch->regbase + AU1000_GPIO2_DIR);
	99	tmp \|= mask;
	100	writel(tmp, gpch->regbase + AU1000_GPIO2_DIR);
	101	writel(out_mask, gpch->regbase + AU1000_GPIO2_OUT);
	102	local_irq_restore(flags);
	103
4ead1681 FF	104	return 0;
4ead1681 FF	105	}
4ead1681 FF	106	#endif /* !defined(CONFIG_SOC_AU1000) */
4ead1681 FF	107
47c969ee	108	static int au1000_gpio1_get(struct gpio_chip *chip, unsigned offset)
2cce8263	109	{
47c969ee FF	110	u32 mask = 1 << offset;
	111	struct au1000_gpio_chip *gpch;
	112
	113	gpch = container_of(chip, struct au1000_gpio_chip, chip);
	114	return readl(gpch->regbase + AU1000_GPIO1_ST) & mask;
2cce8263 PP	115	}
2cce8263 PP	116
47c969ee FF	117	static void au1000_gpio1_set(struct gpio_chip *chip,
47c969ee FF	118	unsigned offset, int value)
2cce8263	119	{
47c969ee FF	120	u32 mask = 1 << offset;
	121	u32 reg_offset;
	122	struct au1000_gpio_chip *gpch;
	123	unsigned long flags;
	124
	125	gpch = container_of(chip, struct au1000_gpio_chip, chip);
	126
4ead1681	127	if (value)
47c969ee	128	reg_offset = AU1000_GPIO1_OUT;
2cce8263	129	else
47c969ee	130	reg_offset = AU1000_GPIO1_CLR;
2cce8263	131
47c969ee FF	132	local_irq_save(flags);
	133	writel(mask, gpch->regbase + reg_offset);
	134	local_irq_restore(flags);
2cce8263 PP	135	}
2cce8263 PP	136
47c969ee	137	static int au1000_gpio1_direction_input(struct gpio_chip *chip, unsigned offset)
4ead1681	138	{
47c969ee FF	139	u32 mask = 1 << offset;
	140	struct au1000_gpio_chip *gpch;
	141
	142	gpch = container_of(chip, struct au1000_gpio_chip, chip);
	143	writel(mask, gpch->regbase + AU1000_GPIO1_ST);
	144
4ead1681 FF	145	return 0;
4ead1681 FF	146	}
2cce8263	147
47c969ee FF	148	static int au1000_gpio1_direction_output(struct gpio_chip *chip,
47c969ee FF	149	unsigned offset, int value)
2cce8263	150	{
47c969ee FF	151	u32 mask = 1 << offset;
47c969ee FF	152	struct au1000_gpio_chip *gpch;
4ead1681	153
47c969ee	154	gpch = container_of(chip, struct au1000_gpio_chip, chip);
4ead1681	155
47c969ee FF	156	writel(mask, gpch->regbase + AU1000_GPIO1_TRI_OUT);
47c969ee FF	157	au1000_gpio1_set(chip, offset, value);
7acae224	158
47c969ee	159	return 0;
2cce8263	160	}
4ead1681	161
47c969ee FF	162	struct au1000_gpio_chip au1000_gpio_chip[] = {
	163	[0] = {
	164	.regbase = (void __iomem *)SYS_BASE,
	165	.chip = {
	166	.label = "au1000-gpio1",
	167	.direction_input = au1000_gpio1_direction_input,
	168	.direction_output = au1000_gpio1_direction_output,
	169	.get = au1000_gpio1_get,
	170	.set = au1000_gpio1_set,
	171	.base = 0,
	172	.ngpio = 32,
	173	},
	174	},
	175	#if !defined(CONFIG_SOC_AU1000)
	176	[1] = {
	177	.regbase = (void __iomem *)GPIO2_BASE,
	178	.chip = {
	179	.label = "au1000-gpio2",
	180	.direction_input = au1000_gpio2_direction_input,
	181	.direction_output = au1000_gpio2_direction_output,
	182	.get = au1000_gpio2_get,
	183	.set = au1000_gpio2_set,
	184	.base = AU1XXX_GPIO_BASE,
	185	.ngpio = 32,
	186	},
	187	},
	188	#endif
	189	};
	190
	191	static int __init au1000_gpio_init(void)
2cce8263	192	{
47c969ee FF	193	gpiochip_add(&au1000_gpio_chip[0].chip);
	194	#if !defined(CONFIG_SOC_AU1000)
	195	gpiochip_add(&au1000_gpio_chip[1].chip);
4ead1681	196	#endif
7acae224	197
47c969ee	198	return 0;
2cce8263	199	}
47c969ee FF	200	arch_initcall(au1000_gpio_init);
47c969ee FF	201