[mirror_ubuntu-artful-kernel.git] / arch / mips / alchemy / devboards / bcsr.c

/*
 * bcsr.h -- Db1xxx/Pb1xxx Devboard CPLD registers ("BCSR") abstraction.
 *
 * All Alchemy development boards (except, of course, the weird PB1000)
 * have a few registers in a CPLD with standardised layout; they mostly
 * only differ in base address.
 * All registers are 16bits wide with 32bit spacing.
 */

#include <linux/interrupt.h>
#include <linux/irqchip/chained_irq.h>
#include <linux/init.h>
#include <linux/export.h>
#include <linux/spinlock.h>
#include <linux/irq.h>
#include <asm/addrspace.h>
#include <asm/io.h>
#include <asm/mach-db1x00/bcsr.h>

static struct bcsr_reg {
	void __iomem *raddr;
	spinlock_t lock;
} bcsr_regs[BCSR_CNT];

static void __iomem *bcsr_virt; /* KSEG1 addr of BCSR base */
static int bcsr_csc_base;	/* linux-irq of first cascaded irq */

void __init bcsr_init(unsigned long bcsr1_phys, unsigned long bcsr2_phys)
{
	int i;

	bcsr1_phys = KSEG1ADDR(CPHYSADDR(bcsr1_phys));
	bcsr2_phys = KSEG1ADDR(CPHYSADDR(bcsr2_phys));

	bcsr_virt = (void __iomem *)bcsr1_phys;

	for (i = 0; i < BCSR_CNT; i++) {
		if (i >= BCSR_HEXLEDS)
			bcsr_regs[i].raddr = (void __iomem *)bcsr2_phys +
					(0x04 * (i - BCSR_HEXLEDS));
		else
			bcsr_regs[i].raddr = (void __iomem *)bcsr1_phys +
					(0x04 * i);

		spin_lock_init(&bcsr_regs[i].lock);
	}
}

unsigned short bcsr_read(enum bcsr_id reg)
{
	unsigned short r;
	unsigned long flags;

	spin_lock_irqsave(&bcsr_regs[reg].lock, flags);
	r = __raw_readw(bcsr_regs[reg].raddr);
	spin_unlock_irqrestore(&bcsr_regs[reg].lock, flags);
	return r;
}
EXPORT_SYMBOL_GPL(bcsr_read);

void bcsr_write(enum bcsr_id reg, unsigned short val)
{
	unsigned long flags;

	spin_lock_irqsave(&bcsr_regs[reg].lock, flags);
	__raw_writew(val, bcsr_regs[reg].raddr);
	wmb();
	spin_unlock_irqrestore(&bcsr_regs[reg].lock, flags);
}
EXPORT_SYMBOL_GPL(bcsr_write);

void bcsr_mod(enum bcsr_id reg, unsigned short clr, unsigned short set)
{
	unsigned short r;
	unsigned long flags;

	spin_lock_irqsave(&bcsr_regs[reg].lock, flags);
	r = __raw_readw(bcsr_regs[reg].raddr);
	r &= ~clr;
	r |= set;
	__raw_writew(r, bcsr_regs[reg].raddr);
	wmb();
	spin_unlock_irqrestore(&bcsr_regs[reg].lock, flags);
}
EXPORT_SYMBOL_GPL(bcsr_mod);

/*
 * DB1200/PB1200 CPLD IRQ muxer
 */
static void bcsr_csc_handler(struct irq_desc *d)
{
	unsigned short bisr = __raw_readw(bcsr_virt + BCSR_REG_INTSTAT);
	struct irq_chip *chip = irq_desc_get_chip(d);

	chained_irq_enter(chip, d);
	generic_handle_irq(bcsr_csc_base + __ffs(bisr));
	chained_irq_exit(chip, d);
}

static void bcsr_irq_mask(struct irq_data *d)
{
	unsigned short v = 1 << (d->irq - bcsr_csc_base);
	__raw_writew(v, bcsr_virt + BCSR_REG_MASKCLR);
	wmb();
}

static void bcsr_irq_maskack(struct irq_data *d)
{
	unsigned short v = 1 << (d->irq - bcsr_csc_base);
	__raw_writew(v, bcsr_virt + BCSR_REG_MASKCLR);
	__raw_writew(v, bcsr_virt + BCSR_REG_INTSTAT);	/* ack */
	wmb();
}

static void bcsr_irq_unmask(struct irq_data *d)
{
	unsigned short v = 1 << (d->irq - bcsr_csc_base);
	__raw_writew(v, bcsr_virt + BCSR_REG_MASKSET);
	wmb();
}

static struct irq_chip bcsr_irq_type = {
	.name		= "CPLD",
	.irq_mask	= bcsr_irq_mask,
	.irq_mask_ack	= bcsr_irq_maskack,
	.irq_unmask	= bcsr_irq_unmask,
};

void __init bcsr_init_irq(int csc_start, int csc_end, int hook_irq)
{
	unsigned int irq;

	/* mask & enable & ack all */
	__raw_writew(0xffff, bcsr_virt + BCSR_REG_MASKCLR);
	__raw_writew(0xffff, bcsr_virt + BCSR_REG_INTSET);
	__raw_writew(0xffff, bcsr_virt + BCSR_REG_INTSTAT);
	wmb();

	bcsr_csc_base = csc_start;

	for (irq = csc_start; irq <= csc_end; irq++)
		irq_set_chip_and_handler_name(irq, &bcsr_irq_type,
					      handle_level_irq, "level");

	irq_set_chained_handler(hook_irq, bcsr_csc_handler);
}
Commit	Line	Data
9bdcf336 ML	1	/*
	2	* bcsr.h -- Db1xxx/Pb1xxx Devboard CPLD registers ("BCSR") abstraction.
	3	*
	4	* All Alchemy development boards (except, of course, the weird PB1000)
	5	* have a few registers in a CPLD with standardised layout; they mostly
	6	* only differ in base address.
	7	* All registers are 16bits wide with 32bit spacing.
	8	*/
	9
95a43796	10	#include <linux/interrupt.h>
e0288a0a	11	#include <linux/irqchip/chained_irq.h>
26dd3e4f PG	12	#include <linux/init.h>
26dd3e4f PG	13	#include <linux/export.h>
9bdcf336	14	#include <linux/spinlock.h>
ca4d3e67	15	#include <linux/irq.h>
9bdcf336 ML	16	#include <asm/addrspace.h>
	17	#include <asm/io.h>
	18	#include <asm/mach-db1x00/bcsr.h>
	19
	20	static struct bcsr_reg {
	21	void __iomem *raddr;
	22	spinlock_t lock;
	23	} bcsr_regs[BCSR_CNT];
	24
70342287	25	static void __iomem bcsr_virt; / KSEG1 addr of BCSR base */
95a43796 ML	26	static int bcsr_csc_base; /* linux-irq of first cascaded irq */
95a43796 ML	27
9bdcf336 ML	28	void __init bcsr_init(unsigned long bcsr1_phys, unsigned long bcsr2_phys)
	29	{
	30	int i;
	31
	32	bcsr1_phys = KSEG1ADDR(CPHYSADDR(bcsr1_phys));
	33	bcsr2_phys = KSEG1ADDR(CPHYSADDR(bcsr2_phys));
	34
95a43796 ML	35	bcsr_virt = (void __iomem *)bcsr1_phys;
95a43796 ML	36
9bdcf336 ML	37	for (i = 0; i < BCSR_CNT; i++) {
	38	if (i >= BCSR_HEXLEDS)
	39	bcsr_regs[i].raddr = (void __iomem *)bcsr2_phys +
	40	(0x04 * (i - BCSR_HEXLEDS));
	41	else
	42	bcsr_regs[i].raddr = (void __iomem *)bcsr1_phys +
	43	(0x04 * i);
	44
	45	spin_lock_init(&bcsr_regs[i].lock);
	46	}
	47	}
	48
	49	unsigned short bcsr_read(enum bcsr_id reg)
	50	{
	51	unsigned short r;
	52	unsigned long flags;
	53
	54	spin_lock_irqsave(&bcsr_regs[reg].lock, flags);
	55	r = __raw_readw(bcsr_regs[reg].raddr);
	56	spin_unlock_irqrestore(&bcsr_regs[reg].lock, flags);
	57	return r;
	58	}
	59	EXPORT_SYMBOL_GPL(bcsr_read);
	60
	61	void bcsr_write(enum bcsr_id reg, unsigned short val)
	62	{
	63	unsigned long flags;
	64
	65	spin_lock_irqsave(&bcsr_regs[reg].lock, flags);
	66	__raw_writew(val, bcsr_regs[reg].raddr);
	67	wmb();
	68	spin_unlock_irqrestore(&bcsr_regs[reg].lock, flags);
	69	}
	70	EXPORT_SYMBOL_GPL(bcsr_write);
	71
	72	void bcsr_mod(enum bcsr_id reg, unsigned short clr, unsigned short set)
	73	{
	74	unsigned short r;
	75	unsigned long flags;
	76
	77	spin_lock_irqsave(&bcsr_regs[reg].lock, flags);
	78	r = __raw_readw(bcsr_regs[reg].raddr);
	79	r &= ~clr;
	80	r \|= set;
	81	__raw_writew(r, bcsr_regs[reg].raddr);
	82	wmb();
	83	spin_unlock_irqrestore(&bcsr_regs[reg].lock, flags);
	84	}
	85	EXPORT_SYMBOL_GPL(bcsr_mod);
95a43796 ML	86
	87	/*
	88	* DB1200/PB1200 CPLD IRQ muxer
	89	*/
bd0b9ac4	90	static void bcsr_csc_handler(struct irq_desc *d)
95a43796 ML	91	{
95a43796 ML	92	unsigned short bisr = __raw_readw(bcsr_virt + BCSR_REG_INTSTAT);
e0288a0a	93	struct irq_chip *chip = irq_desc_get_chip(d);
95a43796	94
e0288a0a	95	chained_irq_enter(chip, d);
6c2be5cf	96	generic_handle_irq(bcsr_csc_base + __ffs(bisr));
e0288a0a	97	chained_irq_exit(chip, d);
95a43796 ML	98	}
95a43796 ML	99
d24c1a26	100	static void bcsr_irq_mask(struct irq_data *d)
95a43796	101	{
d24c1a26	102	unsigned short v = 1 << (d->irq - bcsr_csc_base);
95a43796 ML	103	__raw_writew(v, bcsr_virt + BCSR_REG_MASKCLR);
	104	wmb();
	105	}
	106
d24c1a26	107	static void bcsr_irq_maskack(struct irq_data *d)
95a43796	108	{
d24c1a26	109	unsigned short v = 1 << (d->irq - bcsr_csc_base);
95a43796 ML	110	__raw_writew(v, bcsr_virt + BCSR_REG_MASKCLR);
	111	__raw_writew(v, bcsr_virt + BCSR_REG_INTSTAT); /* ack */
	112	wmb();
	113	}
	114
d24c1a26	115	static void bcsr_irq_unmask(struct irq_data *d)
95a43796	116	{
d24c1a26	117	unsigned short v = 1 << (d->irq - bcsr_csc_base);
95a43796 ML	118	__raw_writew(v, bcsr_virt + BCSR_REG_MASKSET);
	119	wmb();
	120	}
	121
	122	static struct irq_chip bcsr_irq_type = {
	123	.name = "CPLD",
d24c1a26 TG	124	.irq_mask = bcsr_irq_mask,
	125	.irq_mask_ack = bcsr_irq_maskack,
	126	.irq_unmask = bcsr_irq_unmask,
95a43796 ML	127	};
	128
	129	void __init bcsr_init_irq(int csc_start, int csc_end, int hook_irq)
	130	{
	131	unsigned int irq;
	132
fb469f08	133	/* mask & enable & ack all */
95a43796	134	__raw_writew(0xffff, bcsr_virt + BCSR_REG_MASKCLR);
fb469f08	135	__raw_writew(0xffff, bcsr_virt + BCSR_REG_INTSET);
95a43796 ML	136	__raw_writew(0xffff, bcsr_virt + BCSR_REG_INTSTAT);
	137	wmb();
	138
	139	bcsr_csc_base = csc_start;
	140
	141	for (irq = csc_start; irq <= csc_end; irq++)
e4ec7989 TG	142	irq_set_chip_and_handler_name(irq, &bcsr_irq_type,
e4ec7989 TG	143	handle_level_irq, "level");
95a43796	144
e4ec7989	145	irq_set_chained_handler(hook_irq, bcsr_csc_handler);
95a43796	146	}