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Commit | Line | Data |
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f869d42e | 1 | /* |
24e8c1a6 | 2 | * Alchemy Db1550/Pb1550 board support |
f869d42e ML |
3 | * |
4 | * (c) 2011 Manuel Lauss <manuel.lauss@googlemail.com> | |
5 | */ | |
6 | ||
415e0fec | 7 | #include <linux/clk.h> |
f869d42e ML |
8 | #include <linux/dma-mapping.h> |
9 | #include <linux/gpio.h> | |
10 | #include <linux/i2c.h> | |
11 | #include <linux/init.h> | |
12 | #include <linux/io.h> | |
13 | #include <linux/interrupt.h> | |
14 | #include <linux/mtd/mtd.h> | |
15 | #include <linux/mtd/nand.h> | |
16 | #include <linux/mtd/partitions.h> | |
17 | #include <linux/platform_device.h> | |
18 | #include <linux/pm.h> | |
19 | #include <linux/spi/spi.h> | |
20 | #include <linux/spi/flash.h> | |
24e8c1a6 | 21 | #include <asm/bootinfo.h> |
f869d42e | 22 | #include <asm/mach-au1x00/au1000.h> |
832f5dac | 23 | #include <asm/mach-au1x00/gpio-au1000.h> |
f869d42e ML |
24 | #include <asm/mach-au1x00/au1xxx_eth.h> |
25 | #include <asm/mach-au1x00/au1xxx_dbdma.h> | |
26 | #include <asm/mach-au1x00/au1xxx_psc.h> | |
27 | #include <asm/mach-au1x00/au1550_spi.h> | |
24e8c1a6 | 28 | #include <asm/mach-au1x00/au1550nd.h> |
f869d42e ML |
29 | #include <asm/mach-db1x00/bcsr.h> |
30 | #include <prom.h> | |
31 | #include "platform.h" | |
32 | ||
f869d42e ML |
33 | static void __init db1550_hw_setup(void) |
34 | { | |
35 | void __iomem *base; | |
1d09de7d | 36 | unsigned long v; |
f869d42e | 37 | |
c02a505e ML |
38 | /* complete pin setup: assign GPIO16 to PSC0_SYNC1 (SPI cs# line) |
39 | * as well as PSC1_SYNC for AC97 on PB1550. | |
f869d42e | 40 | */ |
1d09de7d ML |
41 | v = alchemy_rdsys(AU1000_SYS_PINFUNC); |
42 | alchemy_wrsys(v | 1 | SYS_PF_PSC1_S1, AU1000_SYS_PINFUNC); | |
f869d42e ML |
43 | |
44 | /* reset the AC97 codec now, the reset time in the psc-ac97 driver | |
45 | * is apparently too short although it's ridiculous as it is. | |
46 | */ | |
47 | base = (void __iomem *)KSEG1ADDR(AU1550_PSC1_PHYS_ADDR); | |
48 | __raw_writel(PSC_SEL_CLK_SERCLK | PSC_SEL_PS_AC97MODE, | |
49 | base + PSC_SEL_OFFSET); | |
50 | __raw_writel(PSC_CTRL_DISABLE, base + PSC_CTRL_OFFSET); | |
51 | wmb(); | |
52 | __raw_writel(PSC_AC97RST_RST, base + PSC_AC97RST_OFFSET); | |
53 | wmb(); | |
f869d42e ML |
54 | } |
55 | ||
bd8510df | 56 | int __init db1550_board_setup(void) |
f869d42e ML |
57 | { |
58 | unsigned short whoami; | |
59 | ||
60 | bcsr_init(DB1550_BCSR_PHYS_ADDR, | |
61 | DB1550_BCSR_PHYS_ADDR + DB1550_BCSR_HEXLED_OFS); | |
62 | ||
24e8c1a6 | 63 | whoami = bcsr_read(BCSR_WHOAMI); /* PB1550 hexled offset differs */ |
970e268d ML |
64 | switch (BCSR_WHOAMI_BOARD(whoami)) { |
65 | case BCSR_WHOAMI_PB1550_SDR: | |
66 | case BCSR_WHOAMI_PB1550_DDR: | |
24e8c1a6 ML |
67 | bcsr_init(PB1550_BCSR_PHYS_ADDR, |
68 | PB1550_BCSR_PHYS_ADDR + PB1550_BCSR_HEXLED_OFS); | |
970e268d ML |
69 | case BCSR_WHOAMI_DB1550: |
70 | break; | |
71 | default: | |
72 | return -ENODEV; | |
73 | } | |
24e8c1a6 | 74 | |
70342287 | 75 | pr_info("Alchemy/AMD %s Board, CPLD Rev %d Board-ID %d " \ |
24e8c1a6 | 76 | "Daughtercard ID %d\n", get_system_type(), |
f869d42e ML |
77 | (whoami >> 4) & 0xf, (whoami >> 8) & 0xf, whoami & 0xf); |
78 | ||
79 | db1550_hw_setup(); | |
bd8510df | 80 | return 0; |
f869d42e ML |
81 | } |
82 | ||
83 | /*****************************************************************************/ | |
84 | ||
85 | static struct mtd_partition db1550_spiflash_parts[] = { | |
86 | { | |
87 | .name = "spi_flash", | |
70342287 | 88 | .offset = 0, |
f869d42e ML |
89 | .size = MTDPART_SIZ_FULL, |
90 | }, | |
91 | }; | |
92 | ||
93 | static struct flash_platform_data db1550_spiflash_data = { | |
94 | .name = "s25fl010", | |
95 | .parts = db1550_spiflash_parts, | |
96 | .nr_parts = ARRAY_SIZE(db1550_spiflash_parts), | |
97 | .type = "m25p10", | |
98 | }; | |
99 | ||
100 | static struct spi_board_info db1550_spi_devs[] __initdata = { | |
101 | { | |
102 | /* TI TMP121AIDBVR temp sensor */ | |
103 | .modalias = "tmp121", | |
104 | .max_speed_hz = 2400000, | |
105 | .bus_num = 0, | |
106 | .chip_select = 0, | |
107 | .mode = SPI_MODE_0, | |
108 | }, | |
109 | { | |
110 | /* Spansion S25FL001D0FMA SPI flash */ | |
111 | .modalias = "m25p80", | |
112 | .max_speed_hz = 2400000, | |
113 | .bus_num = 0, | |
114 | .chip_select = 1, | |
115 | .mode = SPI_MODE_0, | |
116 | .platform_data = &db1550_spiflash_data, | |
117 | }, | |
118 | }; | |
119 | ||
120 | static struct i2c_board_info db1550_i2c_devs[] __initdata = { | |
121 | { I2C_BOARD_INFO("24c04", 0x52),}, /* AT24C04-10 I2C eeprom */ | |
122 | { I2C_BOARD_INFO("ne1619", 0x2d),}, /* adm1025-compat hwmon */ | |
123 | { I2C_BOARD_INFO("wm8731", 0x1b),}, /* I2S audio codec WM8731 */ | |
124 | }; | |
125 | ||
126 | /**********************************************************************/ | |
127 | ||
128 | static void au1550_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, | |
129 | unsigned int ctrl) | |
130 | { | |
b1afda0e | 131 | struct nand_chip *this = mtd_to_nand(mtd); |
f869d42e ML |
132 | unsigned long ioaddr = (unsigned long)this->IO_ADDR_W; |
133 | ||
134 | ioaddr &= 0xffffff00; | |
135 | ||
136 | if (ctrl & NAND_CLE) { | |
137 | ioaddr += MEM_STNAND_CMD; | |
138 | } else if (ctrl & NAND_ALE) { | |
139 | ioaddr += MEM_STNAND_ADDR; | |
140 | } else { | |
141 | /* assume we want to r/w real data by default */ | |
142 | ioaddr += MEM_STNAND_DATA; | |
143 | } | |
144 | this->IO_ADDR_R = this->IO_ADDR_W = (void __iomem *)ioaddr; | |
145 | if (cmd != NAND_CMD_NONE) { | |
146 | __raw_writeb(cmd, this->IO_ADDR_W); | |
147 | wmb(); | |
148 | } | |
149 | } | |
150 | ||
151 | static int au1550_nand_device_ready(struct mtd_info *mtd) | |
152 | { | |
9cf12167 | 153 | return alchemy_rdsmem(AU1000_MEM_STSTAT) & 1; |
f869d42e ML |
154 | } |
155 | ||
f869d42e ML |
156 | static struct mtd_partition db1550_nand_parts[] = { |
157 | { | |
158 | .name = "NAND FS 0", | |
70342287 | 159 | .offset = 0, |
f869d42e ML |
160 | .size = 8 * 1024 * 1024, |
161 | }, | |
162 | { | |
163 | .name = "NAND FS 1", | |
70342287 | 164 | .offset = MTDPART_OFS_APPEND, |
f869d42e ML |
165 | .size = MTDPART_SIZ_FULL |
166 | }, | |
167 | }; | |
168 | ||
169 | struct platform_nand_data db1550_nand_platdata = { | |
170 | .chip = { | |
171 | .nr_chips = 1, | |
172 | .chip_offset = 0, | |
173 | .nr_partitions = ARRAY_SIZE(db1550_nand_parts), | |
174 | .partitions = db1550_nand_parts, | |
175 | .chip_delay = 20, | |
f869d42e ML |
176 | }, |
177 | .ctrl = { | |
178 | .dev_ready = au1550_nand_device_ready, | |
179 | .cmd_ctrl = au1550_nand_cmd_ctrl, | |
180 | }, | |
181 | }; | |
182 | ||
183 | static struct resource db1550_nand_res[] = { | |
184 | [0] = { | |
185 | .start = 0x20000000, | |
186 | .end = 0x200000ff, | |
187 | .flags = IORESOURCE_MEM, | |
188 | }, | |
189 | }; | |
190 | ||
191 | static struct platform_device db1550_nand_dev = { | |
192 | .name = "gen_nand", | |
193 | .num_resources = ARRAY_SIZE(db1550_nand_res), | |
194 | .resource = db1550_nand_res, | |
195 | .id = -1, | |
196 | .dev = { | |
197 | .platform_data = &db1550_nand_platdata, | |
198 | } | |
199 | }; | |
200 | ||
24e8c1a6 ML |
201 | static struct au1550nd_platdata pb1550_nand_pd = { |
202 | .parts = db1550_nand_parts, | |
203 | .num_parts = ARRAY_SIZE(db1550_nand_parts), | |
204 | .devwidth = 0, /* x8 NAND default, needs fixing up */ | |
205 | }; | |
206 | ||
207 | static struct platform_device pb1550_nand_dev = { | |
208 | .name = "au1550-nand", | |
209 | .id = -1, | |
210 | .resource = db1550_nand_res, | |
211 | .num_resources = ARRAY_SIZE(db1550_nand_res), | |
212 | .dev = { | |
213 | .platform_data = &pb1550_nand_pd, | |
214 | }, | |
215 | }; | |
216 | ||
217 | static void __init pb1550_nand_setup(void) | |
218 | { | |
9cf12167 | 219 | int boot_swapboot = (alchemy_rdsmem(AU1000_MEM_STSTAT) & (0x7 << 1)) | |
24e8c1a6 ML |
220 | ((bcsr_read(BCSR_STATUS) >> 6) & 0x1); |
221 | ||
222 | gpio_direction_input(206); /* de-assert NAND CS# */ | |
223 | switch (boot_swapboot) { | |
224 | case 0: case 2: case 8: case 0xC: case 0xD: | |
225 | /* x16 NAND Flash */ | |
226 | pb1550_nand_pd.devwidth = 1; | |
227 | /* fallthrough */ | |
228 | case 1: case 3: case 9: case 0xE: case 0xF: | |
229 | /* x8 NAND, already set up */ | |
230 | platform_device_register(&pb1550_nand_dev); | |
231 | } | |
232 | } | |
233 | ||
f869d42e ML |
234 | /**********************************************************************/ |
235 | ||
236 | static struct resource au1550_psc0_res[] = { | |
237 | [0] = { | |
238 | .start = AU1550_PSC0_PHYS_ADDR, | |
239 | .end = AU1550_PSC0_PHYS_ADDR + 0xfff, | |
240 | .flags = IORESOURCE_MEM, | |
241 | }, | |
242 | [1] = { | |
243 | .start = AU1550_PSC0_INT, | |
244 | .end = AU1550_PSC0_INT, | |
245 | .flags = IORESOURCE_IRQ, | |
246 | }, | |
247 | [2] = { | |
248 | .start = AU1550_DSCR_CMD0_PSC0_TX, | |
249 | .end = AU1550_DSCR_CMD0_PSC0_TX, | |
250 | .flags = IORESOURCE_DMA, | |
251 | }, | |
252 | [3] = { | |
253 | .start = AU1550_DSCR_CMD0_PSC0_RX, | |
254 | .end = AU1550_DSCR_CMD0_PSC0_RX, | |
255 | .flags = IORESOURCE_DMA, | |
256 | }, | |
257 | }; | |
258 | ||
259 | static void db1550_spi_cs_en(struct au1550_spi_info *spi, int cs, int pol) | |
260 | { | |
261 | if (cs) | |
262 | bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_SPISEL); | |
263 | else | |
264 | bcsr_mod(BCSR_BOARD, BCSR_BOARD_SPISEL, 0); | |
265 | } | |
266 | ||
267 | static struct au1550_spi_info db1550_spi_platdata = { | |
268 | .mainclk_hz = 48000000, /* PSC0 clock: max. 2.4MHz SPI clk */ | |
269 | .num_chipselect = 2, | |
270 | .activate_cs = db1550_spi_cs_en, | |
271 | }; | |
272 | ||
273 | static u64 spi_dmamask = DMA_BIT_MASK(32); | |
274 | ||
275 | static struct platform_device db1550_spi_dev = { | |
276 | .dev = { | |
277 | .dma_mask = &spi_dmamask, | |
278 | .coherent_dma_mask = DMA_BIT_MASK(32), | |
279 | .platform_data = &db1550_spi_platdata, | |
280 | }, | |
281 | .name = "au1550-spi", | |
282 | .id = 0, /* bus number */ | |
283 | .num_resources = ARRAY_SIZE(au1550_psc0_res), | |
284 | .resource = au1550_psc0_res, | |
285 | }; | |
286 | ||
287 | /**********************************************************************/ | |
288 | ||
289 | static struct resource au1550_psc1_res[] = { | |
290 | [0] = { | |
291 | .start = AU1550_PSC1_PHYS_ADDR, | |
292 | .end = AU1550_PSC1_PHYS_ADDR + 0xfff, | |
293 | .flags = IORESOURCE_MEM, | |
294 | }, | |
295 | [1] = { | |
296 | .start = AU1550_PSC1_INT, | |
297 | .end = AU1550_PSC1_INT, | |
298 | .flags = IORESOURCE_IRQ, | |
299 | }, | |
300 | [2] = { | |
301 | .start = AU1550_DSCR_CMD0_PSC1_TX, | |
302 | .end = AU1550_DSCR_CMD0_PSC1_TX, | |
303 | .flags = IORESOURCE_DMA, | |
304 | }, | |
305 | [3] = { | |
306 | .start = AU1550_DSCR_CMD0_PSC1_RX, | |
307 | .end = AU1550_DSCR_CMD0_PSC1_RX, | |
308 | .flags = IORESOURCE_DMA, | |
309 | }, | |
310 | }; | |
311 | ||
312 | static struct platform_device db1550_ac97_dev = { | |
313 | .name = "au1xpsc_ac97", | |
314 | .id = 1, /* PSC ID */ | |
315 | .num_resources = ARRAY_SIZE(au1550_psc1_res), | |
316 | .resource = au1550_psc1_res, | |
317 | }; | |
318 | ||
319 | ||
320 | static struct resource au1550_psc2_res[] = { | |
321 | [0] = { | |
322 | .start = AU1550_PSC2_PHYS_ADDR, | |
323 | .end = AU1550_PSC2_PHYS_ADDR + 0xfff, | |
324 | .flags = IORESOURCE_MEM, | |
325 | }, | |
326 | [1] = { | |
327 | .start = AU1550_PSC2_INT, | |
328 | .end = AU1550_PSC2_INT, | |
329 | .flags = IORESOURCE_IRQ, | |
330 | }, | |
331 | [2] = { | |
332 | .start = AU1550_DSCR_CMD0_PSC2_TX, | |
333 | .end = AU1550_DSCR_CMD0_PSC2_TX, | |
334 | .flags = IORESOURCE_DMA, | |
335 | }, | |
336 | [3] = { | |
337 | .start = AU1550_DSCR_CMD0_PSC2_RX, | |
338 | .end = AU1550_DSCR_CMD0_PSC2_RX, | |
339 | .flags = IORESOURCE_DMA, | |
340 | }, | |
341 | }; | |
342 | ||
343 | static struct platform_device db1550_i2c_dev = { | |
344 | .name = "au1xpsc_smbus", | |
345 | .id = 0, /* bus number */ | |
346 | .num_resources = ARRAY_SIZE(au1550_psc2_res), | |
347 | .resource = au1550_psc2_res, | |
348 | }; | |
349 | ||
350 | /**********************************************************************/ | |
351 | ||
352 | static struct resource au1550_psc3_res[] = { | |
353 | [0] = { | |
354 | .start = AU1550_PSC3_PHYS_ADDR, | |
355 | .end = AU1550_PSC3_PHYS_ADDR + 0xfff, | |
356 | .flags = IORESOURCE_MEM, | |
357 | }, | |
358 | [1] = { | |
359 | .start = AU1550_PSC3_INT, | |
360 | .end = AU1550_PSC3_INT, | |
361 | .flags = IORESOURCE_IRQ, | |
362 | }, | |
363 | [2] = { | |
364 | .start = AU1550_DSCR_CMD0_PSC3_TX, | |
365 | .end = AU1550_DSCR_CMD0_PSC3_TX, | |
366 | .flags = IORESOURCE_DMA, | |
367 | }, | |
368 | [3] = { | |
369 | .start = AU1550_DSCR_CMD0_PSC3_RX, | |
370 | .end = AU1550_DSCR_CMD0_PSC3_RX, | |
371 | .flags = IORESOURCE_DMA, | |
372 | }, | |
373 | }; | |
374 | ||
375 | static struct platform_device db1550_i2s_dev = { | |
376 | .name = "au1xpsc_i2s", | |
377 | .id = 3, /* PSC ID */ | |
378 | .num_resources = ARRAY_SIZE(au1550_psc3_res), | |
379 | .resource = au1550_psc3_res, | |
380 | }; | |
381 | ||
382 | /**********************************************************************/ | |
383 | ||
384 | static struct platform_device db1550_stac_dev = { | |
385 | .name = "ac97-codec", | |
386 | .id = 1, /* on PSC1 */ | |
387 | }; | |
388 | ||
389 | static struct platform_device db1550_ac97dma_dev = { | |
390 | .name = "au1xpsc-pcm", | |
391 | .id = 1, /* on PSC3 */ | |
392 | }; | |
393 | ||
394 | static struct platform_device db1550_i2sdma_dev = { | |
395 | .name = "au1xpsc-pcm", | |
396 | .id = 3, /* on PSC3 */ | |
397 | }; | |
398 | ||
399 | static struct platform_device db1550_sndac97_dev = { | |
400 | .name = "db1550-ac97", | |
401 | }; | |
402 | ||
403 | static struct platform_device db1550_sndi2s_dev = { | |
404 | .name = "db1550-i2s", | |
405 | }; | |
406 | ||
407 | /**********************************************************************/ | |
408 | ||
f869d42e ML |
409 | static int db1550_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin) |
410 | { | |
411 | if ((slot < 11) || (slot > 13) || pin == 0) | |
412 | return -1; | |
413 | if (slot == 11) | |
414 | return (pin == 1) ? AU1550_PCI_INTC : 0xff; | |
415 | if (slot == 12) { | |
416 | switch (pin) { | |
417 | case 1: return AU1550_PCI_INTB; | |
418 | case 2: return AU1550_PCI_INTC; | |
419 | case 3: return AU1550_PCI_INTD; | |
420 | case 4: return AU1550_PCI_INTA; | |
421 | } | |
422 | } | |
423 | if (slot == 13) { | |
424 | switch (pin) { | |
425 | case 1: return AU1550_PCI_INTA; | |
426 | case 2: return AU1550_PCI_INTB; | |
427 | case 3: return AU1550_PCI_INTC; | |
428 | case 4: return AU1550_PCI_INTD; | |
429 | } | |
430 | } | |
431 | return -1; | |
432 | } | |
433 | ||
24e8c1a6 ML |
434 | static int pb1550_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin) |
435 | { | |
436 | if ((slot < 12) || (slot > 13) || pin == 0) | |
437 | return -1; | |
438 | if (slot == 12) { | |
439 | switch (pin) { | |
440 | case 1: return AU1500_PCI_INTB; | |
441 | case 2: return AU1500_PCI_INTC; | |
442 | case 3: return AU1500_PCI_INTD; | |
443 | case 4: return AU1500_PCI_INTA; | |
444 | } | |
445 | } | |
446 | if (slot == 13) { | |
447 | switch (pin) { | |
448 | case 1: return AU1500_PCI_INTA; | |
449 | case 2: return AU1500_PCI_INTB; | |
450 | case 3: return AU1500_PCI_INTC; | |
451 | case 4: return AU1500_PCI_INTD; | |
452 | } | |
453 | } | |
454 | return -1; | |
455 | } | |
456 | ||
f869d42e ML |
457 | static struct resource alchemy_pci_host_res[] = { |
458 | [0] = { | |
459 | .start = AU1500_PCI_PHYS_ADDR, | |
460 | .end = AU1500_PCI_PHYS_ADDR + 0xfff, | |
461 | .flags = IORESOURCE_MEM, | |
462 | }, | |
463 | }; | |
464 | ||
465 | static struct alchemy_pci_platdata db1550_pci_pd = { | |
466 | .board_map_irq = db1550_map_pci_irq, | |
467 | }; | |
468 | ||
469 | static struct platform_device db1550_pci_host_dev = { | |
470 | .dev.platform_data = &db1550_pci_pd, | |
471 | .name = "alchemy-pci", | |
472 | .id = 0, | |
473 | .num_resources = ARRAY_SIZE(alchemy_pci_host_res), | |
474 | .resource = alchemy_pci_host_res, | |
475 | }; | |
476 | ||
477 | /**********************************************************************/ | |
478 | ||
479 | static struct platform_device *db1550_devs[] __initdata = { | |
f869d42e ML |
480 | &db1550_i2c_dev, |
481 | &db1550_ac97_dev, | |
482 | &db1550_spi_dev, | |
483 | &db1550_i2s_dev, | |
484 | &db1550_stac_dev, | |
485 | &db1550_ac97dma_dev, | |
486 | &db1550_i2sdma_dev, | |
487 | &db1550_sndac97_dev, | |
488 | &db1550_sndi2s_dev, | |
489 | }; | |
490 | ||
491 | /* must be arch_initcall; MIPS PCI scans busses in a subsys_initcall */ | |
24e8c1a6 | 492 | int __init db1550_pci_setup(int id) |
f869d42e | 493 | { |
24e8c1a6 ML |
494 | if (id) |
495 | db1550_pci_pd.board_map_irq = pb1550_map_pci_irq; | |
f869d42e ML |
496 | return platform_device_register(&db1550_pci_host_dev); |
497 | } | |
f869d42e | 498 | |
24e8c1a6 | 499 | static void __init db1550_devices(void) |
f869d42e | 500 | { |
24e8c1a6 | 501 | alchemy_gpio_direction_output(203, 0); /* red led on */ |
f869d42e | 502 | |
70342287 RB |
503 | irq_set_irq_type(AU1550_GPIO0_INT, IRQ_TYPE_EDGE_BOTH); /* CD0# */ |
504 | irq_set_irq_type(AU1550_GPIO1_INT, IRQ_TYPE_EDGE_BOTH); /* CD1# */ | |
505 | irq_set_irq_type(AU1550_GPIO3_INT, IRQ_TYPE_LEVEL_LOW); /* CARD0# */ | |
506 | irq_set_irq_type(AU1550_GPIO5_INT, IRQ_TYPE_LEVEL_LOW); /* CARD1# */ | |
f869d42e ML |
507 | irq_set_irq_type(AU1550_GPIO21_INT, IRQ_TYPE_LEVEL_LOW); /* STSCHG0# */ |
508 | irq_set_irq_type(AU1550_GPIO22_INT, IRQ_TYPE_LEVEL_LOW); /* STSCHG1# */ | |
509 | ||
24e8c1a6 ML |
510 | db1x_register_pcmcia_socket( |
511 | AU1000_PCMCIA_ATTR_PHYS_ADDR, | |
512 | AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1, | |
513 | AU1000_PCMCIA_MEM_PHYS_ADDR, | |
514 | AU1000_PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1, | |
515 | AU1000_PCMCIA_IO_PHYS_ADDR, | |
516 | AU1000_PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1, | |
e34b6fcf | 517 | AU1550_GPIO3_INT, 0, |
24e8c1a6 ML |
518 | /*AU1550_GPIO21_INT*/0, 0, 0); |
519 | ||
520 | db1x_register_pcmcia_socket( | |
521 | AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004000000, | |
522 | AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004400000 - 1, | |
523 | AU1000_PCMCIA_MEM_PHYS_ADDR + 0x004000000, | |
524 | AU1000_PCMCIA_MEM_PHYS_ADDR + 0x004400000 - 1, | |
525 | AU1000_PCMCIA_IO_PHYS_ADDR + 0x004000000, | |
526 | AU1000_PCMCIA_IO_PHYS_ADDR + 0x004010000 - 1, | |
e34b6fcf | 527 | AU1550_GPIO5_INT, 1, |
24e8c1a6 ML |
528 | /*AU1550_GPIO22_INT*/0, 0, 1); |
529 | ||
530 | platform_device_register(&db1550_nand_dev); | |
531 | ||
532 | alchemy_gpio_direction_output(202, 0); /* green led on */ | |
533 | } | |
534 | ||
535 | static void __init pb1550_devices(void) | |
536 | { | |
537 | irq_set_irq_type(AU1550_GPIO0_INT, IRQ_TYPE_LEVEL_LOW); | |
538 | irq_set_irq_type(AU1550_GPIO1_INT, IRQ_TYPE_LEVEL_LOW); | |
539 | irq_set_irq_type(AU1550_GPIO201_205_INT, IRQ_TYPE_LEVEL_HIGH); | |
540 | ||
541 | /* enable both PCMCIA card irqs in the shared line */ | |
542 | alchemy_gpio2_enable_int(201); /* socket 0 card irq */ | |
543 | alchemy_gpio2_enable_int(202); /* socket 1 card irq */ | |
544 | ||
545 | /* Pb1550, like all others, also has statuschange irqs; however they're | |
546 | * wired up on one of the Au1550's shared GPIO201_205 line, which also | |
70342287 | 547 | * services the PCMCIA card interrupts. So we ignore statuschange and |
24e8c1a6 ML |
548 | * use the GPIO201_205 exclusively for card interrupts, since a) pcmcia |
549 | * drivers are used to shared irqs and b) statuschange isn't really use- | |
550 | * ful anyway. | |
551 | */ | |
552 | db1x_register_pcmcia_socket( | |
553 | AU1000_PCMCIA_ATTR_PHYS_ADDR, | |
554 | AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1, | |
555 | AU1000_PCMCIA_MEM_PHYS_ADDR, | |
556 | AU1000_PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1, | |
557 | AU1000_PCMCIA_IO_PHYS_ADDR, | |
558 | AU1000_PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1, | |
559 | AU1550_GPIO201_205_INT, AU1550_GPIO0_INT, 0, 0, 0); | |
560 | ||
561 | db1x_register_pcmcia_socket( | |
562 | AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x008000000, | |
563 | AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x008400000 - 1, | |
564 | AU1000_PCMCIA_MEM_PHYS_ADDR + 0x008000000, | |
565 | AU1000_PCMCIA_MEM_PHYS_ADDR + 0x008400000 - 1, | |
566 | AU1000_PCMCIA_IO_PHYS_ADDR + 0x008000000, | |
567 | AU1000_PCMCIA_IO_PHYS_ADDR + 0x008010000 - 1, | |
568 | AU1550_GPIO201_205_INT, AU1550_GPIO1_INT, 0, 0, 1); | |
569 | ||
570 | pb1550_nand_setup(); | |
571 | } | |
572 | ||
573 | int __init db1550_dev_setup(void) | |
574 | { | |
575 | int swapped, id; | |
415e0fec | 576 | struct clk *c; |
24e8c1a6 ML |
577 | |
578 | id = (BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI)) != BCSR_WHOAMI_DB1550); | |
579 | ||
f869d42e ML |
580 | i2c_register_board_info(0, db1550_i2c_devs, |
581 | ARRAY_SIZE(db1550_i2c_devs)); | |
582 | spi_register_board_info(db1550_spi_devs, | |
583 | ARRAY_SIZE(db1550_i2c_devs)); | |
584 | ||
415e0fec ML |
585 | c = clk_get(NULL, "psc0_intclk"); |
586 | if (!IS_ERR(c)) { | |
c02a505e | 587 | clk_set_rate(c, 50000000); |
415e0fec ML |
588 | clk_prepare_enable(c); |
589 | clk_put(c); | |
590 | } | |
591 | c = clk_get(NULL, "psc2_intclk"); | |
592 | if (!IS_ERR(c)) { | |
c02a505e | 593 | clk_set_rate(c, db1550_spi_platdata.mainclk_hz); |
415e0fec ML |
594 | clk_prepare_enable(c); |
595 | clk_put(c); | |
596 | } | |
597 | ||
f869d42e ML |
598 | /* Audio PSC clock is supplied by codecs (PSC1, 3) FIXME: platdata!! */ |
599 | __raw_writel(PSC_SEL_CLK_SERCLK, | |
600 | (void __iomem *)KSEG1ADDR(AU1550_PSC1_PHYS_ADDR) + PSC_SEL_OFFSET); | |
601 | wmb(); | |
602 | __raw_writel(PSC_SEL_CLK_SERCLK, | |
603 | (void __iomem *)KSEG1ADDR(AU1550_PSC3_PHYS_ADDR) + PSC_SEL_OFFSET); | |
604 | wmb(); | |
605 | /* SPI/I2C use internally supplied 50MHz source */ | |
606 | __raw_writel(PSC_SEL_CLK_INTCLK, | |
607 | (void __iomem *)KSEG1ADDR(AU1550_PSC0_PHYS_ADDR) + PSC_SEL_OFFSET); | |
608 | wmb(); | |
609 | __raw_writel(PSC_SEL_CLK_INTCLK, | |
610 | (void __iomem *)KSEG1ADDR(AU1550_PSC2_PHYS_ADDR) + PSC_SEL_OFFSET); | |
611 | wmb(); | |
612 | ||
24e8c1a6 | 613 | id ? pb1550_devices() : db1550_devices(); |
f869d42e | 614 | |
24e8c1a6 ML |
615 | swapped = bcsr_read(BCSR_STATUS) & |
616 | (id ? BCSR_STATUS_PB1550_SWAPBOOT : BCSR_STATUS_DB1000_SWAPBOOT); | |
f869d42e ML |
617 | db1x_register_norflash(128 << 20, 4, swapped); |
618 | ||
619 | return platform_add_devices(db1550_devs, ARRAY_SIZE(db1550_devs)); | |
620 | } |