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MIPS: Alchemy: Single kernel for DB1200/1300/1550
[mirror_ubuntu-bionic-kernel.git] / arch / mips / alchemy / devboards / db1550.c
CommitLineData
f869d42e
ML		 1/*
2 * Alchemy Db1550 board support
3 *
4 * (c) 2011 Manuel Lauss <manuel.lauss@googlemail.com>
5 */
6
7#include <linux/dma-mapping.h>
8#include <linux/gpio.h>
9#include <linux/i2c.h>
10#include <linux/init.h>
11#include <linux/io.h>
12#include <linux/interrupt.h>
13#include <linux/mtd/mtd.h>
14#include <linux/mtd/nand.h>
15#include <linux/mtd/partitions.h>
16#include <linux/platform_device.h>
17#include <linux/pm.h>
18#include <linux/spi/spi.h>
19#include <linux/spi/flash.h>
20#include <asm/mach-au1x00/au1000.h>
21#include <asm/mach-au1x00/au1xxx_eth.h>
22#include <asm/mach-au1x00/au1xxx_dbdma.h>
23#include <asm/mach-au1x00/au1xxx_psc.h>
24#include <asm/mach-au1x00/au1550_spi.h>
25#include <asm/mach-db1x00/bcsr.h>
26#include <prom.h>
27#include "platform.h"
28
f869d42e
ML		 29static void __init db1550_hw_setup(void)
30{
31 void __iomem *base;
32
33 alchemy_gpio_direction_output(203, 0); /* red led on */
34
35 /* complete SPI setup: link psc0_intclk to a 48MHz source,
36 * and assign GPIO16 to PSC0_SYNC1 (SPI cs# line)
37 */
38 base = (void __iomem *)SYS_CLKSRC;
39 __raw_writel(__raw_readl(base) | 0x000001e0, base);
40 base = (void __iomem *)SYS_PINFUNC;
41 __raw_writel(__raw_readl(base) | 1, base);
42 wmb();
43
44 /* reset the AC97 codec now, the reset time in the psc-ac97 driver
45 * is apparently too short although it's ridiculous as it is.
46 */
47 base = (void __iomem *)KSEG1ADDR(AU1550_PSC1_PHYS_ADDR);
48 __raw_writel(PSC_SEL_CLK_SERCLK | PSC_SEL_PS_AC97MODE,
49 base + PSC_SEL_OFFSET);
50 __raw_writel(PSC_CTRL_DISABLE, base + PSC_CTRL_OFFSET);
51 wmb();
52 __raw_writel(PSC_AC97RST_RST, base + PSC_AC97RST_OFFSET);
53 wmb();
54
55 alchemy_gpio_direction_output(202, 0); /* green led on */
56}
57
bd8510df 58int __init db1550_board_setup(void)
f869d42e
ML		 59{
60 unsigned short whoami;
61
62 bcsr_init(DB1550_BCSR_PHYS_ADDR,
63 DB1550_BCSR_PHYS_ADDR + DB1550_BCSR_HEXLED_OFS);
64
65 whoami = bcsr_read(BCSR_WHOAMI);
66 printk(KERN_INFO "Alchemy/AMD DB1550 Board, CPLD Rev %d"
67 " Board-ID %d Daughtercard ID %d\n",
68 (whoami >> 4) & 0xf, (whoami >> 8) & 0xf, whoami & 0xf);
69
70 db1550_hw_setup();
bd8510df 71 return 0;
f869d42e
ML		 72}
73
74/*****************************************************************************/
75
76static struct mtd_partition db1550_spiflash_parts[] = {
77 {
78 .name = "spi_flash",
79 .offset = 0,
80 .size = MTDPART_SIZ_FULL,
81 },
82};
83
84static struct flash_platform_data db1550_spiflash_data = {
85 .name = "s25fl010",
86 .parts = db1550_spiflash_parts,
87 .nr_parts = ARRAY_SIZE(db1550_spiflash_parts),
88 .type = "m25p10",
89};
90
91static struct spi_board_info db1550_spi_devs[] __initdata = {
92 {
93 /* TI TMP121AIDBVR temp sensor */
94 .modalias = "tmp121",
95 .max_speed_hz = 2400000,
96 .bus_num = 0,
97 .chip_select = 0,
98 .mode = SPI_MODE_0,
99 },
100 {
101 /* Spansion S25FL001D0FMA SPI flash */
102 .modalias = "m25p80",
103 .max_speed_hz = 2400000,
104 .bus_num = 0,
105 .chip_select = 1,
106 .mode = SPI_MODE_0,
107 .platform_data = &db1550_spiflash_data,
108 },
109};
110
111static struct i2c_board_info db1550_i2c_devs[] __initdata = {
112 { I2C_BOARD_INFO("24c04", 0x52),}, /* AT24C04-10 I2C eeprom */
113 { I2C_BOARD_INFO("ne1619", 0x2d),}, /* adm1025-compat hwmon */
114 { I2C_BOARD_INFO("wm8731", 0x1b),}, /* I2S audio codec WM8731 */
115};
116
117/**********************************************************************/
118
119static void au1550_nand_cmd_ctrl(struct mtd_info *mtd, int cmd,
120 unsigned int ctrl)
121{
122 struct nand_chip *this = mtd->priv;
123 unsigned long ioaddr = (unsigned long)this->IO_ADDR_W;
124
125 ioaddr &= 0xffffff00;
126
127 if (ctrl & NAND_CLE) {
128 ioaddr += MEM_STNAND_CMD;
129 } else if (ctrl & NAND_ALE) {
130 ioaddr += MEM_STNAND_ADDR;
131 } else {
132 /* assume we want to r/w real data by default */
133 ioaddr += MEM_STNAND_DATA;
134 }
135 this->IO_ADDR_R = this->IO_ADDR_W = (void __iomem *)ioaddr;
136 if (cmd != NAND_CMD_NONE) {
137 __raw_writeb(cmd, this->IO_ADDR_W);
138 wmb();
139 }
140}
141
142static int au1550_nand_device_ready(struct mtd_info *mtd)
143{
144 return __raw_readl((void __iomem *)MEM_STSTAT) & 1;
145}
146
f869d42e
ML		 147static struct mtd_partition db1550_nand_parts[] = {
148 {
149 .name = "NAND FS 0",
150 .offset = 0,
151 .size = 8 * 1024 * 1024,
152 },
153 {
154 .name = "NAND FS 1",
155 .offset = MTDPART_OFS_APPEND,
156 .size = MTDPART_SIZ_FULL
157 },
158};
159
160struct platform_nand_data db1550_nand_platdata = {
161 .chip = {
162 .nr_chips = 1,
163 .chip_offset = 0,
164 .nr_partitions = ARRAY_SIZE(db1550_nand_parts),
165 .partitions = db1550_nand_parts,
166 .chip_delay = 20,
f869d42e
ML		 167 },
168 .ctrl = {
169 .dev_ready = au1550_nand_device_ready,
170 .cmd_ctrl = au1550_nand_cmd_ctrl,
171 },
172};
173
174static struct resource db1550_nand_res[] = {
175 [0] = {
176 .start = 0x20000000,
177 .end = 0x200000ff,
178 .flags = IORESOURCE_MEM,
179 },
180};
181
182static struct platform_device db1550_nand_dev = {
183 .name = "gen_nand",
184 .num_resources = ARRAY_SIZE(db1550_nand_res),
185 .resource = db1550_nand_res,
186 .id = -1,
187 .dev = {
188 .platform_data = &db1550_nand_platdata,
189 }
190};
191
192/**********************************************************************/
193
194static struct resource au1550_psc0_res[] = {
195 [0] = {
196 .start = AU1550_PSC0_PHYS_ADDR,
197 .end = AU1550_PSC0_PHYS_ADDR + 0xfff,
198 .flags = IORESOURCE_MEM,
199 },
200 [1] = {
201 .start = AU1550_PSC0_INT,
202 .end = AU1550_PSC0_INT,
203 .flags = IORESOURCE_IRQ,
204 },
205 [2] = {
206 .start = AU1550_DSCR_CMD0_PSC0_TX,
207 .end = AU1550_DSCR_CMD0_PSC0_TX,
208 .flags = IORESOURCE_DMA,
209 },
210 [3] = {
211 .start = AU1550_DSCR_CMD0_PSC0_RX,
212 .end = AU1550_DSCR_CMD0_PSC0_RX,
213 .flags = IORESOURCE_DMA,
214 },
215};
216
217static void db1550_spi_cs_en(struct au1550_spi_info *spi, int cs, int pol)
218{
219 if (cs)
220 bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_SPISEL);
221 else
222 bcsr_mod(BCSR_BOARD, BCSR_BOARD_SPISEL, 0);
223}
224
225static struct au1550_spi_info db1550_spi_platdata = {
226 .mainclk_hz = 48000000, /* PSC0 clock: max. 2.4MHz SPI clk */
227 .num_chipselect = 2,
228 .activate_cs = db1550_spi_cs_en,
229};
230
231static u64 spi_dmamask = DMA_BIT_MASK(32);
232
233static struct platform_device db1550_spi_dev = {
234 .dev = {
235 .dma_mask = &spi_dmamask,
236 .coherent_dma_mask = DMA_BIT_MASK(32),
237 .platform_data = &db1550_spi_platdata,
238 },
239 .name = "au1550-spi",
240 .id = 0, /* bus number */
241 .num_resources = ARRAY_SIZE(au1550_psc0_res),
242 .resource = au1550_psc0_res,
243};
244
245/**********************************************************************/
246
247static struct resource au1550_psc1_res[] = {
248 [0] = {
249 .start = AU1550_PSC1_PHYS_ADDR,
250 .end = AU1550_PSC1_PHYS_ADDR + 0xfff,
251 .flags = IORESOURCE_MEM,
252 },
253 [1] = {
254 .start = AU1550_PSC1_INT,
255 .end = AU1550_PSC1_INT,
256 .flags = IORESOURCE_IRQ,
257 },
258 [2] = {
259 .start = AU1550_DSCR_CMD0_PSC1_TX,
260 .end = AU1550_DSCR_CMD0_PSC1_TX,
261 .flags = IORESOURCE_DMA,
262 },
263 [3] = {
264 .start = AU1550_DSCR_CMD0_PSC1_RX,
265 .end = AU1550_DSCR_CMD0_PSC1_RX,
266 .flags = IORESOURCE_DMA,
267 },
268};
269
270static struct platform_device db1550_ac97_dev = {
271 .name = "au1xpsc_ac97",
272 .id = 1, /* PSC ID */
273 .num_resources = ARRAY_SIZE(au1550_psc1_res),
274 .resource = au1550_psc1_res,
275};
276
277
278static struct resource au1550_psc2_res[] = {
279 [0] = {
280 .start = AU1550_PSC2_PHYS_ADDR,
281 .end = AU1550_PSC2_PHYS_ADDR + 0xfff,
282 .flags = IORESOURCE_MEM,
283 },
284 [1] = {
285 .start = AU1550_PSC2_INT,
286 .end = AU1550_PSC2_INT,
287 .flags = IORESOURCE_IRQ,
288 },
289 [2] = {
290 .start = AU1550_DSCR_CMD0_PSC2_TX,
291 .end = AU1550_DSCR_CMD0_PSC2_TX,
292 .flags = IORESOURCE_DMA,
293 },
294 [3] = {
295 .start = AU1550_DSCR_CMD0_PSC2_RX,
296 .end = AU1550_DSCR_CMD0_PSC2_RX,
297 .flags = IORESOURCE_DMA,
298 },
299};
300
301static struct platform_device db1550_i2c_dev = {
302 .name = "au1xpsc_smbus",
303 .id = 0, /* bus number */
304 .num_resources = ARRAY_SIZE(au1550_psc2_res),
305 .resource = au1550_psc2_res,
306};
307
308/**********************************************************************/
309
310static struct resource au1550_psc3_res[] = {
311 [0] = {
312 .start = AU1550_PSC3_PHYS_ADDR,
313 .end = AU1550_PSC3_PHYS_ADDR + 0xfff,
314 .flags = IORESOURCE_MEM,
315 },
316 [1] = {
317 .start = AU1550_PSC3_INT,
318 .end = AU1550_PSC3_INT,
319 .flags = IORESOURCE_IRQ,
320 },
321 [2] = {
322 .start = AU1550_DSCR_CMD0_PSC3_TX,
323 .end = AU1550_DSCR_CMD0_PSC3_TX,
324 .flags = IORESOURCE_DMA,
325 },
326 [3] = {
327 .start = AU1550_DSCR_CMD0_PSC3_RX,
328 .end = AU1550_DSCR_CMD0_PSC3_RX,
329 .flags = IORESOURCE_DMA,
330 },
331};
332
333static struct platform_device db1550_i2s_dev = {
334 .name = "au1xpsc_i2s",
335 .id = 3, /* PSC ID */
336 .num_resources = ARRAY_SIZE(au1550_psc3_res),
337 .resource = au1550_psc3_res,
338};
339
340/**********************************************************************/
341
342static struct platform_device db1550_stac_dev = {
343 .name = "ac97-codec",
344 .id = 1, /* on PSC1 */
345};
346
347static struct platform_device db1550_ac97dma_dev = {
348 .name = "au1xpsc-pcm",
349 .id = 1, /* on PSC3 */
350};
351
352static struct platform_device db1550_i2sdma_dev = {
353 .name = "au1xpsc-pcm",
354 .id = 3, /* on PSC3 */
355};
356
357static struct platform_device db1550_sndac97_dev = {
358 .name = "db1550-ac97",
359};
360
361static struct platform_device db1550_sndi2s_dev = {
362 .name = "db1550-i2s",
363};
364
365/**********************************************************************/
366
f869d42e
ML		 367static int db1550_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin)
368{
369 if ((slot < 11) || (slot > 13) || pin == 0)
370 return -1;
371 if (slot == 11)
372 return (pin == 1) ? AU1550_PCI_INTC : 0xff;
373 if (slot == 12) {
374 switch (pin) {
375 case 1: return AU1550_PCI_INTB;
376 case 2: return AU1550_PCI_INTC;
377 case 3: return AU1550_PCI_INTD;
378 case 4: return AU1550_PCI_INTA;
379 }
380 }
381 if (slot == 13) {
382 switch (pin) {
383 case 1: return AU1550_PCI_INTA;
384 case 2: return AU1550_PCI_INTB;
385 case 3: return AU1550_PCI_INTC;
386 case 4: return AU1550_PCI_INTD;
387 }
388 }
389 return -1;
390}
391
392static struct resource alchemy_pci_host_res[] = {
393 [0] = {
394 .start = AU1500_PCI_PHYS_ADDR,
395 .end = AU1500_PCI_PHYS_ADDR + 0xfff,
396 .flags = IORESOURCE_MEM,
397 },
398};
399
400static struct alchemy_pci_platdata db1550_pci_pd = {
401 .board_map_irq = db1550_map_pci_irq,
402};
403
404static struct platform_device db1550_pci_host_dev = {
405 .dev.platform_data = &db1550_pci_pd,
406 .name = "alchemy-pci",
407 .id = 0,
408 .num_resources = ARRAY_SIZE(alchemy_pci_host_res),
409 .resource = alchemy_pci_host_res,
410};
411
412/**********************************************************************/
413
414static struct platform_device *db1550_devs[] __initdata = {
f869d42e
ML		 415 &db1550_nand_dev,
416 &db1550_i2c_dev,
417 &db1550_ac97_dev,
418 &db1550_spi_dev,
419 &db1550_i2s_dev,
420 &db1550_stac_dev,
421 &db1550_ac97dma_dev,
422 &db1550_i2sdma_dev,
423 &db1550_sndac97_dev,
424 &db1550_sndi2s_dev,
425};
426
427/* must be arch_initcall; MIPS PCI scans busses in a subsys_initcall */
bd8510df 428int __init db1550_pci_setup(void)
f869d42e
ML		 429{
430 return platform_device_register(&db1550_pci_host_dev);
431}
f869d42e 432
bd8510df 433int __init db1550_dev_setup(void)
f869d42e
ML		 434{
435 int swapped;
436
437 irq_set_irq_type(AU1550_GPIO0_INT, IRQ_TYPE_EDGE_BOTH); /* CD0# */
438 irq_set_irq_type(AU1550_GPIO1_INT, IRQ_TYPE_EDGE_BOTH); /* CD1# */
439 irq_set_irq_type(AU1550_GPIO3_INT, IRQ_TYPE_LEVEL_LOW); /* CARD0# */
440 irq_set_irq_type(AU1550_GPIO5_INT, IRQ_TYPE_LEVEL_LOW); /* CARD1# */
441 irq_set_irq_type(AU1550_GPIO21_INT, IRQ_TYPE_LEVEL_LOW); /* STSCHG0# */
442 irq_set_irq_type(AU1550_GPIO22_INT, IRQ_TYPE_LEVEL_LOW); /* STSCHG1# */
443
444 i2c_register_board_info(0, db1550_i2c_devs,
445 ARRAY_SIZE(db1550_i2c_devs));
446 spi_register_board_info(db1550_spi_devs,
447 ARRAY_SIZE(db1550_i2c_devs));
448
449 /* Audio PSC clock is supplied by codecs (PSC1, 3) FIXME: platdata!! */
450 __raw_writel(PSC_SEL_CLK_SERCLK,
451 (void __iomem *)KSEG1ADDR(AU1550_PSC1_PHYS_ADDR) + PSC_SEL_OFFSET);
452 wmb();
453 __raw_writel(PSC_SEL_CLK_SERCLK,
454 (void __iomem *)KSEG1ADDR(AU1550_PSC3_PHYS_ADDR) + PSC_SEL_OFFSET);
455 wmb();
456 /* SPI/I2C use internally supplied 50MHz source */
457 __raw_writel(PSC_SEL_CLK_INTCLK,
458 (void __iomem *)KSEG1ADDR(AU1550_PSC0_PHYS_ADDR) + PSC_SEL_OFFSET);
459 wmb();
460 __raw_writel(PSC_SEL_CLK_INTCLK,
461 (void __iomem *)KSEG1ADDR(AU1550_PSC2_PHYS_ADDR) + PSC_SEL_OFFSET);
462 wmb();
463
464 db1x_register_pcmcia_socket(
465 AU1000_PCMCIA_ATTR_PHYS_ADDR,
466 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
467 AU1000_PCMCIA_MEM_PHYS_ADDR,
468 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1,
469 AU1000_PCMCIA_IO_PHYS_ADDR,
470 AU1000_PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1,
471 AU1550_GPIO3_INT, AU1550_GPIO0_INT,
472 /*AU1550_GPIO21_INT*/0, 0, 0);
473
474 db1x_register_pcmcia_socket(
475 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004000000,
476 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004400000 - 1,
477 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x004000000,
478 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x004400000 - 1,
479 AU1000_PCMCIA_IO_PHYS_ADDR + 0x004000000,
480 AU1000_PCMCIA_IO_PHYS_ADDR + 0x004010000 - 1,
481 AU1550_GPIO5_INT, AU1550_GPIO1_INT,
482 /*AU1550_GPIO22_INT*/0, 0, 1);
483
484 swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1000_SWAPBOOT;
485 db1x_register_norflash(128 << 20, 4, swapped);
486
487 return platform_add_devices(db1550_devs, ARRAY_SIZE(db1550_devs));
488}
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